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risc

Here are 262 public repositories matching this topic...

JCLemme / eprisc-open-computer

An open-source computer

cpu fpga assembler computer altera risc bios

Updated Mar 4, 2019
C++

redthing1 / irre-tools

toy handwritten assembler, emulator, compiler, toolchain for a lightweight RISC architecture

emulator virtual-machine architecture assembler risc vbcc irre regularvm

Updated Oct 16, 2023
D

Unnamed-Simulator

tong-ece-cmu / Unnamed-Simulator

What's that weird looking CPU?

cpu hardware processor architecture verilog isa vivado systemverilog risc systemc

Updated May 26, 2021
C++

fabiankuffer / RISC-V-QR-Code-Generator

Minimal implementation of a QR code generator in Assembly for RISC-V architectures.

assembly qr-code risc qrcode-generator rars risc-v-assembly

Updated Nov 5, 2021
Assembly

EmperorPenguin18 / assembler

Mini SRC assembler for school project

c cli fpga assembly assembler risc c-language c-lang fpga-programming

Updated Apr 25, 2022
C

allkern / hv1

A simple 32-bit RISC architecture designed from the ground up for swift development for both compilers and humans

emulator cpu emulation low-level risc

Updated Sep 24, 2022
C++

jamesrosssharp / SLURM

16 bit games console system-on-chip

cplusplus rust-lang verilog game-console risc 16-bit-cpu

Updated Dec 9, 2023
Assembly

IOInfinityStudio / Docker-Nignx-RISC-V

If you want to run Nginx on a RISC-V architecture computer, you can use a Docker container to simplify the process and ensure compatibility.

docker nginx docker-compose docker-container docker-image container risc nginx-server risc-v nginx-docker riscv32 riscv64

Updated Mar 28, 2023
Dockerfile

KamilMarszalek / Third-degree-polynomial

RISC-V assembly student project

Updated May 13, 2024
Assembly

captaindane / swt16

A 16-bit, 5-stage RISC processor. RTL description in Verilog. Includes assembler, simulator, and example programs.

simulation processor assembler verilog isa risc 16-bit 5-stage-pipeline rtl-description

Updated Feb 5, 2020
Verilog

nicolavianello95 / DLX

Design and development of a complete RISC CPU with: five stage pipeline, forwarding, automatic hazard detection, BTB using LRU policy replacement, four-cycle hardware multiplier.

cpu mips vhdl microprocessor forwarding computer-architecture hazard-detection risc dlx multiplier branch-predictor digital-electronics btb bht

Updated Dec 10, 2019
VHDL

jamestiotio / compstruct

SUTD 2020 50.002 Computation Structures Code Dump

cpu fpga hardware beta os operating-system turing-machine lucid computer-architecture risc turing-machine-simulator netlist instruction-set-architecture instruction-set digital-systems hardware-description-language computation-structures netlist-simulator central-processing-unit

Updated Apr 7, 2022
C

ntsdwkr / MIPS

Single Cycle MIPS (RISC) Processor

mips verilog risc risc-v mips32 single-cycle-processor

Updated Jan 30, 2024
Verilog

SKpro-glitch / Shorthand-RISC

This is a simplified assembly language with a tabular structured instruction set. This is meant for easy learning and fast implementation of assembly languages in microprocessors and microcontrollers. - Soham Kapur, VIT Chennai

compiler assembly assembler riscv assembly-language compilers compiler-principles shorthand assembly-language-programming risc compiler-design risc-v compiler-optimization compiler-construction shorthand-notation risc-processor shorthand-syntax

Updated Jul 14, 2024
Java

Kaweees / kiwiRTOS

⏰ A Real-Time Operating System (RTOS) designed for embedded applications with targets for RISC-V (RV32I, RV64I) and ARM written in Zig (🚧 in construction 🚧)

zig os bootloader risc rtos risc-v

Updated Oct 24, 2024
Zig

Fiser12 / Procesador-Segmentado

Procesador RISC segmentado creado con Proteus con Unidad de control, 5 segmentos, corrección de errores mediante unidad de detección de conflictos (DC) y ALU.

processor risc proteus risc-processor

Updated Jun 30, 2016

elvircrn / MIPS

python simulator pipeline mips risc

Updated May 21, 2017
Python

usnwoody / Assembly

Coding in Assembly for university projects

assembly mips-assembly risc mips-architecture

Updated Apr 18, 2018
Assembly

alifarazz / RISCImposter

🐚 low level cycle accurate RISC simulator

simulator mips cycle-accurate risc c11

Updated May 11, 2019
C

ptia / BrainHack

Brainfuck CPU for ICHack19

cpu brainfuck verilog risc

Updated Feb 9, 2019
Verilog

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