sram
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ARM processor pipeline implementation. Featuring hazard unit, forwarding unit, SRAM & cache memory.
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Feb 1, 2024 - Verilog
This repo contains golden vector and randomization testbenches for SRAM module.
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Aug 2, 2020 - Verilog
A bare-metal SRAM memory controller suitable for Xilinx FPGAs.
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Jan 15, 2024 - Verilog
A 32-bit Arm Processor Using Verilog HDL With Hazard Detection, Forwarding Unit, SRAM Memory & A 2-Way Set-Associative Cache.
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Jul 22, 2021 - Verilog
ARM processor implementation, hazard unit, forwarding unit, SRAM & cache memory.
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Jul 24, 2023 - Verilog
Projects of the computer architecture lab (Spring 02) at the University of Tehran.
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Oct 6, 2023 - Verilog
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