Here are
17 public repositories
matching this topic...
The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.
Updated
Oct 21, 2024
Verilog
ARM processor pipeline implementation. Featuring hazard unit, forwarding unit, SRAM & cache memory.
Updated
Feb 1, 2024
Verilog
A bare-metal SRAM memory controller suitable for Xilinx FPGAs.
Updated
Jan 15, 2024
Verilog
Projects of the computer architecture lab (Spring 02) at the University of Tehran.
Updated
Oct 6, 2023
Verilog
ARM processor implementation, hazard unit, forwarding unit, SRAM & cache memory.
Updated
Jul 24, 2023
Verilog
SRAM macros created for the GF180MCU provided by GlobalFoundries.
Updated
Apr 10, 2023
Verilog
Updated
Feb 22, 2023
Verilog
Updated
Feb 21, 2023
Verilog
Eight different verilog projects are combined to creat a big custom asic project.
Updated
Jan 8, 2023
Verilog
Computer architecture lab ARM processor with Verilog.
Updated
Oct 5, 2022
Verilog
🎓💻University of Tehran Computer Architecture Lab Course Projects - Spring 2022
Updated
Jul 15, 2022
Verilog
A 32-bit Arm Processor Using Verilog HDL With Hazard Detection, Forwarding Unit, SRAM Memory & A 2-Way Set-Associative Cache.
Updated
Jul 22, 2021
Verilog
Various HDL (Verilog) IP Cores
Updated
Jul 1, 2021
Verilog
This repo contains golden vector and randomization testbenches for SRAM module.
Updated
Aug 2, 2020
Verilog
Updated
May 6, 2020
Verilog
Updated
May 27, 2019
Verilog
2D GPU made using Verilog
Updated
Sep 16, 2017
Verilog
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