VUnit is a unit testing framework for VHDL/SystemVerilog

Various HDL (Verilog) IP Cores

Python-based Hardware Design Processing Toolkit for Verilog HDL

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 7…

HDL support for VS Code

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

This Repository invites freelancer friendly neighbourhood developers to contribute to open source .

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

High throughput JPEG decoder in Verilog for FPGA

Gigabit Ethernet UDP communication driver

Image Processing Toolbox in Verilog using Basys3 FPGA

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

A complete open-source design-for-testing (DFT) Solution

This is a tutorial on standard digital design flow

This repository hosts the code for an FPGA based accelerator for convolutional neural networks

中山大学计算机组成原理实验 (2018 秋)：用 Verilog 设计并实现的简易单周期和多周期 CPU

An efficient implementation of the Viterbi decoding algorithm in Verilog

A simple implementation of a UART modem in Verilog.

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL