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Firmware m0803
Target
Purpose
Versions
Structure
Boot process
OS and Libraries
Flashing
Interfaces
The firmware is loaded as bitstream into Lattice MachX FPGA, being stored either in serial flash chip or a SoC which controlls it. Location of the target chip:
- in WM220, LCMXO2 FPGA; is on WM220 Core Board A
- in WM330, LCMXO3L FPGA; is on WM330 Receiver Main Processor 3-in-1 board
- in other products, the location is unknown
Used as additional support for collision avoidance and intelligent flight, the FPGA provides a real-time processing of some related information. Details are not known.
TODO
The module contains the FPGA bitstream in ECP5 format proprietary to Lattice FPGAs.
The module file start with ECP5 preamable, 0xFFFFBDB3.
No analysis of the booting procedure were performed.
The module uses IP core integrated with Lattice Synthesis Engine synthesis process.
TODO
TODO
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If you see a mistake, or you know more about specific subject, or you see an area for improvement for the wiki - create an issue in this project and attach your patch (or describe the change you propose).