RISC-V CPU Core (RV32IM)
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Updated
Sep 18, 2021 - Verilog
RISC-V CPU Core (RV32IM)
32-bit Superscalar RISC-V CPU
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
"High density" digital standard cells for SKY130 provided by SkyWater.
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
FPGA CryptoNight V7 Minner
IC implementation of Systolic Array for TPU
Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
Custom chips reverse-engineered from silicon
Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
7 track standard cells for GF180MCU provided by GlobalFoundries.
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