uvm framework generator

Examples with UVM

Fully synthesizable and paramterizable, IEEE-754 compliant Floating Point Unit (FPU) in systemverilog. Supports fused multiply add, division and square root operations.

Superscalar dual-issue RISC-V processor

This repository documents a project undertaken as part of the EN2111 Electronic Circuit Design module at the University of Moratuwa, focusing on the implementation of a UART communication link between two FPGA boards.

Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

First and Last Project for STRUCTURED DESIGN OF INTEGRATED CIRCUITS discipline at UFPB. 24h clock with system verilog + Functional verification.

FIFO, FSM, UART, RAM, ALU, etc.

32-bit Single Precision Floating point Multiplication

Desarrollo de un circuito decodificador de Gray por medio del HDL SystemVerilog

100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore

Project for the class "Digital Low-level Hardware Systems II" in SystemVerilog.

System Verilog BootCamp

Repository of homeworks and projects of the verification class from Bootcamp Pre-Silicon at ITESO with INTEL

Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster

It's a simple verilog based MIPS microarchitecture hardware design.

This is a tutorial for OVM (Open Verification Methodology) testbench .

Implements a simple UVM based testbench for a simple memory DUT.

Functional verification using SystemVerilog's HVL feature