OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

An abstraction library for interfacing EDA tools

FPGA tool performance profiling

Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe

A Python package to use FPGA development tools programmatically.

RealtimeIO for LinuxCNC based on an FPGA

Unofficial Yosys WebAssembly packages

Sphinx Extension which generates various types of diagrams from Verilog code.

HDL development environment on Nix.

An interactive digital logic simulator with verilog support (Yosys)

Example of how to get started with olofk/fusesoc.

Solving Sudokus using open source formal verification tools

A modern hardware definition language and toolchain based on Python

WIP open source tooling for the XC9500 / XC9500XL series of CPLDs from Xilinx.

VHDL / System Verilog to Verilog converter, based on Yosys and the plugins ghdl-yosys-plugin and synlig.

6502 CPU implementation written in nMigen

Synthesize Verilog to Minecraft redstone

A Python library, and CLI utilities, which solves HDL-to-bitstream based on FOSS.

SAK = Swiss Army Knife - Various scripts and utilities around popular FOSS EDA