🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

A small, light weight, RISC CPU soft core

An FPGA-based AXI4 DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

💻 A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.

An open-source 32-bit RISC-V soft-core processor

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

Open source ISS and logic RISC-V 32 bit project

Basic UART TX/RX module for FPGA

A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA

LatticeMico32 instruction set simulator project

Uzh compiler

The Zylin ZPU

Soft core with support for the AVR8 instructions on verilog

RISC-V processor in compliance with RV32IMZicsr

Implementation of MIPS Processor Modules Using Verilog

How to build Zylin ZPU's GCC toolchain with Windows WSL 2022

16-bit MIPS Processor from scratch in VHDL

Trying to implement a soft core SoC

SRP16 is free and open ISA for 16-bit CPUs and Microcontrollers.