ghdl
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✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
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Oct 30, 2024 - Python
Time domain to logarithmic frequency domain converter, as the polyphase FFT do for the linear.
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Oct 24, 2024 - VHDL
High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
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Oct 22, 2024 - VHDL
Fun project to produce (only) pulses as the MultiSignalGene do, with analogue circuits and FPGA or 74HC logic circuits.
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Oct 6, 2024 - VHDL
GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.
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Oct 3, 2024 - C++
An abstraction library for interfacing EDA tools
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Aug 22, 2024 - Python
Custom 64-bit pipelined RISC processor
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Jul 18, 2024 - VHDL
Easy and fast VHDL simulation tool, integrating GHDL and GTKWave
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Jun 16, 2024 - PHP
Repurposing existing HDL tools to help writing better code
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Jun 6, 2024 - Python
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