Hardware Fidelity and Emulation Boundaries

Hardware Fidelity & Emulation Boundaries

xemu does not emulate every transistor, motherboard trace, pull-up resistor, bus clock edge, or piece of analog circuitry in the original Xbox. It emulates the software-visible contract of the machine at several different fidelity levels, then uses host services to realize effects that the guest expects.

That distinction is important for debugging and performance work. A register access that took time on physical hardware may complete synchronously in xemu. A physical pin transition may be represented by directly setting a status bit. A device can expose a register file while omitting the analog hardware behind those registers. Conversely, a host backend can introduce synchronization or scheduling costs that did not exist in the same form on the Xbox.

This page records those boundaries so emulator behavior is not mistaken for literal motherboard behavior.

Fidelity levels used in xemu

Level	What xemu models	Typical example
Architectural	Guest-visible CPU/device semantics at instruction/register level	x86 CPU state, PCI configuration, NV2A registers
Functional / semantic	The result software expects, without reproducing the physical mechanism	SMC power request becoming a QEMU reset request
Register façade	Software can read/write a plausible device register file, but major physical behavior behind it is absent	Current Conexant/Focus/Xcalibur SMBus encoder models
Host-service substitution	Guest hardware behavior is mapped onto a host API or service	NVNet → QEMU network backend, APU → SDL audio stream, NV2A → OpenGL/Vulkan
Compatibility workaround	xemu intentionally differs internally from hardware to preserve the guest-observed result	Writable MCPX boot-ROM overlay for an early-boot cache-dependent kernel quirk
Stub / partial model	Enough identity or state exists for software probing, but the device is incomplete	Current memory-controller placeholder

The fidelity level is not a quality ranking by itself. Emulating an analog signal electrically would often add cost without helping software compatibility. The important question is whether the omitted behavior can become guest-visible.

Physical hardware versus emulator path

flowchart LR
    subgraph Xbox[Physical Xbox]
        A[CPU / device logic] --> B[Register or bus transaction]
        B --> C[Chip / board signal]
        C --> D[Physical device behavior]
        D --> E[IRQ / register / DMA result]
    end

    subgraph xemu[xemu]
        F[Translated guest code] --> G[MMIO / I/O callback]
        G --> H[Device model]
        H --> I{Required fidelity}
        I -->|Register semantics| J[Update emulated state]
        I -->|Host effect| K[Host API / renderer / audio / network]
        I -->|Shortcut| L[Direct semantic result]
        J --> M[IRQ / register / DMA result]
        K --> M
        L --> M
    end

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A useful code-review question is therefore not only “does this match the schematic?” but also:

What can Xbox software observe, and which xemu implementation path produces that observation?

Motherboard pins are not generally simulated as wires

xemu usually does not create a software object for every physical motherboard pin. Pins become worth modeling when software can observe the resulting state through a register, interrupt, DMA engine, or attached device.

The real Xbox LPC debug header exposes signals such as LAD[3:0], LFRAME#, LRESET#, LCLK, SMBus SCL/SDA, power rails, and revision-dependent pins. The current machine model instead exposes the corresponding logical buses and device behavior through QEMU PCI/LPC/SMBus abstractions. There is no per-edge electrical LPC simulation in the normal access path.

Hardware reference: XboxDevWiki — LPC Debug Port.

flowchart TD
    A[Physical LPC pins / traces] -->|hardware| B[MCPX / LPC peripheral]
    B --> C[software-visible I/O/register result]

    D[Guest IN/OUT or PCI config access] -->|xemu| E[QEMU I/O MemoryRegion]
    E --> F[Xbox LPC / PCI device model]
    F --> C

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This is why host traces should not be interpreted as LPC bus-cycle timings. xemu is reproducing the transaction semantics at a higher abstraction level.

LPC debug-port pin map and revision caveats

The physical LPC debug footprint is an unpopulated 2×8 header. This is one of the places where “motherboard access” can be described concretely rather than as a generic bus.

Pin	Signal	Physical role / revision note
1	LCLK	33 MHz LPC/PCI-derived clock
2	GND	Ground
3	LFRAME#	Start/termination of LPC cycle; disconnected on v1.3–v1.5 unless rebuilt
4	PWR on v1.6	Connected to power button on v1.6; absent on earlier boards
5	LRESET#	LPC reset / same logical reset family as PCIRST#
6	5V	5 V supply; behavior differs on v1.6 with AC present
7	LAD3	Multiplexed LPC address/data
8	LAD2	Multiplexed LPC address/data
9	3.3V	3.3 V supply; disconnected on v1.6
10	LAD1	Multiplexed LPC address/data
11	LAD0	Multiplexed LPC address/data
12	GND	Ground
13	SCL	SMBus clock
14	SDA	SMBus data/address
15	3.3V	3.3 V supply
16	SERIRQ on early hardware	Serial IRQ signal documented for early/debug configurations

Hardware reference: XboxDevWiki — LPC Debug Port.

The header omits several optional LPC signals, so an add-on device connected only through this footprint does not automatically have the same DMA, bus-mastering, power-management or interrupt capabilities as an internally integrated MCPX function. xemu's logical LPC/ISA/PCI device topology should therefore not be mistaken for a literal simulation of what an arbitrary peripheral soldered to this header can do.

flowchart TD
    A[Physical 2x8 LPC header] --> B[LCLK / LFRAME# / LAD3:0 / LRESET#]
    A --> C[SCL / SDA]
    A --> D[Power / ground / revision pins]
    B --> E[MCPX LPC controller]
    C --> F[MCPX SMBus controller]

    G[xemu] --> H[QEMU PCI/LPC/ISA abstractions]
    G --> I[QEMU SMBus transactions]
    H --> J[Same software-visible register/I/O contract]
    I --> J

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Development-kit Super I/O versus retail machine

Some Xbox development kits can attach an SMSC LPC47M157 Super I/O board to the LPC debug port for serial kernel debugging. xemu contains an lpc47m157 device model with configuration ports and serial cores.

The implementation supports the Super I/O configuration protocol (0x55 enter, 0xAA exit), logical-device register selection, COM base/IRQ configuration, and two QEMU serial cores. Other logical-device identities exist in the register model, but update_devices() currently realizes only the serial functions.

The normal retail Xbox machine construction in hw/xbox/xbox.c does not directly instantiate this Super I/O device. Its presence in the source tree should therefore not be read as “every emulated retail Xbox has a Super I/O chip.”

Hardware reference: XboxDevWiki — Super I/O.

PC speaker: MCPX pin exists, speaker does not

The hardware distinction is precise: MCPX pin L21 carries a PC-speaker signal controlled through the standard PC-speaker/PIT interface, but a stock Xbox has no speaker connected to that pin. As a result, software can drive the signal on real hardware without producing audible sound unless a speaker is physically attached. Hardware reference: XboxDevWiki — MCPX, Pin L21: PC Speaker.

xemu machine initialization links QEMU's PC-speaker device to the PIT and realizes the speaker on the ISA bus:

flowchart LR
    A[Guest PIT / speaker-port programming] --> B{Physical Xbox}
    B --> C[MCPX L21 speaker signal]
    C --> D[No stock transducer attached]

    A --> E{xemu}
    E --> F[QEMU PIT]
    F --> G[QEMU pcspk device]
    G --> H[Host-audible emulation path]

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This means xemu intentionally exposes the logical PC-speaker output without reproducing the stock board's disconnected transducer. For compatibility this is useful: software exercising the interface has something observable in the emulator. For fidelity/performance analysis it is important not to describe pcspk as analog simulation of a speaker physically present in a retail console.

SMC: physical microcontroller replaced by a semantic device model

On retail hardware the System Management Controller is a PIC-family microcontroller connected over SMBus. It handles power/eject buttons, tray state, fan control, front LED behavior, A/V-pack detection, temperature-related functions, and boot challenge behavior. Hardware reference: XboxDevWiki — System Management Controller.

xemu models the software-facing SMBus device at address 0x10, but it does not execute PIC firmware instruction-by-instruction.

Button path

Physical hardware is approximately:

front-panel button
    ↓ electrical input
SMC/PIC firmware
    ↓
SMC interrupt/status state
    ↓
chipset interrupt path
    ↓
Xbox kernel

xemu currently uses a much shorter semantic path:

sequenceDiagram
    participant U as xemu UI/input
    participant S as SMBus SMC model
    participant A as ACPI/LPC event path
    participant C as Guest CPU

    U->>S: xbox_smc_power_button() / eject_button()
    S->>S: Set INTSTATUS bit
    S->>A: Raise external-SMI event
    A-->>C: Guest-visible event/IRQ path

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There is no simulated front-panel voltage transition and no emulated PIC firmware loop between the UI event and the status/SMI result.

Implemented and omitted SMC behavior

The current SMC source defines registers for fan mode/speed, LED mode/sequence, temperatures, tray eject, interrupt enable, reset-on-eject and other functions. The presence of a register constant does not mean the physical function is implemented.

Current behavior includes:

Area	Current xemu behavior
Version string	Configured three-character version, sequential reads
Power register	Directly requests QEMU reset/power-cycle or shutdown
Tray state	Derived from the QEMU optical block backend
A/V pack	Machine property exposed as SMC register value
Scratch/error registers	Stored in SMC model
Interrupt status	Stored bits; current implementation clears on read with a source FIXME to confirm hardware behavior
Boot challenge request	Returns fixed bytes rather than generating a hardware/PIC random challenge
Challenge response writes	Accepted but not cryptographically validated
Fan/LED/tray-eject controls	Constants exist, but most writes currently fall through without reproducing the physical action
Temperature	SMC-side physical thermal system is not simulated

The tray-state path also contains a source FIXME: instead of being driven by a general tray-change callback, it is explicitly refreshed from UI interaction.

These are compatibility boundaries, not merely missing UI features. Software that depends on exact SMC timing, challenge behavior, LED/fan side effects, or event ordering can expose the difference.

SMBus: transaction semantics without wire time

The physical SMBus transfers bits over SCL and SDA. xemu's AMD756-compatible controller instead performs the selected SMBus operation synchronously when guest software writes the host-controller start bit.

flowchart TD
    A[Guest programs SMBus registers] --> B[Write GLOBAL_ENABLE / START]
    B --> C[amd756_smb_transaction]
    C --> D{Protocol}
    D --> E[QEMU SMBus helper]
    E --> F[Target device callback]
    F --> G[Completion/error status updated]
    G --> H[Optional IRQ]

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There is no modeled bit clock, arbitration delay, line capacitance, pull-up rise time, or per-byte transfer duration in that path. As a result:

• SMBus-heavy guest code can complete faster than literal hardware bus timing would suggest.
• Profiles measure callback/register cost, not simulated electrical bus latency.
• Adding artificial host sleeps to “match bus speed” would be the wrong abstraction unless software-visible timing requires it; a virtual deadline/device state machine would be preferable.

Temperature monitor is a compatibility façade

For non-Xcalibur machine configurations xemu creates an ADM1032-compatible SMBus device. The current implementation returns a fixed value of 50 for its two implemented temperature reads and 0 for other unhandled commands.

Guest reads temperature
    ↓
SMBus device callback
    ↓
return constant 50

There is no thermal model coupling host CPU/GPU utilization, fan speed, virtual silicon temperature, or elapsed time. This makes temperature access deterministic and inexpensive, but software testing thermal-management behavior cannot treat it as a physical simulation.

Video encoders currently behave mostly as register stores

The Conexant CX25871, Focus FS454, and Xcalibur SMBus devices currently maintain a 256-byte register array and command pointer. Writes copy values into the array; reads return them. The analog video encoder, DAC behavior, signal timing, cable loading and physical output circuitry are not simulated by those SMBus files.

This is a useful example of a register façade:

Guest encoder register write
    ↓
SMBus callback
    ↓
store byte in emulated register array
    ↓
later guest read sees stored value

The rendered picture comes from NV2A/display/presentation logic, not from an electrical simulation of the encoder chip.

GPIO and the TV field pin

hw/xbox/acpi_xbox.c exposes a GPIO I/O region. One particularly important approximation is the field-pin read at GPIO offset zero:

field_pin = (field_pin + 1) & 1;
r = field_pin << 5;

The value simply toggles every time software reads it. It is not currently driven by an emulated encoder scan field, raster position, or physical pin transition.

flowchart LR
    A[Guest reads PM GPIO offset 0] --> B[xbox_pm_gpio_read]
    B --> C[Toggle static field_pin]
    C --> D[Return bit 5]

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This can matter to polling loops: guest behavior depends on number of reads, not a faithful video-field clock.

The same GPIO model maps an aspect-ratio write at offset 0x16 directly to xemu_set_widescreen(val == 5), crossing immediately from emulated register state into host/UI policy. The source also carries FIXME: Add GPIO to VM state, so this state deserves care around snapshots.

Generic PC devices reused by the Xbox model

Some original Xbox components are PC-compatible enough that xemu reuses existing QEMU devices rather than implementing them from electrical schematics. Examples include:

• i8259 PIC.
• i8254 PIT.
• mc146818 RTC.
• i8257 DMA controller.
• PIIX3-style IDE controller.
• generic OHCI USB controllers.

The original Xbox hardware overview notes that several of these blocks are PC-compatible, although details can differ—for example the legacy timer frequency is documented as differing from a standard PC. Hardware reference: XboxDevWiki — Xbox Hardware Overview.

Reusing a QEMU device is a behavioral substitution, not proof that the physical chip package on the motherboard was literally the same QEMU model.

Memory controller placeholder

Current xbox_init_common() still creates a pci-testdev for the memory-controller function with the source comment:

FIXME: Stub the memory controller

This is a direct example of an enumerated platform identity with incomplete hardware behavior. Code that only requires PCI presence may work while software depending on undocumented memory-controller registers can expose the missing model.

MCPX boot ROM cache workaround

Some retail 1.1+ boot code depends on a short-lived physical CPU write-back-cache effect while touching the ROM region. xemu does not emulate that cache quirk at the electrical/microarchitectural level.

Instead, the active MCPX boot-ROM overlay is intentionally made writable so the guest observes the expected write/read sequence. Once the overlay is disabled, the apparent writes are discarded with that overlay.

flowchart TD
    A[Guest early boot writes ROM address] --> B{Physical Xbox}
    B --> C[CPU cache temporarily satisfies readback]

    A --> D{xemu}
    D --> E[Writable MCPX overlay accepts write]
    E --> F[Immediate guest read sees expected value]
    F --> G[LPC disables overlay later]

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This is a deliberate compatibility workaround: implementation fidelity is lower, guest-observation fidelity is higher.

MCPX APU: dedicated worker and deliberate shortcuts

The APU has a dedicated host thread (mcpx.apu_thread) that processes audio frames, voice processing and DSP work. It is paced partly by the SDL host-audio queue and QEMU_CLOCK_REALTIME, not by simulating every physical MCPX audio clock edge.

flowchart TD
    A[Guest APU MMIO / RAM state] --> B[APU registers + DSP/voice state]
    B --> C[mcpx.apu_thread]
    C --> D[Voice processing]
    D --> E[DSP frame]
    E --> F[Monitor / host audio stream]
    F --> G{Queued host audio}
    G -->|too much| H[Timed wait/backoff]
    G -->|low| I[Allow/speed pacing]
    H --> C
    I --> C

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That host queue is an emulator pacing mechanism. Host audio backend behavior can therefore influence where APU time and waits appear in a profile.

The APU source also contains an explicit shortcut for NV_PAPU_FEMEMDATA: a value that hardware is expected to write to guest memory after a notify-related completion is written immediately by xemu with stl_le_phys(...). The source itself calls this a “magic write.”

That shortcut removes unknown hardware latency/state transitions from the path. It can affect both compatibility edge cases and performance attribution.

The reset path also carries FIXME: Reset DSP state; current code invalidates DSP opcache state rather than modeling a complete physical reset sequence.

NVNet: real descriptor DMA semantics, simplified physical NIC

NVNet is more than a register bag. It walks guest transmit/receive descriptor rings with pci_dma_read()/pci_dma_write(), copies packet payloads, updates descriptors, raises PCI interrupts, and connects packets to QEMU's network backend.

sequenceDiagram
    participant G as Guest driver
    participant N as NVNet model
    participant M as Guest RAM
    participant Q as QEMU network backend

    G->>M: Build TX descriptors + packet buffers
    G->>N: Program ring + KICK
    N->>M: DMA-read descriptor/data
    N->>Q: qemu_send_packet()
    N->>M: Clear/update descriptor flags
    N->>G: Raise TX interrupt

    Q->>N: Receive host/network packet
    N->>M: DMA-write RX buffer + descriptor
    N->>G: Raise RX interrupt

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The PHY is still a logical model. Auto-negotiation is represented by a 250 ms QEMU_CLOCK_VIRTUAL timer, and several filter/status paths carry source FIXMEs. Receive-buffer length and TX-buffer limits also currently use assertions in places rather than fully modeled hardware error behavior.

The result is useful NIC semantics without simulating Ethernet magnetics, PHY analog signaling, collision waveforms, or wire propagation.

USB/XID: protocol behavior mapped to host input

The Xbox controllers are emulated as USB XID devices above generic OHCI controller models. Host controller state is sampled and packed into Xbox input reports; guest rumble output is forwarded back to the host input layer.

Some unexpected or unsupported XID requests currently return USB_RET_STALL and also contain assertions. This is a known compatibility/debug boundary: malformed or unusual guest USB traffic can terminate an assertion-enabled build where physical hardware would normally respond with protocol-level failure behavior.

Fast paths can change the apparent hardware cost

A fast path is not automatically a hack. It is safe when it preserves all guest-visible dependencies.

Examples include:

Fast path / shortcut	Benefit	Risk if assumptions are wrong
TCG translation-block chaining	Avoid dispatcher lookup between compatible blocks	Miss an interrupt/invalidation boundary
Direct host pointer to guest RAM	Avoid repeated address-space dispatch for proven RAM access	Bypass remap/MMIO/dirty semantics
Cached renderer resource	Avoid texture/shader/pipeline recreation	Reuse stale guest identity/state
Direct mapped Vulkan buffer update	Avoid staging copy/barrier/pass break	Earlier recorded GPU work sees later bytes
Synchronous SMBus helper call	Simple/cheap device transaction	Software-visible bus timing omitted
Fixed/register-only board device	Cheap deterministic compatibility	Software depending on physical side effects fails
APU immediate notify write	Avoid incomplete hardware state machine	Completion becomes visible earlier than hardware

A performance patch must state which observable dependency allows the fast path.

Known limitations are part of architecture

Source FIXME, TODO, assertions, no-op register cases and intentionally simplified models belong in architecture documentation when they change what software can observe or how a profile should be interpreted.

Use this classification when adding a limitation:

Class	Meaning
Fidelity gap	Physical behavior is intentionally or accidentally omitted
Compatibility workaround	xemu differs internally to preserve expected guest behavior
Fast path	Work is skipped/reused under a proven invariant
Stub	Device/function identity exists but implementation is incomplete
Host coupling	Host API/driver/scheduler behavior affects timing or output
Assertion boundary	Unexpected guest input can abort a debug/assert build instead of producing hardware-like error handling
Research boundary	Current implementation is correct enough to ship, but an alternative is being investigated

Why this matters to performance analysis

flowchart TD
    A[Hot or cold profiler region] --> B{What fidelity level is this path?}
    B -->|Full/functional model| C[Optimize implementation while preserving semantics]
    B -->|Register façade / stub| D[Do not infer physical hardware cost from host time]
    B -->|Host-service substitution| E[Separate emulator CPU time from host API/driver wait]
    B -->|Compatibility workaround| F[Preserve the guest-observed quirk before optimizing]
    B -->|Fast path| G[Revalidate invariant before broadening reuse]

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A low-cost emulated device can be cheap because xemu skips physical behavior. A high-cost backend can be expensive because host synchronization is doing work the original hardware performed asynchronously. Both facts matter when deciding whether a hotspot is “overhead.”

Source map

Area	Representative source
Machine/device construction	hw/xbox/xbox.c
PCI/LPC/IRQ routing	hw/xbox/xbox_pci.c
ACPI/GPIO	hw/xbox/acpi_xbox.c
SMBus controller	hw/xbox/amd_smbus.c
SMC	hw/xbox/smbus_xbox_smc.c
Temperature sensor	hw/xbox/smbus_adm1032.c
Video encoders	hw/xbox/smbus_cx25871.c, smbus_fs454.c, smbus_xcalibur.c
Optional/dev-kit Super I/O	hw/xbox/lpc47m157.c
MCPX APU	hw/xbox/mcpx/apu/*
NVNet	hw/xbox/mcpx/nvnet/*
XID input	hw/xbox/xid.c
NV2A	hw/xbox/nv2a/*

Related pages

• Hardware Oddities — sourced hardware observations, family-level leads, and unexecuted test proposals with explicit evidence labels.
• Architecture
• System Architecture
• Platform & I/O
• Memory & DMA
• CPU & vCPU Execution
• Clocks & Timers
• Performance Methodology