Hardware Oddity DRAM Geometry

DRAM geometry and expansion

Evidence: Xbox observed. Catalog correction SYS-003: Xbox revision 1.6 must not be excluded from 128 MiB-capable modifications merely because the spare RAM footprints were removed. A documented modification stacks chips and connects their chip-selects separately. This is a board-modification result, not a claim about unmodified retail RAM.

The 256 MiB interposer project exposed a narrower controller/DRAM mismatch: its DRAM uses A0–A7 and A9 for nine column bits, reserving A8 for auto-precharge, while the relevant NV2A configuration puts the added column bit on A8. The interposer exchanges A8/A9, and startup Xcodes adjust the auto-precharge selection through NV_PFB_CFG1. The project separately reports BIOS initialization without allocatable RAM and a tested stability need to reduce RAM speed from 200 to 150 MHz. Those are allocation-policy and signal-integrity observations, not further proof of a universal addressing ceiling.

Document row, column, bank, chip-select, auto-precharge, board wiring, BIOS allocation, and clock configuration independently. A single “64/128/256 MiB supported” field loses the causal information.

Proposed test: compare geometry-register programming, row/column aliasing, allocation visibility, and stability separately on named board/chip/BIOS combinations.

Sources: revision-1.6 128 MiB procedure; Prehistoricman's 256 MiB project and design files.

See also Memory & DMA and GPU address domains above 64 MiB.