Hardware Oddity Address Domains

GPU address domains above 64 MiB

Evidence: Xbox observed. Catalog correction NV2A-015: a guest software operation of AND 0x03FFFFFF only proves that this code path folds addresses to 26 bits. It does not establish a universal NV2A address limit. For example, applying that mask changes 0x04400000 (68 MiB) to 0x00400000 (4 MiB); whether any specific engine or DMA object performs that transformation still needs measurement.

In Ryan Miceli's firsthand Halo 2 HD investigation, the kernel allocator initially prevented upper-memory allocation, but a different allocation path let GPU resources above 64 MiB render. Preserve the distinction between kernel policy and the tested GPU path; this does not prove every GPU engine reaches every address.

Proposed test: on documented 64/128 MiB setups, place distinguishable patterns at addresses separated by 64 MiB and exercise each engine, register path, and DMA object. Record the installed-memory configuration, software mask, field width, object aperture, and observed aliasing separately.

See also Memory & DMA and DRAM geometry and expansion.