Hot Path vCPU Native Reciprocal Estimates

Native Reciprocal and Reciprocal-Square-Root Estimates

Lifecycle: Performance - Unproven · Type: Approximate ISA shortcut
State: Source-backed; runtime value is not established.

Status: Source-validated shortcut candidate; not implemented and not benchmarked in xemu.

Mechanism class: Host-ISA helper bypass with explicit numerical/fidelity risk.

Reviewed source: 322986f4c5502b3fa887a9605ac8cd88e9b2c579

Primary files: target/i386/ops_sse.h, target/i386/tcg/ops_sse_header.h.inc, target/i386/tcg/emit.c.inc.

Summary

Guest RCPPS, RCPSS, RSQRTPS, and RSQRTSS request approximate reciprocal operations. Current xemu expresses those operations through C helpers that calculate each lane with floating-point division and, for reciprocal square root, square root.

On an x86 host, the candidate emits the corresponding packed or scalar host estimate instruction and bypasses:

• helper-call setup and dispatch;
• lane-by-lane SoftFloat operation selection;
• four independent square-root/division calculations for packed 128-bit input;
• helper-related state materialization surrounding the call.

This is a genuine shortcut because a general helper route remains available and a host-capability route deliberately skips it.

It is not initially an equivalent shortcut. Native estimate instructions can produce different result bits from current xemu, and a modern host need not reproduce the exact estimate table of the original Xbox CPU.

Current source behavior

The packed reciprocal-square-root helper saves the current exception flags, evaluates each lane as 1 / sqrt(x), and restores the prior flags. The reciprocal helper similarly evaluates 1 / x per lane. The helper declarations expose packed and scalar versions to the translator.

flowchart TD
    A[Guest RCP/RSQRT instruction] --> B[Translator selects SSE helper]
    B --> C[Materialize helper arguments and state]
    C --> D[Call C helper]
    D --> E[For each active lane]
    E --> F{Operation}
    F -->|RCP| G[float32 division: 1 / x]
    F -->|RSQRT| H[float32 sqrt then division: 1 / sqrt x]
    G --> I[Store lane result]
    H --> I
    I --> J[Return to translated execution]

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The current helper does not simply expose the guest instruction's approximate estimate behavior. It computes a mathematical route using xemu's floating-point machinery.

Proposed shortcut

flowchart TD
    A[Guest RCP/RSQRT instruction] --> B{Supported x86 host route enabled?}
    B -->|No| R[Current helper reference route]
    B -->|Yes| C[Load guest source into host vector register]
    C --> D[Emit RCPPS/RCPSS or RSQRTPS/RSQRTSS]
    D --> E[Preserve scalar untouched lanes where required]
    E --> F[Write guest destination]

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Illustrative packed route:

movups  xmm0, [guest_source]
rsqrtps xmm0, xmm0
movups  [guest_destination], xmm0

The actual integration should emit host instructions through the TCG x86 backend or a narrowly scoped x86-specific translation path. An intrinsic-backed helper can be useful as a probe, but leaving the operation as an out-of-line C helper preserves part of the overhead the experiment is intended to remove.

Why it may help

The local opportunity is approximately:

executed candidate instructions
× current helper/FP-state expansion
× avoided per-lane arithmetic cost

The supplied standalone probe showed that a packed native kernel compiled to one estimate instruction between loads/stores. That proves compact host representation, not xemu speed.

The first required measurement is dynamic instruction count:

RCPPS
RCPSS
RSQRTPS
RSQRTSS

Group counts by guest PC, title/workload, and translated block. A perfect local replacement has negligible gameplay value if these instructions are rare.

Emulation and fidelity boundary

Question	Current helper	Native estimate candidate
Operation form	Mathematical per-lane calculation	Host approximate estimate instruction
Result bits	xemu SoftFloat-derived	Host instruction-specific estimate
Exceptions/status	Current helper preserves prior exception flags	Must reproduce the guest-visible contract explicitly
Packed execution	Loop over lanes	One packed host operation
Original Xbox resemblance	Not established	Plausible, but not established bit-for-bit

The supplied probe found that input 1.0f produced 0x3f7ff800 from the native reciprocal-square-root estimate instead of exact 1.0f. Therefore a candidate comparison must expect numerical differences rather than silently calling the route equivalent.

Do not add a Newton-Raphson correction in the first experiment. That changes both cost and numerical policy before establishing how games use the instruction.

Host and guest behavior that must be tested

Test packed and scalar forms across:

• positive normal values;
• positive and negative zero;
• subnormal inputs with relevant denormal modes;
• positive and negative infinities;
• negative finite input to reciprocal square root;
• quiet and signaling NaNs;
• destination/source aliasing;
• scalar upper-lane preservation;
• guest code that performs its own refinement step;
• changes in guest MXCSR rounding, exception masks, DAZ, and FTZ state.

Three comparisons answer different questions:

Comparison	Meaning
Current xemu helper vs host estimate	Compatibility difference introduced by the shortcut
Original Xbox/Pentium III result vs host estimate	Hardware-fidelity evidence
Reference vs candidate in retail workloads	Whether the route matters to useful guest progress

Do not treat the second comparison as complete until hardware or an accepted CPU oracle supplies actual guest results. Host-to-host consistency is insufficient.

Code and ownership map

File/area	Role
target/i386/ops_sse.h	Current reciprocal/reciprocal-square-root helper semantics
target/i386/tcg/ops_sse_header.h.inc	Helper declarations for packed/scalar forms
target/i386/tcg/emit.c.inc	Guest instruction translation/helper selection seam
tcg/i386/tcg-target.c.inc	Potential host x86 opcode emission
CPUX86State::sse_status / guest MXCSR state	Guest-visible floating-point environment

Evidence counters

Counter	Unit	Meaning
rcp_ps_exec / rcp_ss_exec	instructions	Dynamic reciprocal use
rsqrt_ps_exec / rsqrt_ss_exec	instructions	Dynamic reciprocal-square-root use
native_estimate_entries	instructions	Candidate route actually emitted/executed
reference_helper_entries	instructions	Reference route used
unsupported_host_fallbacks	instructions	Host route unavailable
numerical_mismatches	cases	Result differs from current reference in differential tests
helper_calls_avoided	calls	Local work removed
host_code_bytes	bytes	Generated-code footprint

Counters used for performance must be bounded and cheap. Exact bit-by-bit differential comparison belongs in correctness runs, not retail timing runs.

Expected profile signature

A useful candidate should show:

candidate instruction count > 0
reference helper samples/calls fall
helper-adjacent FP materialization falls
host samples remain in compact translated code
fixed guest progress improves or CPU time falls

A local host-code reduction with no measurable vCPU or workload effect is a valid negative result.

Failure modes

• Assuming all x86 implementations return the same estimate bits.
• Forgetting scalar upper-lane semantics.
• Changing guest exception/status behavior unexpectedly.
• Inheriting host DAZ/FTZ state without matching guest policy.
• Treating current-helper differences as automatically more hardware accurate.
• Adding refinement and hiding whether the native estimate itself helped.
• Benchmarking a synthetic reciprocal loop without proving retail reachability.
• Retaining a candidate route on non-x86 hosts without a defined implementation.

Qualification plan

1. Add dynamic instruction counters without changing execution.
2. Identify hot guest PCs and workloads using the instructions.
3. Build an instruction-level oracle for all special classes and randomized values.
4. Add same-binary reference/native routing in an optimized Release build.
5. Verify generated code contains the intended native op and no helper for admitted instructions.
6. Compare current-helper output, host-estimate output, and hardware/oracle output separately.
7. Run mixed x87/SSE and MXCSR-transition tests.
8. Run PGR2, Morrowind, CPU-heavy workloads, and applicable XISO cases with fixed guest progress.
9. Report numerical divergence, vCPU CPU time, frame tails, and guest progress together.
10. Keep the reference helper available until host coverage and compatibility scope are established.

External precedent

Clang's _mm_rcp_ps and _mm_rsqrt_ps intrinsics map to native reciprocal and reciprocal-square-root estimate instructions. That proves the host instruction is directly expressible; it does not prove xemu compatibility or original-Xbox result identity.

Related pages

• vCPU Shortcut Candidates
• Helper-Aware x87 Cache Retention
• Native SSE Arithmetic
• CPU & vCPU Execution
• Debugging Lag & Hot-Path Analysis

Full technical reference

Primary reference: This subject page is the design and research reference for Native Reciprocal Estimates. Pull requests are implementation/test history only.
Lifecycle: Performance - Unproven · Mechanism: Approximate ISA-native shortcut
Reviewed source: 322986f4c5502b3fa887a9605ac8cd88e9b2c579 · Acceptance class: approximate or scoped

1. Scope

Emit host RCPPS/RCPSS/RSQRTPS/RSQRTSS estimates for the guest estimate instructions instead of lane-wise mathematical reciprocal and square-root/division helper work.

This entry remains Unproven: the source path and opportunity are concrete, but no accepted xemu runtime result has established that the candidate improves representative workloads. The page defines what must be bypassed, what remains mandatory, and how the hypothesis can be rejected.

2. Source seams

File / function	Role
target/i386/ops_sse.h	reciprocal/rsqrt helper implementations
target/i386/tcg/emit.c.inc	guest opcode translation to helpers
tcg/i386/tcg-target.c.inc	host SSE emission capability

3. Current execution path

flowchart TD
    N0["Guest RSQRTPS"]
    N1["Helper transition"]
    N0 --> N1
    N2["For each lane: sqrt"]
    N1 --> N2
    N3["For each lane: divide 1/x"]
    N2 --> N3
    N4["Write exact-ish mathematical result"]
    N3 --> N4
    N5["Preserve/restore status policy"]
    N4 --> N5

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4. Candidate execution path

flowchart TD
    N0["Guest RSQRTPS"]
    N1["Admit x86 host/native estimate policy"]
    N0 --> N1
    N2["Emit one rsqrtps"]
    N1 --> N2
    N3["Write hardware estimate result"]
    N2 --> N3
    N4["Reference helper on unsupported host/policy"]
    N3 --> N4

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5. Why it may help

The guest instruction requests an estimate, while current code expresses a more expensive mathematical path. Native host estimates are compact but produce different bits and are not automatically identical to the original Pentium III estimate. Performance, compatibility, and hardware-fidelity questions must be tested separately.

6. Work removed

• Lane-wise sqrt/divide arithmetic
• Out-of-line helper transition
• Some helper state preparation

7. Work that remains mandatory

• Guest operand/destination semantics
• Scalar upper-lane preservation
• Defined status/exception policy
• Reference helper
• Non-x86 backend implementation

8. Implementation sketch

; Candidate x86-64 generated shape for packed reciprocal sqrt
movups  xmm0, [guest_src]
rsqrtps xmm0, xmm0
movups  [guest_dst], xmm0

; Reference semantic shape is effectively four lanes of:
; dst[i] = 1.0f / sqrtf(src[i])

The sketch defines the intended boundary; it is not a complete patch and does not replace source review, ownership design, or focused tests.

9. Correctness contract

• Approximate numerical differences are expected and must be declared.
• Signed zero, subnormals, infinities, negatives and NaNs follow the accepted guest-hardware/compatibility policy.
• Scalar forms preserve untouched lanes.
• Unsupported hosts use the maintained helper.

10. State, ownership, invalidation, and fallback

The route is selected by host ISA and explicit policy at translation/codegen time. No mutable cache is needed. Translation invalidation occurs normally when policy/build changes.

The maintained reference path remains the fallback whenever admission, capability, lifetime, or validation is uncertain. A fast result with an unproven dependency is not acceptable as an exact optimization.

11. Advantages

• Very small host instruction sequence
• May be closer to guest estimate intent
• Clear dynamic instruction counts
• Excellent isolated microbenchmark

12. Costs and failure modes

• Bit results differ from current xemu and may differ from Xbox CPU
• Games may refine or depend on estimate characteristics
• Rare instruction frequency means no game benefit
• Needs AArch64/other backend strategy

13. Evidence counters

Counters must be cheap, subsystem-owned, and snapshotted outside the hot loop. Record at least:

• RCPPS/RCPSS/RSQRTPS/RSQRTSS dynamic counts
• helper calls avoided
• host instructions/bytes
• numerical error distribution
• compatibility mismatches
• vCPU/frame time

A local reduction is not enough. Evidence must connect route reachability and removed work to fixed guest progress, CPU/GPU time where applicable, and p95/p99 behavior.

14. Qualification matrix

• All special FP classes
• Scalar upper lanes
• Random positive normals
• Known original-hardware results if obtainable
• Programs with Newton refinement
• Instruction microbench
• Representative gameplay with dynamic counts

Correctness runs may use validation layers, detailed comparisons, and fault injection. Performance acceptance must use optimized Release builds with matching symbols and minimal instrumentation.

15. Acceptance rule

Promote only after instruction frequency and gameplay value are demonstrated and the selected numerical policy is explicitly accepted or hardware-validated.

16. Rejection rule

Reject as a default if compatibility changes are unexplained, instructions are rare, or native host estimates do not match the desired guest contract.

17. Related architecture and history

CPU-and-vCPU-Execution · Performance-Unproven · Hot-Path-vCPU-Native-SSE-Arithmetic · vCPU-Windows-XMM-Register-Budget

PR pages may be linked as supporting evidence, but they are not substitutes for this reference.