Performance Unproven

Performance - Unproven

Reviewed: 2026-11-01 · Source: b7140848 · Availability: current main; stable/main boundaries are stated below.

This directory covers remaining proposal scope. Some linked pages now contain delivered or measured components; their status below takes precedence over the original candidate classification. See Implemented and Researched.

Every row below opens a standalone technical reference page. The subject page—not a PR—is the primary reference for the mechanism. Each page contains source seams, current and proposed flows, implementation or assembly sketches, invariants, pros/cons, evidence counters, and a qualification plan.

Jump to a subsystem

Audio · PFIFO / MMIO · Vulkan: state and prepared work · Vulkan: throughput and residency · vCPU / TCG

Audio

Item	Type	What it tests	Full technical reference
Linear Audio Resampling	Explicit quality/performance approximation	Use libsamplerate's linear converter instead of the current sinc converter under a clearly labeled audio-quality policy.	Open full page →
Prepared Voice Controls	Prepared-state optimization	Decode voice routing, attenuation, format, and static filter inputs once per validated control-word version instead of repeatedly reading and transforming the same guest data.	Open full page →
Span-Based Audio Fetch	Memory-loop restructuring	Resolve one bounded contiguous guest-memory span and one conversion kernel, then process many samples/ADPCM words instead of translating and dispatching each element.	Open full page →

OpenGL

Every row links to a standalone technical reference. The subject page—not a PR—is the primary design and qualification reference.

Item	Type	What it tests	Full technical reference
Native depth variant	Numerical/early-depth experiment	Remove custom fragment-depth writes for a narrowly admitted host-depth route.	Open full page →
Asynchronous display handoff	Host synchronization architecture	Replace CPU waits between render/display contexts with explicit GPU dependencies and slot lifetime.	Open full page →
Completed display reuse	Retained-result shortcut	Reuse a completed composition when the complete source/scanout/PVIDEO key still matches.	Open full page →
Uniform epoch tracking	Prepared-state shortcut	Skip reconstruction and GL uploads for program-local uniform groups that did not change.	Open full page →
GPU-downscaled readback	Transfer-reduction optimization	Downscale to guest resolution before readback instead of discarding scaled pixels on the CPU.	Open full page →
Persistent mapped geometry streaming	Streaming-buffer architecture	Use retired mapped slices instead of repeated orphan/subdata uploads for admitted streams.	Open full page →
Copy-image surface transfer	Exact copy subset	Use direct image-data copy for representation-compatible surface-to-texture updates.	Open full page →
Direct surface binding	Copy-bypass shortcut	Sample the render surface directly when representation, version, lifetime, and feedback rules permit.	Open full page →
Sampler objects	Sampling-state separation/cache	Reuse independent sampler state instead of mutating texture objects for every effective sampling change.	Open full page →
Render-state shadow	State-call suppression	Issue blend/depth/stencil/raster/binding calls only when the effective per-context state changes.	Open full page →
Deferred pooled occlusion queries	Query lifetime/scheduling	Pool exact query objects and defer blocking retrieval until guest ordering requires the value.	Open full page →
PVIDEO GPU conversion	Resource reuse/GPU conversion	Reuse overlay storage and move packed YUV conversion into display composition.	Open full page →
Cold shader stall avoidance	Asynchronous/alternate execution	Overlap first-seen compile/link work or use a proven OpenGL fallback route.	Open full page →

Open the OpenGL candidate overview →

MCPX APU / DSP

Open the APU/DSP investigation overview →

Every row links to a standalone technical reference. The subject page—not a PR—is the primary investigation reference.

Item	Type	What it tests	Full technical reference
DSP JIT qualification	Delivered default / remaining qualification	JIT default is in stable; broader compatibility/PCM/lifecycle evidence remains bounded	Open full page →
Voice-worker dispatch and mix reduction	Host scheduling/aggregation	Find the worker-count crossover, avoid empty wakeups, and reduce only touched mix bins	Open full page →
Prepared Voice Controls	Prepared-state optimization	Decode stable voice control/routing/filter inputs once per safe block	Open full page →
Span-Based Audio Fetch	Memory-loop restructuring	Resolve safe guest-memory/SGE spans once instead of per sample or compressed word	Open full page →
Bulk VP-to-DSP mix transfer	Exact backend shortcut	Replace 1,024 generic DSP writes per subframe with one exact block transfer	Open full page →
DSP DMA block transfers	Memory/backend restructuring	Decode descriptors once and transfer DSP/guest spans without word callbacks and an intermediate scratch copy	Open full page →
APU frame-lock contention	Measurement-first synchronization	Measure vCPU/MMIO wait against APU frame lock hold time before redesigning ownership	Open full page →
HRTF optimization	Exact/specialized signal processing	Remove circular-index and scalar-convolution overhead while preserving the declared audio contract	Open full page →
Experimental lazy GP/EP execution	Destructive observation experiment	Measure whether DSP work can be deferred when host audio monitors VP and no guest observation occurs	Open full page →
Peripheral opportunity counters	Instrumentation gate	Decide whether APU idle wakeups, OHCI, PTIMER, NVNet, or IDE deserve separate investigations	Open full page →

Delivered: DSP JIT selection defaults true(#183), Auto-four workers(#200), reliability#201/#305 and callback-local CFG_FMT#191. Descriptor/payload mappings#190/#275 partially implement fetch preparation. Full scheduler, persistent controls, span/kernel engine, lazy execution and HRTF proposals remain research; their broader benefits are not established.

PFIFO / MMIO

Item	Type	What it tests	Full technical reference
PFIFO Constant Status Read	Current-model constant-response lock bypass	Return the value already modeled as constant for NV_PFIFO_RUNOUT_STATUS without taking the general PFIFO mutex, if access semantics and instrumentation remain intact.	Open full page →

Vulkan: state and prepared work

Item	Type	What it tests	Full technical reference
Approximate Occlusion Reports	Title-scoped guest-result approximation	Avoid issuing and retrieving exact host occlusion counts by substituting a documented approximate guest result for workloads that only need a visibility hint.	Open full page →
Direct Surface Sampling	Guarded image-copy bypass	Sample a compatible rendered surface image directly instead of copying it into a separate texture image.	Open full page →
Frame-Scoped Texture Trust	Explicit stale-within-frame approximation	Validate an admitted RAM-backed texture on first use in a guest frame, then bypass further dirty-page, overlap, and content checks until the defined next validation boundary.	Open full page →
Precompiled Internal Shaders	Build-time preparation	Compile fixed xemu-owned GLSL during the build and embed compatible SPIR-V instead of invoking the runtime compiler at renderer initialization.	Open full page →
Prepared Vertex Layout	Prepared structural draw state	Cache the attribute-format/layout plan across draws while still resolving current addresses, ranges, freshness, and provoking values per draw.	Open full page →
Shader Selection Epoch Trust	Generation-based shader-selection shortcut	Replace repeated multi-category shader dependency inspection with one complete generation comparison, while leaving current uniforms and resources live.	Open full page →
Surface Coverage Index	Conservative spatial metadata/index	Answer common no-overlap range queries without walking every surface, while retaining exact checks for positive or ambiguous cases.	Open full page →
Texture Image / Sampler Separation	Cache and ownership redesign	Separate texture pixel representation from sampling state so filter/address/border changes do not duplicate image allocations and uploads when the underlying host image can be shared.	Open full page →
Uniform Update Plans	Dirty-summary and prepared-copy optimization	Maintain compact dirty summaries and a shader-layout-specific copy plan so clean arrays are not rescanned and inactive uniform metadata is not reinterpreted on every update.	Open full page →

Vulkan: throughput and residency

Item	Type	What it tests	Full technical reference
Adaptive Buffer Placement	Device-aware memory-placement policy	Choose mapped-direct versus staged device-local storage from actual Vulkan memory properties and measured access patterns instead of one fixed policy for unlike hosts.	Open full page →
Dynamic Uniform Descriptors	Descriptor architecture	Use dynamic offsets for ordinary VSH/PSH uniform buffers so changing constant offsets does not require rewriting unchanged texture descriptors or consuming another set.	Open full page →
GPU-Resident Surface Consumers	Representation/coherency architecture	Keep GPU-produced data on the GPU when the next consumer is also GPU-side, materializing guest RAM only at real CPU/device observation boundaries.	Open full page →
Native Vulkan Presentation	Frontend/presentation architecture	Present the Vulkan-composed image through a Vulkan swapchain and Vulkan UI path, removing the requirement to synchronously expose each new output as an OpenGL texture.	Open full page →
PVIDEO Resource Lifetime	Resource reuse plus GPU conversion	Stop recreating PVIDEO image/view/sampler objects on every upload, then test packed upload and GPU-side YUV conversion in the display batch.	Open full page →
Submission and Resource Retirement	Asynchronous batch ownership architecture	Decouple queue submission from immediate CPU completion and recycle descriptors, staging ranges, framebuffers, queries, and cache references only after the owning submission completes.	Open full page →

vCPU / TCG

Item	Type	What it tests	Full technical reference
Direct-RAM Read Windows	Speculative multi-access SoftMMU shortcut	Validate one stable RAM window for a recognized translated region and use direct host loads for several reads instead of repeating software-TLB preparation for each access.	Open full page →
FP Control-State Retention	Guarded host floating-point environment shortcut	Keep known-valid host FP control state across audited boundaries instead of broadly clearing the translator's knowledge and re-emitting MXCSR setup.	Open full page →
Helper-Aware x87 Cache Retention	State-materialization bypass	Keep cached x87 temporaries live across explicitly audited FP-independent helpers instead of unconditionally converting them to canonical 80-bit guest state before every helper call.	Open full page →
Native Reciprocal Estimates	Approximate ISA-native shortcut	Emit host RCPPS/RCPSS/RSQRTPS/RSQRTSS estimates for the guest estimate instructions instead of lane-wise mathematical reciprocal and square-root/division helper work.	Open full page →
Native SSE Arithmetic	Host-ISA direct-emission shortcut	Emit a narrowly admitted subset of guest SSE floating-point arithmetic directly instead of per-lane helper execution, under an explicit host FP-environment contract.	Open full page →
Recognized Poll-Loop Wait	Guest-execution bypass with event wake	Recognize one exact side-effect-free guest polling loop and sleep the vCPU until the producing emulated event, interrupt, timer, invalidation, or deadline requires retrying the original loop.	Open full page →
REP MOVS RAM Chunks	Bounded guest-memory loop shortcut	For a narrow admitted forward non-overlapping RAM case, copy a bounded chunk natively instead of executing generic guest address/load/store/bookkeeping for every element.	Open full page →
Windows XMM Register Budget	Win64 JIT register-allocation optimization	Save selected nonvolatile XMM registers at the C-to-JIT boundary so TCG can allocate more than XMM0-XMM4 during translated execution and potentially reduce spills.	Open full page →
x87 Comparison Flag Capture	Host instruction-selection experiment	Replace the current COMISD/COMISS plus PUSHF/POP full-flag capture with a smaller sequence that extracts only CF, PF and ZF if it is measurably better on the target host.	Open full page →

Promotion rule

Move an item to Researched only after real xemu runtime, profiling, or PR evidence exists. Move it to Implemented only after the mechanism lands in current main.

A negative or failed experiment moves to Researched, because the result prevents repeated work.

Implementation-ready research additions — September 15, 2026

This section preserves 27 workstreams from the source-backed research expansion. It is an additive research register, not a replacement for the original page or a claim that every existing wiki idea was reviewed. Source inspection is pinned to 322986f4c5502b3fa887a9605ac8cd88e9b2c579; historical repository measurements retain their original build/workload scope.

Start with Performance research — common test protocol and Performance research — reproducible checks. Standalone checks were re-run while preparing these notes; no production xemu patch, game benchmark or full-emulator qualification was performed by this documentation update.

Suggested experiment order

Bounded first: A11 attenuation lookup; A01 bulk mixbuffer writes; A07 indexing after its independent target-update repair. Profile-guided next: G01 warm uniform work, G02 exact vertex ranges, A08/A09 repeated preparation, C02 dirty-TLB metadata and C04 PFIFO/PGRAPH handoff attribution. Model ownership first: A03 state fidelity, A04 quiescence, A05 lock splitting, G03 report observation and C03 callback retirement.

Topic notes and first tests

Topic	Evidence added	First experiment
A01 — Bulk VP-to-DSP transfer	1,024 scalar writes per frame; backend ownership identified	One backend-owned 1,024-word mixbuffer write
A02 — DSP DMA block transfers	Per-word callbacks plus staging; formats are not memcpy-equivalent	Contiguous noninterleaved ordinary-memory transfers
A03 — DSP JIT qualification and optimization	Current-state N/M widening is not an identity	Separate current-state round trip from legacy migration
A04 — Lazy GP/EP execution	Zero input can retain effect tails and other side effects	Explicit disabled/reset-state equivalence, not silence detection
A05 — APU frame-lock contention	Frame work and guest DSP writes share a lock	Measure vCPU-blocking wait, then isolate one immutable work unit
A06 — Voice-worker dispatch and reduction	Scheduling/merge overhead, not missing parallelism	Inline small eligible work while preserving multipass grouping
A07 — HRTF addressing, smoothing, and SIMD	Index-walk equivalence plus stale right-target counterexamples	Separate target-update correctness repair from index walking
A08 — Span-based voice fetch	Repeated PCM/ADPCM SGE and physical-memory access	One boundary-limited ordinary-RAM span
A09 — Prepared voice-control data	Some reads already hoisted; pure-value caching is narrower	Per-invocation typed controls and input-keyed derivations
A10 — Peripheral opportunity counters	Establish eligible work and instrumentation overhead first	Bounded per-thread counts with end-of-window aggregation
A11 — Exact finite-domain volume attenuation table	4,096-value domain; immutable 16 KiB table	Table initialized with the unchanged attenuation expression
G01 — Warm texture/shader uniform work	Warm uniform preparation is a measured historical hotspot	Avoid unchanged derived uniform work, not only UBO writes
G02 — Exact vertex byte ranges instead of page-expanded readback triggers	Page-expanded vertex range can trigger unrelated readbacks	Exact consumer-range guard after coarse overlap lookup
G03 — Deferred/asynchronous occlusion-report completion	11.006 ms median STALLED wait in one historical diagnostic	Trace report publication and first required guest observation
G04 — Ordered vertex staging and timeline-managed ring buffers	Per-range retirement can replace broad waits	Bounded upload allocation with explicit last-reader retirement
G05 — Descriptor reuse and pool capacity	Capacity-only probe moved a wait instead of proving a win	Reuse complete effective descriptor identity
G06 — Shader-source deduplication, SPIR-V persistence, and prewarming	Duplicate generated sources and first-use compiler stalls recorded	Exact-source deduplication independent of driver pipeline caching
G07 — Hybrid ubershaders and asynchronous specialization	Correct fallback enables asynchronous specialization without skipped draws	Differential fallback/specialized output and atomic package publication
G08 — Native BC/DXT textures	Avoiding decode/expanded upload has a concrete mechanism	Native-versus-decoded sampling with valid per-format staging layout
G09 — Pipeline-key minimization and texture-scale suppression	79.9% fewer lookups corresponded to 1.079% historical throughput gain	One-field dependency table against always-recompute reference
G10 — Batched submissions and multithreaded command recording	Batching needs immutable tasks and demonstrated recording cost	Attribute serial recording cost before parallel dispatch
C01 — Static-state TB lookup and block chaining	Dispatcher cost is addressable only at legal lookup/chaining boundaries	One redundant key derivation or missed legal chain
C02 — Active-MMU dirty reset, range-helper inlining, and tiny-draw metadata	Conservative metadata can skip only provably empty eligible structures	Randomized full-scan versus optimized state comparison
C03 — Cached memory-access callbacks	Identity generations do not keep callback objects alive	Delayed-reader retirement stress before lookup optimization
C04 — PFIFO/PGRAPH dispatch handoffs and command-front-end batching	Source-confirmed ownership transfer per dispatch; selected inline packets already have packet-level bulk handling	Count handoffs, words per handoff, contention and zero-progress returns before bounded cross-packet batching
T01 — PTIMER masked-alarm work and overdue-epoch coalescing	Host callback scheduling is distinct from guest alarm state	Controlled guest-time reconcile tests at every observation boundary
T02 — Exact QPC scaling and presentation-deadline control	Clock arithmetic and guest time semantics must stay distinct	Exact integer scaling oracle plus fixed-work pacing controls

Evidence labels

MODEL_CHECKED establishes only the modeled domain. REDUCTION_REPRODUCED establishes a standalone source-equivalent case. SOURCE_CONFIRMED establishes that the inspected code contains the mechanism. REPOSITORY_REPORTED attributes an old measured result to its original source/build. PROPOSED_TEST is not a passing result. None is automatically PRODUCT_QUALIFIED.

Keep results and implementation status on the individual topic pages; keep this index to short findings and next tests. When a candidate is implemented, attach exact source and evidence identities before updating its status.

APU / DSP investigation suite

The MCPX recheck found that the strongest remaining non-graphics opportunities are concentrated in small 32-sample audio blocks crossing worker scheduling, guest-memory translation, DSP backend calls, DMA conversion, HRTF processing, and the APU frame mutex. The pages below preserve the verified starting point, source seams, counters, failure modes, and qualification gates so implementation work does not restart from zero.

Investigation	Evidence class	Full notes
Existing DSP56300 JIT qualification	Existing alternate engine; compatibility and gain unproven	APU DSP JIT Qualification
Voice-worker dispatch and full-matrix reduction	Source-confirmed fixed scheduling/reduction work; runtime share unmeasured	Voice-Worker Dispatch and Mix Reduction
Prepared voice controls	Existing subject page enriched with authority, invalidation, and negative-control requirements	Prepared Voice Controls
Span-based PCM/ADPCM fetching	Existing subject page enriched with safe span boundaries and ownership rules	Span-Based Audio Fetch
Bulk VP-to-DSP mix transfer	Exact backend shortcut candidate; 1,024 generic writes per active subframe are source-derived	Bulk VP-to-DSP Mix Transfer
DSP DMA block transfers	Source-confirmed word/callback/intermediate-buffer path; frequency must be counted	DSP DMA Block Transfers
APU frame-lock contention	Measurement-first cross-thread interference investigation	APU Frame-Lock Contention
HRTF convolution	Strong but workload-dependent inner-loop investigation	APU HRTF Optimization
Lazy GP/EP execution	Explicitly destructive observation experiment, not a normal optimization toggle	Experimental Lazy GP / EP Execution
Secondary peripheral counters	Promotion gate for OHCI, PTIMER, NVNet, IDE, and APU idle wakeups	Peripheral Opportunity Counters

Start with the APU / DSP Performance Investigations directory. No performance improvement in this suite is established until fixed-work Release measurements and guest-visible correctness comparisons exist.