Performance Research A02 DSP DMA Spans

DSP DMA block transfers

A02 — Implementation and validation notes

Field	Value
Evidence state	Source-confirmed opportunity; transfer semantics require differential tests
Inspected source	322986f4c5502b3fa887a9605ac8cd88e9b2c579
First experiment	Contiguous noninterleaved ordinary-memory transfers
Scope	Addendum dated September 15, 2026; not a current-main benchmark or implementation status

Unproven performance research · Performance research — common test protocol · Performance research — reproducible checks

Evidence and implementation reasoning

Verified opportunity. dsp_dma_run() already stages transfers in an intermediate buffer, but accesses DSP memory one word at a time through backend callbacks. It separately handles interleaving, 16-bit scaling, 24-bit masking, circular scratch, FIFOs, and descriptor writeback. DMA implementation.

Implementation. Begin with contiguous, noninterleaved ordinary-memory spans. Retain the descriptor-by-descriptor outer protocol and the existing scalar fallback. Reuse a bounded per-instance staging allocation rather than broadening the existing function-static scratch-buffer design into a parallel subsystem. The current growth path assigns a fresh malloc result without freeing the previous allocation; that ownership issue should be isolated from throughput changes.

Why a plain memcpy is insufficient. The source shifts 16-bit DSP values on export/import and masks 24-bit imports. Program-memory writes can invalidate compiled code. Circular boundaries, FIFO callbacks, descriptor mutation, and buffer-offset writeback are observable parts of the operation. Eliminating staging can also change aliasing behavior; a model counterexample is included, but it does not establish that today's MCPX buffers actually alias.

Expected gain. Remove per-word dispatch and redundant conversion/mapping work for eligible spans. The ceiling is the measured DMA contribution, not the complete DSP execution time. Add histograms of transfer length, direction, format, memory space, interleave, and fallback reason before selecting the first fast path.

Acceptance. Compare destination bytes, DSP words, descriptor state, callback order, and program-cache invalidation. Include wrap boundaries, successive descriptors that mutate later descriptors, zero/small transfers, and failure/retry behavior.

First patch boundary

Keep staging and descriptor order in the first patch. Fix staging-buffer ownership separately. Program-memory writes keep their cache-invalidation path.

descriptor -> scalar backend word loop -> scratch/FIFO -> writeback; replace only eligible word loops

Locate the inspected seam before editing; names or ownership may have changed since the pinned review:

git grep -n -E 'dsp_dma_run|scratch_circular_copy|mem_read|mem_write' -- hw/xbox/mcpx/apu/dsp

Proposed focused tests

These are implementation gates to add or exercise, not claims that production tests already exist or passed. Retained standalone checks are on the checks page.

Test ID	Setup / deliberate control	Required oracle
A02.01	Both directions, supported 16/24-bit formats, and lengths 0, 1, 2, 31, 32 and a valid full span.	DSP words, output bytes, shifts and masks match the scalar reference.
A02.02	Cross scratch wrap; run descriptors that update a later descriptor; request interleave and program-memory writes.	Callback order, writeback and invalidation match; unsupported spans take the original path.
A02.03	Run the supplied staged-versus-forward-copy counterexample.	The model remains different; removal of staging is not silently treated as equivalent.

Counters and rejection criteria

Collect: dma_words, dma_descriptors, eligible_spans, scalar_fallbacks_by_reason, backend_calls, conversion_cpu_ns, dma_cpu_ns. Keep exact counts separate from sampled durations; use an uninstrumented build for performance qualification.

Reject or hold: Reject a callback/order/descriptor mismatch even when final audio matches. Report allocation cleanup as correctness/maintenance, not an assumed throughput gain.

Follow the common protocol for source identities, previous-main/fixed-baseline controls, raw results, confidence and retail/XISO qualification. No gain becomes proven from a model, cache hit, local operation count, or shifted wait label alone.