Hardware Oddities

Hardware Oddities

Reviewed: 2026-11-01 · Source: b7140848 · Availability: current main; stable/main boundaries are stated below.

Current implementation/defaults and stable/main availability are maintained in Current status, Current register and Controls. Dated observations below retain their own source and evidence boundary.

This is the home page for original Xbox behaviors that are easy to misclassify as an overflow, an unsupported shader, or a generic device error. Each linked page separates the observation from its interpretation and gives a concrete test for xemu. These are research notes, not a claim that xemu currently reproduces every behavior.

Evidence labels

Label	Meaning
Xbox observed	Firsthand original-Xbox hardware experiment or production-game behavior. Record the tested board, chip, BIOS, or game when known.
Original implementation	Original game shader/source or driver change. It proves the software path, not every silicon edge case.
NVIDIA-family documentation	Vendor specification or generation-tagged reverse engineering. Useful test target; not automatically an NV2A measurement.
Reported Xbox behavior	Firsthand report whose public register-level reproduction remains incomplete.
Proposed test	A falsifiable xemu-versus-hardware comparison, not a completed test.

Memory, addressing, and resource views

Oddity	Evidence	Why it matters
DRAM geometry and expansion	Xbox observed	Board wiring, column bits, auto-precharge, BIOS allocation, and signal integrity are distinct limits. Includes correction SYS-003.
GPU address domains above 64 MiB	Xbox observed	A guest mask is not a universal GPU address limit. Corrects NV2A-015.
Halo 2 resource aliasing and tiled pitch	Xbox observed / original implementation	Many views can share few buffers; view identity requires interpretation and history.

Shader and graphics dataflow

Oddity	Evidence	Why it matters
Shrek's HILO_1 path	Xbox observed	Early assembler limitations did not define silicon capabilities.
Combiner-dependent bit packing	Original implementation	A near-identical image can hide changed payload bits.
Texture-stage dependencies	NVIDIA-family documentation	Stage 3 can feed a stage-2 lookup; intermediate and RGBA results differ.
XF context writes and STPOS	NVIDIA-family documentation	Some vertex modes mutate parameter storage or read position output.
RCC boundary values	NVIDIA-family documentation	Clamped reciprocal has finite signed boundary results.
The formerly illegal combiner mode	NVIDIA-family documentation	Hardware accepted a useful combination the early API prohibited.

Command, display, and board devices

Oddity	Evidence	Why it matters
PFIFO calls, payloads, and endpoints	NVIDIA-family documentation	The documented pusher has one return slot, not a recursive stack.
Semaphore DMA object quirk	NVIDIA-family documentation	An acquire may bind a nominally write-only DMA class.
TV scanout alongside CRTC	Reported Xbox behavior	Rendering and display generation need distinct diagnosis.
Xyclops serial freeze and chip variants	Xbox observed	Debug receive activity may suspend board management. Corrects SMC-002.
NVNet receive-status combinations	Original implementation	Framing-only and framing-plus-hard-error are different cases.
MCPX overlay and a retracted boot theory	Xbox observed	A flash dump is not necessarily the executing boot code.

How to use this section

Keep software masks, register widths, DMA apertures, installed-memory decoding, and BIOS allocation policy separate. Preserve raw GPU state and memory/view history alongside reconstructed shaders. Do not infer that arbitrary out-of-range texture accesses are safe: the sourced cases describe specific mechanisms. No new physical-console tests were run for this catalog.