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Here are 40 public repositories matching this topic...

riscv-mcu / e203_hbirdv2

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The Ultra-Low Power RISC-V Core

cpu fpga core riscv verilog china hummingbird nuclei soc risc-v low-power e203

Updated Oct 9, 2024
Verilog

sergeykhbr / riscv_vhdl

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Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

debugger qt simulator cpu vhdl riscv systemc soc

Updated Nov 15, 2024
Verilog

WilsonChen003 / HDLGen

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HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

python automation asic script perl rtl verilog hdl soc

Updated Oct 31, 2023
Verilog

AleksandarKostovic / Riscy-SoC

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Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

verilog soc risc-v riscy-soc

Updated Oct 11, 2019
Verilog

waynezv / FPGA_Ultrasound

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CMU 18545 FPGA project -- Multi-channel ultrasound data acquisition and beamforming system.

fpga data-acquisition ultrasound soc beamforming

Updated Apr 27, 2016
Verilog

chili-chips-ba / openCologne

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Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chili-chips.xyz/open-cologne

design embedded fpga hls digital pcb rtl systemverilog soc risc-v gatemate colognechip

Updated Nov 1, 2024
Verilog

abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor

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I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be …

asic fpga vhdl rtl verilog synthesis fft soc asic-verification asic-design

Updated Dec 3, 2023
Verilog

edabk-hust / edabk_brain_soc

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A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated by ChatGPT-4 with advanced optimizations.

verilog soc snn efabless openlane chatgpt chatgpt4

Updated Feb 18, 2024
Verilog

Goshik92 / SHA256Hasher

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SHA-256 IP core for ZedBoard (Zynq SoC)

arm fpga zynq xilinx sha256 vivado systemverilog soc zedboard

Updated Jun 22, 2018
Verilog

siorpaes / BareBonesCortexM0

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Extremely basic CortexM0 SoC based on ARM DesignStart Eval

fpga rtl verilog vivado hardware-designs mcu soc cortex-m0 xilinx-vivado

Updated Oct 8, 2018
Verilog

chili-chips-ba / openXC7-TetriSaraj

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Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.

open-source gamedev fpga rtl xilinx soc verilog-hdl yosys basys3 tetris-game nextpnr xc7a35t

Updated Oct 16, 2024
Verilog

ZipCPU / xulalx25soc

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A System on a Chip Implementation for the XuLA2-LX25 board

fpga soc zipcpu wishbone-bus

Updated Dec 13, 2018
Verilog

ZipCPU / videozip

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A ZipCPU SoC for the Nexys Video board supporting video functionality

fpga gplv3 verilog hdmi soc system-on-chip verilator zipcpu nexys-video

Updated Nov 13, 2024
Verilog

NOP-Processor / NOP-SoC

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System-on-chip design for NOP in NSCSCC 2023.

soc nscscc

Updated Aug 21, 2023
Verilog

dawsonjon / chips_v

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RISC-V System on Chip Builder

python c embedded fpga riscv verilog chips soc fpga-soc risc-v chip-builder

Updated Sep 27, 2020
Verilog

abdelazeem201 / ASIC-Implementation-UART

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This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between computer and peripherals. UART mainly contains Transmitter, Receiver and Baud Rate Generator. Baud Rate Generator generates the clock for the UART. We can achieve the desired Baud Rate by using divide factor from sys…

asic fpga vhdl eda rtl verilog synthesis uart soc pnr