Firtool Release 1.45.0

What's Changed

• [LowerIntrinsics] Touchup to avoid unused instance path cache. by @dtzSiFive in #5411
• [Comb] Truth table operation by @teqdruid in #5404
• [OM] Expose ReferenceAttr to Python by @nandor in #5413
• [FIRRTL][InferWidths] Tweak debug printing to show names and more bits. by @dtzSiFive in #5415
• [FIRRTL] Clean up instances in ExtractClasses. by @mikeurbach in #5395
• [CI] Push circt python wheel to pypi nightly by @rsetaluri in #5412
• [Pipeline] Add verifiers and fix register materialization pass by @mortbopet in #5386
• [Pipeline] Add "ext" inputs to pipelines by @mortbopet in #5347
• [DCToHW] Add DCToHW conversion pass by @mortbopet in #5298
• [FIRRTL] ExtractClasses: Fix use-after-free. by @dtzSiFive in #5429
• [Reduce] Add missing build deps on HW/FIRRTL dialects. by @dtzSiFive in #5430
• [CAPI][NFC] Address function prototype warnings by @trilorez in #5432
• [Python] Fix import path by @teqdruid in #5434
• [PyCDE] Fix parameterized extern mods by @teqdruid in #5435
• [Comb] Lower comb pass boilerplate by @teqdruid in #5433
• [LowerComb] Truth table to mux tree lowering by @teqdruid in #5405
• [FIRRTL] Support EnumTypes in error messages by @youngar in #5439
• PTECH-747: llvm bump on circt. Found 2 errors. by @mbalboni07 in #5414
• [Seq] Add seq.fifo ODS and rationale by @mortbopet in #4189
• [CMake] Make cmake config more reliable? by @maerhart in #5145
• [FIRRTL] Add mux cell intrinsics by @uenoku in #5428
• [FIRRTL] Add BaseTypeAliasType by @uenoku in #5416
• [ExportVerilog] Remove array literal by @uenoku in #5443
• [FIRRTL][InferResets] Fix reset inference through const cast. by @dtzSiFive in #5370
• [HW] Add struct_create(struct_explode) folder by @maerhart in #5450
• [CI][Win] Reduce peak disk usage after LLVM rebuild. by @dtzSiFive in #5446
• [Seq] Add FirMem op by @fabianschuiki in #5009
• Bump LLVM along Main by @mwachs5 in #5451
• [FIRRTL] Implement alias-aware type casts by @uenoku in #5417
• [FIRRTL] Options for using both @info and .fir, attach .fir as notes. by @dtzSiFive in #4671
• [Seq] Fix FirMemReadWriteOp::canonicalize by @trilorez in #5460
• [SVExtractTestCode] Clone constants even when used by designs as well by @uenoku in #5466
• [SVExtractTestCode] Use name/namehint as a port name by @uenoku in #5464
• [FIRRTL] Reset values added in InferResets are now const. by @trilorez in #5468
• [SeqToSV] Add clock_gate lowering by @mortbopet in #5457
• [Pipeline] add 'go' signal to pipeline by @mortbopet in #5455
• [Pipeline] Add preliminary stall lowering by @mortbopet in #5467
• [FIRRTL] Add type alias parser by @uenoku in #5449
• [FIRRTL] Drop unused repl-seq-mem-circuit option. by @dtzSiFive in #5474
• [Seq] Lower FirMemOp to HWModuleGeneratedOp by @fabianschuiki in #5024
• [Calyx] Add sequential memories by @andrewb1999 in #5471
• [FIRRTL][CHIRRTL] Add dialect C API by @SpriteOvO in #5472
• [FIRRTL] Support instances of property modules in ExtractClasses. by @mikeurbach in #5396
• [FIRRTL][CHIRRTL] C API rename and change some types by @SpriteOvO in #5486
• [NFC][Pipeline] Restructure pipeline dialect tablegen files by @mortbopet in #5475
• [Arc] Eliminate AllocateState moveBefore/isBeforeInBlock combination by @TaoBi22 in #5481
• [FIRRTL][NFC] Add test rejecting connect of properties. by @dtzSiFive in #5491
• Add support for Windows and revamp FIRRTL release artifacts by @jackkoenig in #5470
• [FIRRTL][NFC] Fix typo in Vector type parameter. by @dtzSiFive in #5495
• [FIRRTL][Properties] Add List, Map<K, V> types. by @dtzSiFive in #5492
• [circt-lec] Fixed equivalence check for multiple outputs by @fzi-hielscher in #5358
• [FIRRTLToHW] Add missing twoState attributes by @fzi-hielscher in #5257
• [FIRRTL][CreateSifiveMetadata] Use symbols for memory metadata by @prithayan in #5482
• [SV] Cleanup HWExportModuleHierarchyPass by @seldridge in #5485
• [FIRRTL] Export literal identifiers correctly by @seldridge in #5502
• [InferWidth] Parallelize post processing, NFCI by @uenoku in #5496
• [Comb][ExportVerilog] Support SV attributes for MuxOp by @uenoku in #5487
• [FIRRTL][FIRParser] Rework assert+FALLTHROUGH, NFCI. by @dtzSiFive in #5505
• [FIRRTL] Verify OpenAggs, fix agg-of-properties. by @dtzSiFive in #5508
• [FIRRTL][IMDCE] Remove some cached state by @youngar in #5480
• [LowerFIRRTLToHW] Create less wires with instance ports by @youngar in #5510
• [FIRRTL][IMDCE] Add test for dead output ports, NFC by @youngar in #5512
• [LowerFIRRTLToHW] Use backedges over temporary wires, NFC by @youngar in #5513
• [FIRRTL] Add FIRRTLTypeSwitch by @uenoku in #5456
• [IMDCE] Delete unreachable modules by @uenoku in #5517
• [Arc] Fix dominance issue in GroupResetsAndEnables by @zyedidia in #5511
• [FIRRTL] Canonicalize reductions looking through casts of various forms by @darthscsi in #5499
• [InstanceGraph] Speed up instance graph constructions, NFCI by @uenoku in #5520
• [FIRRTL][FIRPaser] Better diagnostic for unsupported rwprobe's. by @dtzSiFive in #5522
• [InferWidths] Remove expensive walks, NFC by @uenoku in #5523
• [ExportChiselInterface] Support probe types by @trilorez in #5497
• [FIRRTL] Change emitter to v3.0.0 by @seldridge in #5509
• [Calyx] Add Static Groups and Control by @andrewb1999 in #5354
• [PyCDE] Upgrade FSMs to new module style by @teqdruid in #5516
• [LLVM] Weekly bump by @maerhart in #5503
• [FIRRTL] Add containTypeAlias to type storage and define getAnonymousType by @uenoku in #5493
• [Pipeline] Add per-register clock gating by @mortbopet in #5489
• [LowerToHW] Implement MuxCell intrinsics lowering by @uenoku in #5458
• [InferReset] Parallelize the annotations accumulation, NFC by @uenoku in #5534
• [FIRRTL] Canonicalize away CVT and adjust all patterns which matched cvt by @darthscsi in #5527
• [FIRRTL] Remove UninferredWidthCastOp for now. by @dtzSiFive in #5528
• [Support] Add a 'by-name' lookup for HWModuleLike ops by @mortbopet in #5473
• [Comb][Canonicalize] keep attributes during op width narrowing by @7FM in #5532
• [Pipeline] Fix ScheduledPipelineOp builder by @mortbopet in #5540
• [Seq] Canonicalize transitive clock gates by @mortbopet in #5504
• [SCF-to-Calyx] Fix Ordering Bug by @calebmkim in #5526
• Bump LLVM to 015dabd7672f936cdb5bdcad20fe80b17f05c9ca by @mikeurbach in #5546
• [HW] Fix instance ops in hw-flatten-io pass by @mortbopet in #5537
• [FIRRTLFolds] Fix andr(pad(x:sint, n)) -> andr(x) canonicalization by @uenoku in #5547
• [FIRRTL] incorrect canonicalization pattern by @darthscsi in #5556

New Contributors

• @mbalboni07 made their first contribution in #5414
• @fzi-hielscher made their first contribution in #5358
• @calebmkim made their first contribution in #5526

Full Changelog: firtool-1.44.0...firtool-1.45.0