Corpus Testing 29

Corpus Page 29

Part 29 of 29 of Corpus Testing: boards 3,025 to 3,132, six runs each, one file format a run, as Corpus Testing describes.

3025. backplane_fp6

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	1.8	0.2 ms	1.9	64 ms	0.2	0.2	4.7
Simulation, STEP	0.2	0.4	1.7	0.2 ms	1.8	1.6	0.2	0.2	6.0
Simulation, STL	0.2	0.3	1.7	0.1 ms	1.6	0.1	0.2	0.2	4.4
Simulation, OBJ	0.2	0.4	1.8	0.1 ms	1.7	1.7	0.2	0.2	6.1
Visual, GLB	0.2	0.3	1.8	0.2 ms	3.4	48 ms	0.3	0.2	6.2
Visual, OBJ	0.2	0.3	1.8	0.2 ms	3.5	1.4	0.4	0.2	7.7

Board Repo: winkleplex10-bit/the-mac-pro-project Board: backplane_fp6.kicad_pcb Folder kicad / macpro62-backplane / variants / fp6_floorplan_6L Complexity 191 / 1000 (size 116, features 75) KESE features slotted holes, rounded, trapezoid or chamfered pads, curved board outline, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 20, 0, 0 Triangles, simulation 418,448 in 15 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 15 MB 307 MB STEP 61 MB 355 MB STL 21 MB 306 MB OBJ 44 MB 357 MB Visual GLB 12 MB 363 MB OBJ 36 MB 411 MB

3026. backplane_hub_fp2

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.4	2.4	0.1 ms	2.1	76 ms	0.3	0.2	5.8
Simulation, STEP	0.2	0.4	2.6	0.2 ms	2.1	2.0	0.3	0.2	7.9
Simulation, STL	0.2	0.5	2.6	0.2 ms	2.2	0.1	0.2	0.2	6.0
Simulation, OBJ	0.2	0.5	2.5	0.2 ms	2.2	2.8	0.2	0.2	8.8
Visual, GLB	0.2	0.4	2.4	0.2 ms	4.2	54 ms	0.3	0.2	7.9
Visual, OBJ	0.3	0.5	2.4	0.2 ms	3.8	1.9	0.4	0.3	9.7

Board Repo: winkleplex10-bit/the-mac-pro-project Board: backplane_hub_fp2.kicad_pcb Folder kicad / macpro62-backplane / variants / hub_fp2_d30_assumed Complexity 192 / 1000 (size 117, features 75) KESE features slotted holes, rounded, trapezoid or chamfered pads, curved board outline, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 21, 0, 0 Triangles, simulation 429,260 in 15 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 15 MB 315 MB STEP 62 MB 352 MB STL 21 MB 311 MB OBJ 46 MB 358 MB Visual GLB 12 MB 418 MB OBJ 37 MB 413 MB

3027. macpro62-io-board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.2	7.1	0.2 ms	7.5	0.3	0.5	0.3	17.4
Simulation, STEP	0.5	1.1	7.4	0.3 ms	7.8	5.0	0.5	0.2	22.5
Simulation, STL	0.5	1.3	7.5	0.2 ms	7.7	0.6	0.5	0.2	18.2
Simulation, OBJ	0.5	1.2	7.6	0.3 ms	8.1	7.0	0.5	0.2	25.1
Visual, GLB	0.5	1.2	7.5	0.1 ms	16.2	0.2	1.5	0.2	27.3
Visual, OBJ	0.5	1.2	7.4	0.4 ms	15.8	6.0	2.2	0.2	33.4

Board Repo: winkleplex10-bit/the-mac-pro-project Board: macpro62-io-board.kicad_pcb Folder kicad / macpro62-io-board Complexity 237 / 1000 (size 162, features 75) KESE features slotted holes, rounded, trapezoid or chamfered pads, curved board outline, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 143, 0, 0 Triangles, simulation 1,595,010 in 16 parts Note mostly unrouted Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 59 MB 735 MB STEP 284 MB 919 MB STL 80 MB 752 MB OBJ 180 MB 1.2 GB Visual GLB 47 MB 1.1 GB OBJ 147 MB 1.1 GB

3028. mod_hdmi

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	56 ms	0.1	0.5	0.1 ms	1.1	30 ms	0.1	0.2	2.2
Simulation, STEP	56 ms	0.2	0.5	0.1 ms	1.2	0.9	0.1	0.2	3.1
Simulation, STL	55 ms	0.1	0.5	0.1 ms	1.1	46 ms	0.1	0.2	2.2
Simulation, OBJ	84 ms	0.1	0.5	0.2 ms	1.1	0.8	0.1	0.2	2.9
Visual, GLB	60 ms	0.1	0.5	2 ms	1.7	21 ms	0.2	0.2	2.8
Visual, OBJ	74 ms	0.2	0.5	0.1 ms	1.8	0.6	0.2	0.2	3.4

Board Repo: winkleplex10-bit/the-mac-pro-project Board: mod_hdmi.kicad_pcb Folder kicad / macpro62-io-modules / mod_hdmi Complexity 196 / 1000 (size 131, features 65) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 4, 291, 24 Triangles, simulation 168,642 in 27 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 6.3 MB 211 MB STEP 36 MB 223 MB STL 8.4 MB 205 MB OBJ 18 MB 207 MB Visual GLB 5.0 MB 175 MB OBJ 14 MB 175 MB

3029. mod_usba

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	99 ms	0.3	1.6	0.3 ms	2.2	48 ms	0.3	0.2	4.8
Simulation, STEP	98 ms	0.3	1.6	0.2 ms	2.4	1.5	0.3	0.2	6.5
Simulation, STL	0.1	0.4	1.6	0.2 ms	2.2	69 ms	0.3	0.3	4.9
Simulation, OBJ	94 ms	0.3	1.6	0.2 ms	2.2	1.3	0.3	0.3	6.1
Visual, GLB	0.1	0.4	1.5	0.1 ms	2.8	36 ms	0.3	0.2	5.2
Visual, OBJ	96 ms	0.3	1.5	0.2 ms	2.7	1.0	0.2	0.2	6.0

Board Repo: winkleplex10-bit/the-mac-pro-project Board: mod_usba.kicad_pcb Folder kicad / macpro62-io-modules / mod_usba Complexity 190 / 1000 (size 125, features 65) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 4, 198, 19 Triangles, simulation 264,738 in 22 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 10 MB 263 MB STEP 57 MB 273 MB STL 13 MB 262 MB OBJ 29 MB 257 MB Visual GLB 7.1 MB 236 MB OBJ 20 MB 237 MB

3030. mod_usbc

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	92 ms	0.2	0.5	0.1 ms	1.4	39 ms	0.2	0.2	2.7
Simulation, STEP	91 ms	0.2	0.6	0.2 ms	1.3	1.1	0.2	0.2	3.7
Simulation, STL	76 ms	0.2	0.5	0.2 ms	1.2	45 ms	0.2	0.2	2.5
Simulation, OBJ	77 ms	0.2	0.6	0.1 ms	1.2	1.0	0.2	0.2	3.4
Visual, GLB	76 ms	0.2	0.5	0.2 ms	2.0	26 ms	0.2	0.2	3.3
Visual, OBJ	73 ms	0.2	0.5	0.1 ms	1.9	0.9	0.2	0.2	4.0

Board Repo: winkleplex10-bit/the-mac-pro-project Board: mod_usbc.kicad_pcb Folder kicad / macpro62-io-modules / mod_usbc Complexity 209 / 1000 (size 134, features 75) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 4, 361, 29 Triangles, simulation 184,304 in 30 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 6.9 MB 208 MB STEP 39 MB 232 MB STL 9.2 MB 206 MB OBJ 19 MB 209 MB Visual GLB 5.5 MB 192 MB OBJ 15 MB 188 MB

3031. panel_a25

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	2.8	18.7	0.6 ms	51.1	0.3	2.5	0.3	76.4
Simulation, STEP	0.7	2.6	18.5	0.4 ms	50.3	8.7	2.5	0.3	83.8
Simulation, STL	0.8	2.7	18.2	0.4 ms	50.9	0.5	2.4	0.3	75.9
Simulation, OBJ	0.8	2.7	19.2	0.3 ms	50.9	10.9	2.7	0.3	87.5
Visual, GLB	0.8	2.8	19.1	0.5 ms	25.2	0.2	1.7	0.3	50.1
Visual, OBJ	0.8	2.9	19.9	0.4 ms	25.4	8.1	2.1	0.3	59.5

Board Repo: winkleplex10-bit/the-mac-pro-project Board: panel_a25.kicad_pcb Folder kicad / macpro62-io-modules / panel / panel_a25 Complexity 220 / 1000 (size 165, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper drawings Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 22, 825, 88 Triangles, simulation 1,738,244 in 61 parts Note panel Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 68 MB 969 MB STEP 418 MB 1.0 GB STL 87 MB 945 MB OBJ 202 MB 1.4 GB Visual GLB 48 MB 1.2 GB OBJ 142 MB 1.1 GB

3032. panel_c50

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.1	3.3	20.3	1.0 ms	24.2	0.5	3.0	0.3	52.8
Simulation, STEP	1.2	3.4	21.1	0.7 ms	23.4	8.9	2.7	0.4	61.1
Simulation, STL	1.2	3.2	21.4	0.8 ms	25.1	0.7	3.0	0.4	55.1
Simulation, OBJ	1.1	3.3	21.4	0.8 ms	25.4	13.8	3.4	0.4	68.7
Visual, GLB	1.2	3.6	21.4	1 ms	29.0	0.3	3.0	0.3	58.8
Visual, OBJ	1.1	3.4	21.2	0.8 ms	29.4	10.3	3.2	0.3	68.9

Board Repo: winkleplex10-bit/the-mac-pro-project Board: panel_c50.kicad_pcb Folder kicad / macpro62-io-modules / panel / panel_c50 Complexity 254 / 1000 (size 189, features 65) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper drawings Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 40, 2,532, 222 Triangles, simulation 2,001,402 in 153 parts Note panel Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 76 MB 985 MB STEP 471 MB 1.1 GB STL 100 MB 960 MB OBJ 228 MB 1.5 GB Visual GLB 58 MB 1.2 GB OBJ 177 MB 1.3 GB

3033. tdr_coupon_a25

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.2	8.0	0.1 ms	10.4	0.1	1.6	0.2	22.0
Simulation, STEP	0.3	1.2	8.3	0.1 ms	10.9	3.9	1.6	0.2	26.6
Simulation, STL	0.3	1.2	8.1	0.1 ms	11.0	0.2	1.7	0.2	22.7
Simulation, OBJ	0.3	1.2	8.3	0.1 ms	10.8	3.9	1.6	0.3	26.5
Visual, GLB	0.3	1.2	8.2	0.1 ms	7.8	59 ms	0.6	0.2	18.4
Visual, OBJ	0.3	1.3	8.1	0.1 ms	7.8	1.9	0.5	0.2	20.1

Board Repo: winkleplex10-bit/the-mac-pro-project Board: tdr_coupon_a25.kicad_pcb Folder kicad / macpro62-io-modules / tdr / tdr_coupon_a25 Complexity 142 / 1000 (size 107, features 35) KESE features through vias, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 6, 33, 12 Triangles, simulation 610,764 in 12 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 26 MB 561 MB STEP 166 MB 550 MB STL 31 MB 558 MB OBJ 74 MB 571 MB Visual GLB 13 MB 379 MB OBJ 37 MB 434 MB

3034. tdr_coupon_c50

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.6	9.1	0.1 ms	9.5	0.2	1.8	0.2	22.8
Simulation, STEP	0.4	1.6	9.4	0.2 ms	9.5	4.3	1.7	0.2	27.1
Simulation, STL	0.4	1.5	8.9	0.2 ms	9.3	0.2	1.8	0.3	22.5
Simulation, OBJ	0.4	1.6	9.3	0.1 ms	9.3	4.7	1.9	0.3	27.4
Visual, GLB	0.4	1.5	9.4	0.1 ms	8.0	83 ms	0.5	0.3	20.3
Visual, OBJ	0.5	1.6	9.3	0.1 ms	7.8	2.6	0.7	0.3	22.7

Board Repo: winkleplex10-bit/the-mac-pro-project Board: tdr_coupon_c50.kicad_pcb Folder kicad / macpro62-io-modules / tdr / tdr_coupon_c50 Complexity 161 / 1000 (size 126, features 35) KESE features through vias, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 12, 75, 24 Triangles, simulation 639,392 in 18 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 27 MB 543 MB STEP 167 MB 550 MB STL 32 MB 556 MB OBJ 76 MB 599 MB Visual GLB 15 MB 435 MB OBJ 41 MB 418 MB

3035. riser_a

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	18 ms	0.1	0.6	0.1 ms	0.6	25 ms	77 ms	0.2	1.6
Simulation, STEP	15 ms	0.1	0.6	0.1 ms	0.6	0.8	78 ms	0.2	2.4
Simulation, STL	16 ms	0.1	0.6	0.1 ms	0.6	32 ms	66 ms	0.2	1.6
Simulation, OBJ	15 ms	0.1	0.6	0.2 ms	0.6	0.8	72 ms	0.2	2.4
Visual, GLB	15 ms	0.1	0.6	0.1 ms	1.0	15 ms	92 ms	0.2	2.0
Visual, OBJ	17 ms	0.1	0.6	0.1 ms	1.1	0.4	96 ms	0.2	2.5

Board Repo: winkleplex10-bit/the-mac-pro-project Board: riser_a.kicad_pcb Folder kicad / macpro62-io-risers / riser_a Complexity 68 / 1000 (size 48, features 20) KESE features slotted holes, rounded, trapezoid or chamfered pads Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 3, 0, 0 Triangles, simulation 175,292 in 12 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 5.8 MB 190 MB STEP 18 MB 193 MB STL 8.8 MB 195 MB OBJ 17 MB 197 MB Visual GLB 3.2 MB 138 MB OBJ 8.9 MB 140 MB

3036. riser_c

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	30 ms	0.1	0.5	0.1 ms	0.7	24 ms	62 ms	0.2	1.7
Simulation, STEP	32 ms	0.1	0.5	0.1 ms	0.8	1.0	68 ms	0.2	2.7
Simulation, STL	31 ms	0.1	0.5	0.1 ms	0.8	42 ms	0.1	0.2	1.8
Simulation, OBJ	31 ms	0.1	0.5	0.1 ms	0.8	0.8	68 ms	0.2	2.6
Visual, GLB	48 ms	0.1	0.5	0.1 ms	1.4	18 ms	0.1	0.3	2.5
Visual, OBJ	31 ms	0.1	0.5	0.1 ms	1.3	0.6	0.1	0.2	2.9

Board Repo: winkleplex10-bit/the-mac-pro-project Board: riser_c.kicad_pcb Folder kicad / macpro62-io-risers / riser_c Complexity 81 / 1000 (size 51, features 30) KESE features slotted holes, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 4, 0, 0 Triangles, simulation 139,356 in 12 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 4.9 MB 180 MB STEP 19 MB 192 MB STL 7.0 MB 180 MB OBJ 14 MB 181 MB Visual GLB 3.6 MB 146 MB OBJ 10 MB 139 MB

3037. riser_hdmi

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	13 ms	49 ms	0.2	0.1 ms	0.4	13 ms	35 ms	0.2	0.9
Simulation, STEP	11 ms	61 ms	0.2	0.1 ms	0.4	0.7	29 ms	0.2	1.6
Simulation, STL	12 ms	49 ms	0.2	0.1 ms	0.4	14 ms	26 ms	0.2	0.9
Simulation, OBJ	11 ms	56 ms	0.2	0.1 ms	0.4	0.3	28 ms	0.2	1.2
Visual, GLB	11 ms	48 ms	0.2	0.1 ms	0.5	7 ms	55 ms	0.2	1.0
Visual, OBJ	12 ms	46 ms	0.2	0.1 ms	0.5	0.3	52 ms	0.2	1.4

Board Repo: winkleplex10-bit/the-mac-pro-project Board: riser_hdmi.kicad_pcb Folder kicad / macpro62-io-risers / riser_hdmi Complexity 65 / 1000 (size 45, features 20) KESE features slotted holes, rounded, trapezoid or chamfered pads Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 2, 0, 0 Triangles, simulation 64,084 in 12 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 2.3 MB 53 MB STEP 11 MB 166 MB STL 3.2 MB 53 MB OBJ 6.3 MB 68 MB Visual GLB 1.6 MB 89 MB OBJ 4.5 MB 82 MB

3038. macpro62_lga1700

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	2.2	13.0	0.1 ms	17.2	0.4	0.8	0.3	34.5
Simulation, STEP	0.5	2.2	12.9	0.1 ms	17.7	9.2	0.8	0.3	43.6
Simulation, STL	0.6	2.1	13.4	0.2 ms	16.8	1.0	0.8	0.2	35.1
Simulation, OBJ	0.6	2.2	12.6	0.1 ms	17.7	13.7	0.8	0.3	47.9
Visual, GLB	0.5	2.1	13.0	0.1 ms	30.7	0.4	3.6	0.2	50.5
Visual, OBJ	0.5	2.2	12.8	0.2 ms	31.2	12.3	4.6	0.3	63.9

Board Repo: winkleplex10-bit/the-mac-pro-project Board: macpro62_lga1700.kicad_pcb Folder kicad / macpro62-lga1700-v2 Complexity 217 / 1000 (size 162, features 55) KESE features curved board outline, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 10 File format KiCad 9 (20241229) Parts, tracks, vias 24, 0, 0 Triangles, simulation 2,922,588 in 26 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 103 MB 1.2 GB STEP 402 MB 1.6 GB STL 146 MB 1.2 GB OBJ 319 MB 2.0 GB Visual GLB 90 MB 1.9 GB OBJ 287 MB 1.9 GB

3039. macpro62-storage-face-2x

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	6.5	21.3	2 ms	25.0	1.0	2.2	0.4	57.0
Simulation, STEP	0.8	5.9	21.1	2 ms	25.6	9.3	2.1	0.3	65.1
Simulation, STL	0.6	6.3	21.4	3 ms	25.3	2.0	2.0	0.3	57.9
Simulation, OBJ	0.7	6.3	21.2	2 ms	25.4	29.6	2.1	0.3	85.6
Visual, GLB	0.6	6.0	21.2	2 ms	42.1	0.4	5.0	0.3	75.7
Visual, OBJ	0.7	6.1	20.6	2 ms	43.4	12.1	5.2	0.3	88.3

Board Repo: winkleplex10-bit/the-mac-pro-project Board: macpro62-storage-face-2x.kicad_pcb Folder kicad / macpro62-storage-face-2x Complexity 363 / 1000 (size 228, features 135) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 85, 1,215, 2,048 Triangles, simulation 5,621,626 in 180 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 186 MB 1.8 GB STEP 439 MB 2.4 GB STL 281 MB 1.8 GB OBJ 593 MB 3.6 GB Visual GLB 85 MB 1.6 GB OBJ 274 MB 1.8 GB

3040. macpro62-storage-face

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.7	2.8	0.3 ms	2.7	0.1	0.3	0.2	7.0
Simulation, STEP	0.3	0.6	2.9	0.2 ms	2.8	2.5	0.3	0.2	9.5
Simulation, STL	0.3	0.6	2.9	0.2 ms	2.8	0.2	0.3	0.2	7.3
Simulation, OBJ	0.3	0.6	2.9	0.2 ms	2.7	5.0	0.3	0.2	11.9
Visual, GLB	0.3	0.6	2.9	0.3 ms	6.8	0.1	0.7	0.2	11.5
Visual, OBJ	0.3	0.6	2.8	0.2 ms	6.7	3.8	0.7	0.2	15.1

Board Repo: winkleplex10-bit/the-mac-pro-project Board: macpro62-storage-face.kicad_pcb Folder kicad / macpro62-storage-face Complexity 261 / 1000 (size 171, features 90) KESE features slotted holes, custom pads, rounded, trapezoid or chamfered pads, curved board outline, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 58, 6, 0 Triangles, simulation 1,066,172 in 18 parts Note mostly unrouted Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 37 MB 545 MB STEP 166 MB 603 MB STL 53 MB 533 MB OBJ 111 MB 734 MB Visual GLB 28 MB 824 MB OBJ 84 MB 744 MB

3041. fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	2.2	9.4	0.7 ms	7.7	0.3	1.0	0.3	21.4
Simulation, STEP	0.4	2.1	9.4	0.4 ms	7.2	5.5	1.0	0.2	25.7
Simulation, STL	0.5	2.1	9.1	0.5 ms	7.1	0.8	1.0	0.3	20.9
Simulation, OBJ	0.5	2.2	9.4	0.7 ms	7.5	11.1	1.1	0.2	31.9
Visual, GLB	0.4	2.1	9.4	0.5 ms	15.1	0.2	1.6	0.2	29.1
Visual, OBJ	0.4	2.0	9.5	0.5 ms	14.9	6.7	1.9	0.2	35.7

Board Repo: Wren6991/Snowflake-FPGA Board: fpga_hat.kicad_pcb Folder board Complexity 316 / 1000 (size 261, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,081, 164 Triangles, simulation 2,069,882 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 72 MB 768 MB STEP 320 MB 901 MB STL 104 MB 794 MB OBJ 219 MB 1.4 GB Visual GLB 43 MB 873 MB OBJ 131 MB 982 MB

3042. 2019-07-02_12:26:12_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	4 ms	42 ms	4 ms	0.0 ms	83 ms	2 ms	2 ms	0.2	0.3
Simulation, STEP	4 ms	34 ms	11 ms	0.0 ms	84 ms	66 ms	2 ms	0.2	0.4
Simulation, STL	3 ms	42 ms	8 ms	0.1 ms	0.1	3 ms	3 ms	0.2	0.4
Simulation, OBJ	3 ms	34 ms	7 ms	0.0 ms	65 ms	40 ms	3 ms	0.2	0.3
Visual, GLB	4 ms	37 ms	7 ms	0.0 ms	0.1	3 ms	47 ms	0.2	0.4
Visual, OBJ	5 ms	38 ms	4 ms	0.0 ms	0.1	47 ms	51 ms	0.2	0.5

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_12:26:12_fpga_hat.kicad_pcb Folder timelapse Complexity 27 / 1000 (size 17, features 10) KESE features curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 0, 0, 0 Triangles, simulation 10,440 in 3 parts Note no components Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 278 kB 41 MB STEP 1.7 MB 42 MB STL 522 kB 41 MB OBJ 984 kB 43 MB Visual GLB 378 kB 61 MB OBJ 984 kB 77 MB

3043. 2019-07-02_12:31:57_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	4 ms	39 ms	5 ms	0.0 ms	77 ms	2 ms	3 ms	0.2	0.3
Simulation, STEP	5 ms	42 ms	4 ms	0.0 ms	81 ms	64 ms	3 ms	0.2	0.4
Simulation, STL	5 ms	42 ms	5 ms	0.0 ms	80 ms	3 ms	2 ms	0.2	0.4
Simulation, OBJ	3 ms	52 ms	4 ms	0.1 ms	84 ms	50 ms	2 ms	0.2	0.4
Visual, GLB	4 ms	48 ms	4 ms	0.0 ms	0.1	3 ms	54 ms	0.2	0.5
Visual, OBJ	4 ms	37 ms	4 ms	0.0 ms	0.1	86 ms	55 ms	0.2	0.5

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_12:31:57_fpga_hat.kicad_pcb Folder timelapse Complexity 27 / 1000 (size 17, features 10) KESE features curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 0, 0, 0 Triangles, simulation 10,440 in 3 parts Note no components Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 278 kB 41 MB STEP 1.7 MB 42 MB STL 522 kB 41 MB OBJ 984 kB 41 MB Visual GLB 378 kB 67 MB OBJ 984 kB 62 MB

3044. 2019-07-02_12:40:42_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.7	36 ms	0.1 ms	0.1	3 ms	5 ms	0.2	1.2
Simulation, STEP	0.2	0.6	37 ms	0.1 ms	0.1	93 ms	4 ms	0.2	1.3
Simulation, STL	0.3	0.6	51 ms	0.2 ms	0.1	7 ms	5 ms	0.2	1.3
Simulation, OBJ	0.2	0.6	31 ms	0.1 ms	88 ms	62 ms	4 ms	0.2	1.2
Visual, GLB	0.2	0.6	38 ms	0.1 ms	0.2	4 ms	44 ms	0.2	1.3
Visual, OBJ	0.2	0.6	38 ms	0.1 ms	0.1	66 ms	47 ms	0.2	1.3

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_12:40:42_fpga_hat.kicad_pcb Folder timelapse Complexity 160 / 1000 (size 140, features 20) KESE features rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 0, 0 Triangles, simulation 16,832 in 5 parts Note mostly unrouted Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 463 kB 79 MB STEP 1.8 MB 79 MB STL 842 kB 78 MB OBJ 1.6 MB 77 MB Visual GLB 507 kB 105 MB OBJ 1.3 MB 111 MB

3045. 2019-07-02_12:48:58_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.8	1.0	0.2 ms	1.1	39 ms	0.2	0.2	3.7
Simulation, STEP	0.2	0.8	1.1	0.4 ms	1.0	1.0	0.2	0.2	4.4
Simulation, STL	0.2	0.9	1.1	0.2 ms	1.0	58 ms	0.2	0.2	3.5
Simulation, OBJ	0.2	0.8	1.0	0.4 ms	1.0	1.3	0.2	0.2	4.6
Visual, GLB	0.2	0.8	1.0	0.2 ms	1.7	16 ms	0.1	0.2	4.1
Visual, OBJ	0.2	0.8	1.0	0.3 ms	1.6	0.5	0.1	0.2	4.5

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_12:48:58_fpga_hat.kicad_pcb Folder timelapse Complexity 160 / 1000 (size 140, features 20) KESE features rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 0, 0 Triangles, simulation 268,520 in 43 parts Note mostly unrouted Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 8.4 MB 226 MB STEP 32 MB 236 MB STL 13 MB 224 MB OBJ 26 MB 235 MB Visual GLB 3.6 MB 173 MB OBJ 10 MB 179 MB

3046. 2019-07-02_13:01:55_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.9	2.2	0.4 ms	1.8	91 ms	0.3	0.2	5.8
Simulation, STEP	0.2	1.2	2.4	0.4 ms	1.8	1.8	0.3	0.2	7.9
Simulation, STL	0.2	1.0	2.3	0.3 ms	1.9	0.1	0.3	0.2	6.1
Simulation, OBJ	0.2	1.0	2.3	0.4 ms	1.8	3.2	0.4	0.2	9.2
Visual, GLB	0.2	1.0	2.2	0.3 ms	2.9	41 ms	0.4	0.2	7.1
Visual, OBJ	0.3	1.0	2.4	0.4 ms	2.7	1.2	0.2	0.2	8.1

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_13:01:55_fpga_hat.kicad_pcb Folder timelapse Complexity 160 / 1000 (size 140, features 20) KESE features rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 0, 0 Triangles, simulation 568,796 in 82 parts Note mostly unrouted Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 18 MB 275 MB STEP 70 MB 327 MB STL 28 MB 284 MB OBJ 57 MB 421 MB Visual GLB 8.1 MB 298 MB OBJ 24 MB 288 MB

3047. 2019-07-02_13:07:01_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.1	2.7	0.4 ms	2.1	0.1	0.3	0.2	7.0
Simulation, STEP	0.3	1.2	2.8	0.5 ms	2.1	1.9	0.3	0.2	8.8
Simulation, STL	0.3	1.1	2.6	0.7 ms	2.1	0.1	0.4	0.2	6.8
Simulation, OBJ	0.3	1.2	2.8	0.5 ms	2.1	3.4	0.4	0.2	10.4
Visual, GLB	0.2	1.2	2.6	0.5 ms	3.4	44 ms	0.5	0.2	8.2
Visual, OBJ	0.3	1.1	2.6	0.4 ms	3.5	1.4	0.5	0.2	9.7

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_13:07:01_fpga_hat.kicad_pcb Folder timelapse Complexity 160 / 1000 (size 140, features 20) KESE features rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 0, 0 Triangles, simulation 594,544 in 95 parts Note mostly unrouted Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 19 MB 304 MB STEP 75 MB 333 MB STL 30 MB 312 MB OBJ 60 MB 436 MB Visual GLB 8.7 MB 317 MB OBJ 26 MB 291 MB

3048. 2019-07-02_13:19:55_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.0	2.3	0.5 ms	1.9	89 ms	0.3	0.2	6.0
Simulation, STEP	0.2	1.0	2.4	0.4 ms	2.0	1.7	0.3	0.3	7.9
Simulation, STL	0.2	1.1	2.3	0.3 ms	2.0	0.1	0.3	0.2	6.3
Simulation, OBJ	0.2	1.1	2.4	0.3 ms	1.9	3.2	0.3	0.2	9.4
Visual, GLB	0.2	1.0	2.4	0.4 ms	3.2	42 ms	0.4	0.2	7.5
Visual, OBJ	0.2	1.1	2.4	0.4 ms	3.3	1.4	0.4	0.2	9.0

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_13:19:55_fpga_hat.kicad_pcb Folder timelapse Complexity 160 / 1000 (size 140, features 20) KESE features rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 0, 0 Triangles, simulation 632,078 in 102 parts Note mostly unrouted Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 20 MB 308 MB STEP 83 MB 347 MB STL 32 MB 316 MB OBJ 64 MB 458 MB Visual GLB 9.8 MB 315 MB OBJ 29 MB 316 MB

3049. 2019-07-02_13:30:37_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.5	4.2	0.5 ms	3.3	0.1	0.5	0.3	10.2
Simulation, STEP	0.3	1.5	4.3	0.5 ms	3.3	2.9	0.5	0.3	12.9
Simulation, STL	0.3	1.3	4.3	0.6 ms	3.2	0.2	0.4	0.3	10.0
Simulation, OBJ	0.3	1.4	4.2	0.5 ms	3.2	5.0	0.4	0.2	14.6
Visual, GLB	0.3	1.3	4.0	0.5 ms	5.8	68 ms	0.9	0.2	12.5
Visual, OBJ	0.3	1.4	4.2	0.7 ms	5.5	2.4	0.8	0.3	14.8

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_13:30:37_fpga_hat.kicad_pcb Folder timelapse Complexity 160 / 1000 (size 140, features 20) KESE features rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 0, 0 Triangles, simulation 853,966 in 148 parts Note mostly unrouted Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 28 MB 355 MB STEP 128 MB 474 MB STL 43 MB 363 MB OBJ 87 MB 617 MB Visual GLB 14 MB 422 MB OBJ 42 MB 427 MB

3050. 2019-07-02_13:46:31_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.3	3.9	0.4 ms	3.1	0.1	0.4	0.2	9.2
Simulation, STEP	0.2	1.2	3.7	0.4 ms	3.0	2.8	0.4	0.2	11.4
Simulation, STL	0.2	1.4	3.7	0.4 ms	3.0	0.2	0.4	0.2	9.1
Simulation, OBJ	0.2	1.3	3.5	0.5 ms	3.2	4.6	0.4	0.3	13.6
Visual, GLB	0.3	1.2	3.7	0.5 ms	5.4	63 ms	0.5	0.2	11.5
Visual, OBJ	0.2	1.2	3.6	0.5 ms	5.2	2.1	0.6	0.2	13.2

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_13:46:31_fpga_hat.kicad_pcb Folder timelapse Complexity 160 / 1000 (size 140, features 20) KESE features rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 0, 0 Triangles, simulation 902,386 in 150 parts Note mostly unrouted Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 30 MB 377 MB STEP 138 MB 481 MB STL 45 MB 367 MB OBJ 92 MB 670 MB Visual GLB 15 MB 432 MB OBJ 45 MB 426 MB

3051. 2019-07-02_13:56:17_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.2	3.7	0.6 ms	3.0	0.1	0.4	0.2	8.9
Simulation, STEP	0.3	1.3	3.8	0.7 ms	3.2	2.7	0.4	0.2	11.8
Simulation, STL	0.2	1.3	3.8	0.7 ms	3.3	0.3	0.4	0.2	9.4
Simulation, OBJ	0.2	1.3	3.6	0.7 ms	3.3	4.5	0.4	0.2	13.5
Visual, GLB	0.2	1.2	3.6	0.5 ms	5.7	67 ms	0.5	0.2	11.6
Visual, OBJ	0.2	1.2	3.6	0.4 ms	5.3	2.3	0.6	0.2	13.5

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_13:56:17_fpga_hat.kicad_pcb Folder timelapse Complexity 160 / 1000 (size 140, features 20) KESE features rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 0, 0 Triangles, simulation 920,616 in 150 parts Note mostly unrouted Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 30 MB 377 MB STEP 141 MB 500 MB STL 46 MB 379 MB OBJ 94 MB 654 MB Visual GLB 16 MB 470 MB OBJ 47 MB 445 MB

3052. 2019-07-02_14:01:06_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.0	3.2	0.6 ms	3.2	0.1	0.4	0.2	8.4
Simulation, STEP	0.2	1.1	3.5	1 ms	3.1	2.5	0.4	0.2	11.0
Simulation, STL	0.2	1.2	3.4	0.5 ms	3.1	0.2	0.4	0.2	8.8
Simulation, OBJ	0.2	1.2	3.4	0.5 ms	3.1	3.9	0.4	0.2	12.4
Visual, GLB	0.2	1.1	3.2	0.5 ms	5.6	66 ms	0.6	0.2	11.0
Visual, OBJ	0.2	1.1	3.4	0.7 ms	5.5	2.0	0.6	0.2	12.9

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_14:01:06_fpga_hat.kicad_pcb Folder timelapse Complexity 160 / 1000 (size 140, features 20) KESE features rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 0, 0 Triangles, simulation 957,960 in 150 parts Note mostly unrouted Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 32 MB 395 MB STEP 150 MB 497 MB STL 48 MB 398 MB OBJ 97 MB 695 MB Visual GLB 17 MB 483 MB OBJ 49 MB 458 MB

3053. 2019-07-02_14:14:35_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.1	3.7	0.4 ms	3.3	0.1	0.4	0.2	9.0
Simulation, STEP	0.2	1.1	3.6	0.4 ms	3.1	2.6	0.4	0.2	11.3
Simulation, STL	0.2	1.1	3.6	0.4 ms	3.1	0.3	0.4	0.2	8.8
Simulation, OBJ	0.2	1.1	3.9	0.4 ms	3.1	4.2	0.3	0.2	13.0
Visual, GLB	0.2	1.0	3.7	0.7 ms	5.5	69 ms	0.6	0.2	11.4
Visual, OBJ	0.2	1.1	3.7	0.4 ms	5.7	2.0	0.8	0.2	13.8

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_14:14:35_fpga_hat.kicad_pcb Folder timelapse Complexity 160 / 1000 (size 140, features 20) KESE features rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 0, 0 Triangles, simulation 1,005,282 in 150 parts Note mostly unrouted Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 33 MB 402 MB STEP 160 MB 527 MB STL 50 MB 408 MB OBJ 102 MB 729 MB Visual GLB 18 MB 479 MB OBJ 52 MB 470 MB

3054. 2019-07-02_15:12:10_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.3	4.1	0.7 ms	3.4	0.2	0.4	0.2	9.7
Simulation, STEP	0.2	1.3	3.9	0.5 ms	3.1	2.7	0.4	0.2	11.9
Simulation, STL	0.2	1.1	3.9	0.4 ms	3.4	0.3	0.4	0.2	9.6
Simulation, OBJ	0.2	1.3	4.0	0.5 ms	3.3	4.0	0.4	0.2	13.4
Visual, GLB	0.2	1.2	3.7	0.5 ms	6.0	77 ms	0.7	0.2	12.2
Visual, OBJ	0.2	1.2	3.8	0.4 ms	5.7	2.2	0.7	0.3	14.2

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_15:12:10_fpga_hat.kicad_pcb Folder timelapse Complexity 160 / 1000 (size 140, features 20) KESE features rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 0, 0 Triangles, simulation 1,005,282 in 150 parts Note mostly unrouted Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 33 MB 409 MB STEP 160 MB 514 MB STL 50 MB 402 MB OBJ 102 MB 727 MB Visual GLB 18 MB 471 MB OBJ 52 MB 505 MB

3055. 2019-07-02_15:26:14_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.3	4.3	0.9 ms	3.6	0.2	0.4	0.2	10.2
Simulation, STEP	0.2	1.4	4.7	0.5 ms	3.5	2.6	0.4	0.3	13.1
Simulation, STL	0.2	1.4	4.7	0.7 ms	3.5	0.3	0.4	0.2	10.7
Simulation, OBJ	0.2	1.3	4.7	0.6 ms	3.5	5.0	0.5	0.2	15.5
Visual, GLB	0.2	1.3	4.5	0.5 ms	7.0	65 ms	0.8	0.2	14.1
Visual, OBJ	0.2	1.3	4.7	0.5 ms	6.6	2.5	0.9	0.3	16.5

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_15:26:14_fpga_hat.kicad_pcb Folder timelapse Complexity 243 / 1000 (size 208, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 25, 13 Triangles, simulation 1,049,378 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 35 MB 405 MB STEP 165 MB 517 MB STL 52 MB 411 MB OBJ 107 MB 730 MB Visual GLB 19 MB 475 MB OBJ 55 MB 476 MB

3056. 2019-07-02_15:37:58_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.4	5.3	0.6 ms	3.8	0.2	0.5	0.3	11.7
Simulation, STEP	0.2	1.3	4.9	0.7 ms	4.0	3.0	0.5	0.2	14.0
Simulation, STL	0.2	1.4	4.7	0.7 ms	3.7	0.3	0.5	0.2	11.1
Simulation, OBJ	0.2	1.4	4.9	0.7 ms	3.9	5.0	0.5	0.2	16.1
Visual, GLB	0.2	1.5	4.9	0.7 ms	7.3	75 ms	0.7	0.2	14.9
Visual, OBJ	0.2	1.4	5.1	0.6 ms	7.5	2.6	1.1	0.2	18.1

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_15:37:58_fpga_hat.kicad_pcb Folder timelapse Complexity 244 / 1000 (size 209, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 28, 13 Triangles, simulation 1,051,284 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 35 MB 413 MB STEP 165 MB 529 MB STL 53 MB 451 MB OBJ 107 MB 754 MB Visual GLB 19 MB 495 MB OBJ 55 MB 491 MB

3057. 2019-07-02_15:42:42_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.2	4.6	0.8 ms	3.3	0.2	0.4	0.2	10.1
Simulation, STEP	0.2	1.2	4.8	0.6 ms	3.3	2.7	0.5	0.2	12.9
Simulation, STL	0.3	1.2	4.7	0.7 ms	3.9	0.3	0.5	0.2	11.1
Simulation, OBJ	0.2	1.2	4.4	0.5 ms	3.5	4.4	0.4	0.2	14.3
Visual, GLB	0.3	1.2	4.6	0.4 ms	6.7	72 ms	0.6	0.2	13.6
Visual, OBJ	0.2	1.4	4.6	0.5 ms	6.0	2.7	0.9	0.3	16.1

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_15:42:42_fpga_hat.kicad_pcb Folder timelapse Complexity 264 / 1000 (size 209, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 28, 13 Triangles, simulation 1,080,820 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 36 MB 414 MB STEP 169 MB 521 MB STL 54 MB 414 MB OBJ 110 MB 783 MB Visual GLB 19 MB 475 MB OBJ 55 MB 492 MB

3058. 2019-07-02_15:44:50_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.6	6.0	0.6 ms	4.7	0.2	0.6	0.3	13.7
Simulation, STEP	0.3	1.6	6.0	0.7 ms	4.4	3.7	0.5	0.3	16.9
Simulation, STL	0.3	1.7	6.0	0.6 ms	4.5	0.3	0.5	0.3	13.6
Simulation, OBJ	0.3	1.6	5.9	1.0 ms	4.5	6.6	0.6	0.3	19.8
Visual, GLB	0.3	1.7	5.9	0.7 ms	8.2	96 ms	0.8	0.2	17.2
Visual, OBJ	0.3	1.6	6.1	0.8 ms	8.1	3.2	0.8	0.3	20.3

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_15:44:50_fpga_hat.kicad_pcb Folder timelapse Complexity 244 / 1000 (size 209, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 10th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 28, 13 Triangles, simulation 1,051,284 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 35 MB 404 MB STEP 165 MB 530 MB STL 53 MB 411 MB OBJ 107 MB 747 MB Visual GLB 19 MB 484 MB OBJ 55 MB 494 MB

3059. 2019-07-02_15:48:31_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.5	5.1	0.7 ms	4.0	0.2	0.5	0.3	11.9
Simulation, STEP	0.3	1.6	5.4	0.5 ms	4.0	3.1	0.5	0.2	15.1
Simulation, STL	0.3	1.5	5.2	0.6 ms	4.0	0.4	0.5	0.3	12.1
Simulation, OBJ	0.2	1.6	5.4	0.9 ms	4.1	5.2	0.6	0.3	17.4
Visual, GLB	0.3	1.5	5.2	0.6 ms	8.1	96 ms	0.9	0.2	16.2
Visual, OBJ	0.3	1.6	5.3	0.5 ms	8.1	2.5	1.0	0.2	19.0

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_15:48:31_fpga_hat.kicad_pcb Folder timelapse Complexity 264 / 1000 (size 209, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 28, 13 Triangles, simulation 1,080,488 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 36 MB 415 MB STEP 169 MB 517 MB STL 54 MB 406 MB OBJ 110 MB 784 MB Visual GLB 19 MB 479 MB OBJ 55 MB 493 MB

3060. 2019-07-02_17:02:16_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.4	5.5	0.6 ms	4.0	0.2	0.4	0.2	11.9
Simulation, STEP	0.2	1.4	5.5	0.5 ms	3.9	3.1	0.4	0.2	14.7
Simulation, STL	0.2	1.4	5.2	0.6 ms	3.8	0.3	0.5	0.2	11.6
Simulation, OBJ	0.2	1.3	5.3	0.6 ms	3.7	5.5	0.5	0.2	16.7
Visual, GLB	0.2	1.4	5.5	0.7 ms	7.0	85 ms	0.7	0.2	15.1
Visual, OBJ	0.2	1.3	5.5	0.6 ms	7.4	2.9	0.8	0.2	18.3

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_17:02:16_fpga_hat.kicad_pcb Folder timelapse Complexity 271 / 1000 (size 236, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 314, 15 Triangles, simulation 1,104,480 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 37 MB 445 MB STEP 181 MB 560 MB STL 55 MB 429 MB OBJ 113 MB 798 MB Visual GLB 20 MB 562 MB OBJ 60 MB 526 MB

3061. 2019-07-02_17:04:43_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.6	6.2	0.6 ms	4.3	0.2	0.5	0.3	13.4
Simulation, STEP	0.3	1.6	6.3	0.7 ms	4.1	3.6	0.6	0.3	16.7
Simulation, STL	0.3	1.5	6.4	0.6 ms	4.2	0.4	0.5	0.3	13.7
Simulation, OBJ	0.3	1.6	6.4	0.6 ms	4.3	6.8	0.6	0.2	20.2
Visual, GLB	0.3	1.6	6.2	0.6 ms	8.3	0.1	1.0	0.3	17.8
Visual, OBJ	0.3	1.5	6.3	1.0 ms	8.3	3.4	1.0	0.2	21.1

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_17:04:43_fpga_hat.kicad_pcb Folder timelapse Complexity 271 / 1000 (size 236, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 314, 15 Triangles, simulation 1,105,008 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 37 MB 423 MB STEP 181 MB 549 MB STL 55 MB 449 MB OBJ 113 MB 783 MB Visual GLB 20 MB 513 MB OBJ 61 MB 526 MB

3062. 2019-07-02_17:57:29_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.4	5.6	0.6 ms	3.8	0.2	0.5	0.2	11.9
Simulation, STEP	0.2	1.4	5.8	0.5 ms	3.8	3.1	0.5	0.2	15.0
Simulation, STL	0.2	1.4	5.7	0.6 ms	3.9	0.3	0.5	0.2	12.1
Simulation, OBJ	0.2	1.4	5.7	0.5 ms	3.8	5.7	0.5	0.2	17.5
Visual, GLB	0.3	1.3	5.7	0.5 ms	7.3	96 ms	0.6	0.2	15.5
Visual, OBJ	0.2	1.3	5.7	0.6 ms	7.0	3.0	0.6	0.2	18.1

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_17:57:29_fpga_hat.kicad_pcb Folder timelapse Complexity 274 / 1000 (size 239, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 369, 15 Triangles, simulation 1,111,608 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 38 MB 424 MB STEP 183 MB 577 MB STL 56 MB 439 MB OBJ 114 MB 779 MB Visual GLB 21 MB 548 MB OBJ 61 MB 553 MB

3063. 2019-07-02_18:04:43_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.4	5.6	0.8 ms	4.0	0.2	0.4	0.3	12.1
Simulation, STEP	0.3	1.4	5.5	0.6 ms	4.0	3.0	0.5	0.2	15.0
Simulation, STL	0.2	1.4	5.7	0.6 ms	4.1	0.3	0.5	0.2	12.4
Simulation, OBJ	0.2	1.3	5.7	0.4 ms	4.0	5.2	0.4	0.3	17.2
Visual, GLB	0.3	1.4	5.7	0.7 ms	7.9	90 ms	0.8	0.3	16.4
Visual, OBJ	0.2	1.3	5.7	0.7 ms	7.6	3.2	0.9	0.2	19.1

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_18:04:43_fpga_hat.kicad_pcb Folder timelapse Complexity 275 / 1000 (size 240, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 403, 16 Triangles, simulation 1,121,362 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 38 MB 461 MB STEP 185 MB 561 MB STL 56 MB 471 MB OBJ 115 MB 795 MB Visual GLB 21 MB 506 MB OBJ 62 MB 538 MB

3064. 2019-07-02_18:08:42_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.2	5.1	1 ms	3.7	0.2	0.4	0.2	11.1
Simulation, STEP	0.3	1.3	5.2	0.6 ms	3.5	2.7	0.4	0.2	13.5
Simulation, STL	0.2	1.2	5.0	0.6 ms	3.6	0.4	0.4	0.2	11.0
Simulation, OBJ	0.3	1.2	5.2	0.6 ms	3.6	4.7	0.4	0.3	15.6
Visual, GLB	0.2	1.2	5.2	0.9 ms	7.2	92 ms	1.0	0.2	15.1
Visual, OBJ	0.2	1.2	5.1	0.6 ms	6.8	2.3	0.9	0.2	16.7

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_18:08:42_fpga_hat.kicad_pcb Folder timelapse Complexity 275 / 1000 (size 240, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 413, 16 Triangles, simulation 1,122,554 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 38 MB 443 MB STEP 185 MB 563 MB STL 56 MB 457 MB OBJ 115 MB 790 MB Visual GLB 21 MB 554 MB OBJ 62 MB 560 MB

3065. 2019-07-02_18:15:30_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.3	5.6	0.9 ms	3.7	0.2	0.4	0.2	11.6
Simulation, STEP	0.2	1.4	5.3	0.9 ms	3.7	3.1	0.5	0.3	14.5
Simulation, STL	0.2	1.4	5.7	0.4 ms	3.8	0.2	0.5	0.2	12.1
Simulation, OBJ	0.2	1.3	5.5	0.6 ms	3.8	5.3	0.5	0.2	16.9
Visual, GLB	0.3	1.4	5.4	0.7 ms	7.7	97 ms	0.8	0.3	15.9
Visual, OBJ	0.3	1.3	5.5	0.6 ms	7.4	2.8	0.7	0.3	18.1

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_18:15:30_fpga_hat.kicad_pcb Folder timelapse Complexity 277 / 1000 (size 242, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 472, 16 Triangles, simulation 1,131,028 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 38 MB 456 MB STEP 188 MB 580 MB STL 57 MB 471 MB OBJ 116 MB 800 MB Visual GLB 21 MB 560 MB OBJ 63 MB 531 MB

3066. 2019-07-02_18:19:44_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.4	5.9	0.5 ms	3.9	0.2	0.5	0.2	12.3
Simulation, STEP	0.3	1.3	5.9	0.5 ms	4.0	3.1	0.5	0.3	15.3
Simulation, STL	0.3	1.4	5.9	0.5 ms	3.9	0.3	0.5	0.2	12.5
Simulation, OBJ	0.2	1.3	6.0	0.8 ms	3.9	5.9	0.5	0.2	18.0
Visual, GLB	0.2	1.4	6.0	0.5 ms	7.2	91 ms	0.6	0.2	15.7
Visual, OBJ	0.2	1.3	5.8	0.5 ms	7.3	3.2	0.6	0.2	18.7

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_18:19:44_fpga_hat.kicad_pcb Folder timelapse Complexity 278 / 1000 (size 243, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 493, 16 Triangles, simulation 1,133,566 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 38 MB 481 MB STEP 189 MB 586 MB STL 57 MB 436 MB OBJ 116 MB 805 MB Visual GLB 21 MB 528 MB OBJ 63 MB 532 MB

3067. 2019-07-02_18:26:57_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.3	5.9	0.6 ms	4.1	0.2	0.5	0.2	12.5
Simulation, STEP	0.2	1.4	6.0	0.6 ms	4.0	3.1	0.5	0.2	15.5
Simulation, STL	0.3	1.4	5.9	1 ms	4.1	0.5	0.5	0.3	12.9
Simulation, OBJ	0.3	1.4	6.0	0.7 ms	5.0	5.9	0.5	0.2	19.3
Visual, GLB	0.3	1.5	5.7	0.6 ms	8.3	0.1	1.0	0.2	17.1
Visual, OBJ	0.2	1.3	5.8	1 ms	8.3	2.7	1.1	0.2	19.7

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_18:26:57_fpga_hat.kicad_pcb Folder timelapse Complexity 279 / 1000 (size 244, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 516, 16 Triangles, simulation 1,136,668 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 39 MB 436 MB STEP 189 MB 559 MB STL 57 MB 471 MB OBJ 117 MB 812 MB Visual GLB 21 MB 598 MB OBJ 64 MB 564 MB

3068. 2019-07-02_18:32:13_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.5	5.5	0.6 ms	3.7	0.2	0.4	0.3	11.8
Simulation, STEP	0.2	1.4	5.6	0.4 ms	3.8	3.0	0.5	0.3	14.7
Simulation, STL	0.2	1.4	5.5	0.5 ms	3.8	0.3	0.5	0.2	12.0
Simulation, OBJ	0.3	1.4	5.7	0.6 ms	3.7	5.4	0.5	0.2	17.1
Visual, GLB	0.2	1.3	5.4	0.6 ms	7.6	94 ms	0.7	0.2	15.5
Visual, OBJ	0.2	1.3	5.6	0.6 ms	8.0	2.5	1.0	0.2	18.8

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_18:32:13_fpga_hat.kicad_pcb Folder timelapse Complexity 279 / 1000 (size 244, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 528, 16 Triangles, simulation 1,137,620 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 39 MB 468 MB STEP 190 MB 587 MB STL 57 MB 470 MB OBJ 117 MB 827 MB Visual GLB 21 MB 555 MB OBJ 64 MB 565 MB

3069. 2019-07-02_18:37:57_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.4	5.6	0.8 ms	3.7	0.2	0.4	0.3	11.9
Simulation, STEP	0.2	1.5	5.7	0.8 ms	3.9	3.0	0.5	0.2	15.0
Simulation, STL	0.2	1.5	5.5	0.5 ms	3.8	0.3	0.5	0.2	12.1
Simulation, OBJ	0.2	1.4	5.1	0.7 ms	3.6	4.9	0.5	0.2	16.0
Visual, GLB	0.2	1.5	5.7	0.6 ms	7.8	99 ms	0.9	0.2	16.5
Visual, OBJ	0.2	1.3	5.4	0.5 ms	7.7	2.8	1.0	0.2	18.7

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_18:37:57_fpga_hat.kicad_pcb Folder timelapse Complexity 280 / 1000 (size 245, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 555, 16 Triangles, simulation 1,138,788 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 39 MB 454 MB STEP 190 MB 591 MB STL 57 MB 464 MB OBJ 117 MB 811 MB Visual GLB 21 MB 569 MB OBJ 64 MB 554 MB

3070. 2019-07-02_19:05:24_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.4	5.9	0.5 ms	4.0	0.2	0.4	0.2	12.5
Simulation, STEP	0.2	1.4	5.8	0.6 ms	3.9	3.4	0.5	0.2	15.4
Simulation, STL	0.2	1.4	5.8	0.6 ms	4.0	0.4	0.5	0.2	12.5
Simulation, OBJ	0.2	1.3	5.7	0.5 ms	4.1	6.0	0.5	0.2	18.1
Visual, GLB	0.3	1.4	6.0	0.6 ms	7.9	89 ms	0.7	0.2	16.6
Visual, OBJ	0.2	1.3	5.6	0.8 ms	8.1	3.4	1.0	0.2	19.9

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_19:05:24_fpga_hat.kicad_pcb Folder timelapse Complexity 280 / 1000 (size 245, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 552, 16 Triangles, simulation 1,136,098 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 39 MB 484 MB STEP 190 MB 590 MB STL 57 MB 469 MB OBJ 117 MB 831 MB Visual GLB 21 MB 509 MB OBJ 64 MB 561 MB

3071. 2019-07-02_19:17:13_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.4	6.0	0.6 ms	4.1	0.2	0.5	0.3	12.8
Simulation, STEP	0.3	1.4	6.0	0.7 ms	4.3	3.4	0.5	0.2	16.1
Simulation, STL	0.3	1.6	6.0	0.5 ms	4.2	0.4	0.5	0.3	13.3
Simulation, OBJ	0.3	1.5	5.9	0.6 ms	4.2	5.7	0.5	0.2	18.4
Visual, GLB	0.3	1.4	5.9	0.7 ms	8.7	99 ms	1.0	0.2	17.7
Visual, OBJ	0.3	1.5	5.9	0.6 ms	8.4	3.1	1.2	0.3	20.6

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_19:17:13_fpga_hat.kicad_pcb Folder timelapse Complexity 279 / 1000 (size 244, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 547, 16 Triangles, simulation 1,133,988 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 38 MB 452 MB STEP 189 MB 574 MB STL 57 MB 472 MB OBJ 117 MB 808 MB Visual GLB 21 MB 581 MB OBJ 63 MB 531 MB

3072. 2019-07-02_19:35:16_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.6	6.7	0.7 ms	4.4	0.2	0.6	0.2	13.9
Simulation, STEP	0.3	1.6	6.5	0.7 ms	4.4	3.5	0.5	0.2	17.0
Simulation, STL	0.3	1.5	6.6	0.6 ms	4.5	0.4	0.6	0.2	14.2
Simulation, OBJ	0.3	1.6	6.6	0.7 ms	4.3	6.7	0.6	0.3	20.3
Visual, GLB	0.3	1.7	6.8	0.6 ms	8.7	0.1	1.1	0.2	18.9
Visual, OBJ	0.3	1.6	6.6	0.8 ms	8.8	3.7	1.1	0.2	22.4

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_19:35:16_fpga_hat.kicad_pcb Folder timelapse Complexity 279 / 1000 (size 244, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 536, 16 Triangles, simulation 1,130,672 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 38 MB 475 MB STEP 188 MB 569 MB STL 57 MB 464 MB OBJ 116 MB 813 MB Visual GLB 21 MB 559 MB OBJ 63 MB 560 MB

3073. 2019-07-02_19:45:35_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.4	5.4	0.9 ms	3.7	0.2	0.5	0.3	11.7
Simulation, STEP	0.2	1.2	5.4	0.7 ms	3.8	3.0	0.5	0.2	14.2
Simulation, STL	0.2	1.3	5.2	0.6 ms	3.8	0.3	0.4	0.2	11.5
Simulation, OBJ	0.2	1.3	5.2	0.9 ms	3.7	5.2	0.5	0.2	16.3
Visual, GLB	0.3	1.4	5.3	0.7 ms	7.4	79 ms	0.7	0.2	15.4
Visual, OBJ	0.2	1.3	5.4	0.6 ms	7.8	2.9	1.1	0.2	18.9

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_19:45:35_fpga_hat.kicad_pcb Folder timelapse Complexity 279 / 1000 (size 244, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 534, 16 Triangles, simulation 1,129,370 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 38 MB 451 MB STEP 188 MB 561 MB STL 56 MB 464 MB OBJ 116 MB 802 MB Visual GLB 21 MB 562 MB OBJ 63 MB 524 MB

3074. 2019-07-02_20:01:46_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.3	5.8	0.5 ms	3.8	0.2	0.5	0.2	12.1
Simulation, STEP	0.3	1.3	6.1	0.7 ms	4.2	3.0	0.5	0.2	15.7
Simulation, STL	0.3	1.4	5.8	0.6 ms	3.9	0.3	0.5	0.2	12.3
Simulation, OBJ	0.3	1.3	6.0	0.6 ms	4.1	6.4	0.5	0.2	18.8
Visual, GLB	0.3	1.4	6.0	0.9 ms	8.0	89 ms	0.7	0.2	16.7
Visual, OBJ	0.2	1.3	5.7	0.6 ms	7.5	3.1	0.8	0.2	18.9

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_20:01:46_fpga_hat.kicad_pcb Folder timelapse Complexity 280 / 1000 (size 245, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 545, 20 Triangles, simulation 1,141,196 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 39 MB 419 MB STEP 189 MB 581 MB STL 57 MB 438 MB OBJ 117 MB 804 MB Visual GLB 21 MB 589 MB OBJ 64 MB 515 MB

3075. 2019-07-02_20:17:06_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.3	5.6	0.5 ms	3.8	0.2	0.5	0.2	11.8
Simulation, STEP	0.2	1.3	5.9	0.8 ms	3.7	3.2	0.5	0.2	15.1
Simulation, STL	0.3	1.3	6.0	0.5 ms	4.1	0.3	0.5	0.2	12.6
Simulation, OBJ	0.2	1.3	5.6	0.5 ms	3.9	5.7	0.4	0.2	17.4
Visual, GLB	0.2	1.4	5.8	0.5 ms	7.4	92 ms	0.7	0.2	15.8
Visual, OBJ	0.3	1.3	5.7	0.5 ms	7.5	3.2	0.9	0.2	19.0

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_20:17:06_fpga_hat.kicad_pcb Folder timelapse Complexity 280 / 1000 (size 245, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 559, 20 Triangles, simulation 1,141,628 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 39 MB 437 MB STEP 190 MB 566 MB STL 57 MB 472 MB OBJ 117 MB 829 MB Visual GLB 21 MB 559 MB OBJ 64 MB 535 MB

3076. 2019-07-02_20:28:54_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.6	7.2	0.7 ms	4.9	0.2	0.7	0.3	15.1
Simulation, STEP	0.3	1.7	6.8	0.6 ms	4.8	3.5	0.6	0.3	18.0
Simulation, STL	0.4	1.6	7.2	0.7 ms	4.9	0.4	0.6	0.3	15.4
Simulation, OBJ	0.3	1.7	6.9	0.6 ms	5.0	6.7	0.6	0.3	21.6
Visual, GLB	0.3	1.6	7.5	0.7 ms	10.0	0.2	1.1	0.3	21.0
Visual, OBJ	0.3	1.8	7.4	0.7 ms	10.7	4.1	1.0	0.3	25.6

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_20:28:54_fpga_hat.kicad_pcb Folder timelapse Complexity 281 / 1000 (size 246, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 10th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 594, 25 Triangles, simulation 1,161,144 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 39 MB 450 MB STEP 192 MB 595 MB STL 58 MB 473 MB OBJ 120 MB 839 MB Visual GLB 22 MB 563 MB OBJ 65 MB 563 MB

3077. 2019-07-02_20:54:50_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.5	6.3	0.6 ms	4.3	0.2	0.5	0.2	13.4
Simulation, STEP	0.3	1.4	6.2	0.5 ms	4.3	3.5	0.5	0.3	16.5
Simulation, STL	0.3	1.4	6.6	0.8 ms	4.4	0.4	0.6	0.2	14.0
Simulation, OBJ	0.3	1.6	6.6	0.5 ms	4.4	6.3	0.5	0.2	19.8
Visual, GLB	0.3	1.4	6.2	0.7 ms	8.7	0.1	0.8	0.2	17.6
Visual, OBJ	0.3	1.3	6.0	0.5 ms	8.4	3.6	1.0	0.2	20.9

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_20:54:50_fpga_hat.kicad_pcb Folder timelapse Complexity 283 / 1000 (size 248, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 637, 29 Triangles, simulation 1,179,866 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 40 MB 476 MB STEP 195 MB 587 MB STL 59 MB 449 MB OBJ 122 MB 847 MB Visual GLB 22 MB 575 MB OBJ 66 MB 560 MB

3078. 2019-07-02_21:04:22_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.7	7.0	0.7 ms	4.7	0.3	0.7	0.3	14.9
Simulation, STEP	0.3	1.7	7.0	0.7 ms	4.7	3.4	0.6	0.3	17.9
Simulation, STL	0.3	1.5	6.8	0.6 ms	4.6	0.4	0.6	0.3	14.5
Simulation, OBJ	0.3	1.6	6.8	0.5 ms	4.5	7.2	0.6	0.2	21.3
Visual, GLB	0.3	1.5	6.9	0.9 ms	9.1	0.1	0.9	0.3	19.1
Visual, OBJ	0.3	1.6	6.8	0.5 ms	9.0	3.9	0.8	0.3	22.7

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_21:04:22_fpga_hat.kicad_pcb Folder timelapse Complexity 283 / 1000 (size 248, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 629, 29 Triangles, simulation 1,179,118 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 40 MB 481 MB STEP 195 MB 580 MB STL 59 MB 489 MB OBJ 122 MB 836 MB Visual GLB 22 MB 532 MB OBJ 66 MB 563 MB

3079. 2019-07-02_21:45:21_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.3	5.1	0.6 ms	3.7	0.2	0.4	0.2	11.1
Simulation, STEP	0.2	1.3	5.0	0.5 ms	3.6	2.8	0.4	0.2	13.5
Simulation, STL	0.2	1.1	5.1	0.6 ms	3.6	0.3	0.4	0.2	11.0
Simulation, OBJ	0.2	1.2	5.1	0.6 ms	3.7	4.9	0.4	0.2	15.7
Visual, GLB	0.2	1.2	5.3	0.7 ms	6.9	94 ms	0.7	0.2	14.7
Visual, OBJ	0.2	1.2	5.4	0.7 ms	7.4	2.7	0.8	0.2	18.0

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-02_21:45:21_fpga_hat.kicad_pcb Folder timelapse Complexity 285 / 1000 (size 250, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 722, 30 Triangles, simulation 1,197,164 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 41 MB 453 MB STEP 200 MB 570 MB STL 60 MB 485 MB OBJ 124 MB 840 MB Visual GLB 23 MB 582 MB OBJ 68 MB 612 MB

3080. 2019-07-03_06:45:34_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.4	5.6	0.8 ms	4.1	0.2	0.5	0.3	12.4
Simulation, STEP	0.3	1.4	5.8	0.7 ms	4.0	3.2	0.5	0.3	15.4
Simulation, STL	0.2	1.5	6.0	0.7 ms	4.4	0.4	0.6	0.3	13.4
Simulation, OBJ	0.3	1.5	5.9	0.6 ms	4.2	5.4	0.6	0.2	18.1
Visual, GLB	0.2	1.5	6.0	1 ms	8.3	0.1	0.7	0.2	17.0
Visual, OBJ	0.3	1.5	5.9	0.7 ms	8.0	2.8	0.8	0.2	19.5

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-03_06:45:34_fpga_hat.kicad_pcb Folder timelapse Complexity 285 / 1000 (size 250, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 742, 30 Triangles, simulation 1,197,162 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 41 MB 482 MB STEP 200 MB 573 MB STL 60 MB 446 MB OBJ 124 MB 846 MB Visual GLB 23 MB 537 MB OBJ 68 MB 576 MB

3081. 2019-07-03_06:50:23_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.2	5.4	0.5 ms	3.8	0.2	0.4	0.2	11.5
Simulation, STEP	0.2	1.3	5.4	0.5 ms	3.6	2.8	0.4	0.2	13.9
Simulation, STL	0.2	1.3	5.3	0.6 ms	3.6	0.3	0.5	0.2	11.3
Simulation, OBJ	0.2	1.1	5.3	0.9 ms	3.8	4.9	0.5	0.2	16.0
Visual, GLB	0.2	1.2	5.6	0.6 ms	8.1	93 ms	1.1	0.2	16.4
Visual, OBJ	0.2	1.3	5.6	1 ms	8.1	2.9	0.9	0.2	19.2

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-03_06:50:23_fpga_hat.kicad_pcb Folder timelapse Complexity 285 / 1000 (size 250, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 721, 30 Triangles, simulation 1,195,974 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 41 MB 475 MB STEP 200 MB 571 MB STL 60 MB 483 MB OBJ 124 MB 861 MB Visual GLB 23 MB 515 MB OBJ 68 MB 587 MB

3082. 2019-07-03_07:08:37_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.6	7.2	1 ms	5.1	0.2	0.6	0.2	15.2
Simulation, STEP	0.3	1.6	7.2	1 ms	4.9	3.7	0.6	0.2	18.6
Simulation, STL	0.3	1.7	7.1	0.6 ms	4.6	0.4	0.6	0.3	15.0
Simulation, OBJ	0.3	1.6	6.9	0.6 ms	4.7	7.2	0.7	0.3	21.6
Visual, GLB	0.3	1.6	7.2	1.0 ms	8.9	0.1	0.9	0.2	19.1
Visual, OBJ	0.3	1.6	7.2	1.0 ms	9.4	3.9	0.8	0.3	23.5

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-03_07:08:37_fpga_hat.kicad_pcb Folder timelapse Complexity 285 / 1000 (size 250, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 755, 30 Triangles, simulation 1,199,370 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 41 MB 502 MB STEP 201 MB 580 MB STL 60 MB 462 MB OBJ 124 MB 852 MB Visual GLB 23 MB 585 MB OBJ 69 MB 585 MB

3083. 2019-07-03_07:15:18_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.4	6.3	0.5 ms	4.2	0.2	0.5	0.3	13.1
Simulation, STEP	0.3	1.5	6.3	0.4 ms	4.1	3.2	0.5	0.2	16.1
Simulation, STL	0.3	1.4	6.2	0.6 ms	4.2	0.3	0.5	0.2	13.1
Simulation, OBJ	0.3	1.4	6.2	0.8 ms	4.2	6.3	0.5	0.2	19.1
Visual, GLB	0.3	1.4	6.3	0.8 ms	8.1	0.1	0.7	0.2	17.0
Visual, OBJ	0.3	1.4	6.4	0.6 ms	8.1	3.5	0.7	0.2	20.5

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-03_07:15:18_fpga_hat.kicad_pcb Folder timelapse Complexity 285 / 1000 (size 250, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 761, 30 Triangles, simulation 1,199,694 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 41 MB 490 MB STEP 201 MB 583 MB STL 60 MB 507 MB OBJ 124 MB 851 MB Visual GLB 23 MB 592 MB OBJ 69 MB 536 MB

3084. 2019-07-03_17:28:54_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.4	6.1	0.7 ms	4.0	0.2	0.5	0.3	12.8
Simulation, STEP	0.3	1.4	6.2	0.6 ms	4.1	3.2	0.5	0.3	16.0
Simulation, STL	0.3	1.4	6.2	0.7 ms	4.0	0.3	0.5	0.2	12.9
Simulation, OBJ	0.3	1.3	6.2	0.6 ms	4.0	5.1	0.5	0.2	17.6
Visual, GLB	0.3	1.4	5.8	0.6 ms	8.1	99 ms	0.7	0.2	16.6
Visual, OBJ	0.3	1.5	6.3	0.5 ms	8.6	3.3	0.6	0.2	20.7

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-03_17:28:54_fpga_hat.kicad_pcb Folder timelapse Complexity 286 / 1000 (size 251, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 783, 30 Triangles, simulation 1,200,172 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 41 MB 519 MB STEP 202 MB 576 MB STL 60 MB 496 MB OBJ 124 MB 854 MB Visual GLB 23 MB 568 MB OBJ 69 MB 556 MB

3085. 2019-07-03_17:47:28_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.4	7.1	1 ms	4.6	0.2	0.6	0.3	14.5
Simulation, STEP	0.3	1.6	7.1	0.8 ms	4.7	3.7	0.6	0.3	18.3
Simulation, STL	0.3	1.5	7.0	0.7 ms	4.6	0.5	0.6	0.3	14.8
Simulation, OBJ	0.3	1.4	6.8	0.7 ms	4.5	5.9	0.6	0.2	19.7
Visual, GLB	0.3	1.5	6.5	0.8 ms	9.0	0.1	1.2	0.3	18.8
Visual, OBJ	0.2	1.5	6.5	0.7 ms	9.2	3.4	1.3	0.2	22.4

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-03_17:47:28_fpga_hat.kicad_pcb Folder timelapse Complexity 286 / 1000 (size 251, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 813, 32 Triangles, simulation 1,209,494 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 41 MB 495 MB STEP 204 MB 576 MB STL 60 MB 495 MB OBJ 125 MB 851 MB Visual GLB 23 MB 531 MB OBJ 69 MB 593 MB

3086. 2019-07-03_17:57:53_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.3	5.7	0.8 ms	3.9	0.2	0.4	0.3	12.0
Simulation, STEP	0.2	1.2	5.5	0.6 ms	3.8	2.8	0.5	0.2	14.3
Simulation, STL	0.3	1.3	5.7	0.7 ms	3.8	0.3	0.5	0.2	12.0
Simulation, OBJ	0.2	1.2	5.8	0.6 ms	3.6	4.7	0.5	0.2	16.3
Visual, GLB	0.2	1.2	5.8	0.5 ms	7.5	95 ms	0.9	0.2	15.9
Visual, OBJ	0.2	1.2	5.8	0.6 ms	7.5	2.7	0.9	0.2	18.5

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-03_17:57:53_fpga_hat.kicad_pcb Folder timelapse Complexity 287 / 1000 (size 252, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 826, 32 Triangles, simulation 1,212,256 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 41 MB 540 MB STEP 205 MB 570 MB STL 61 MB 489 MB OBJ 126 MB 864 MB Visual GLB 23 MB 560 MB OBJ 70 MB 600 MB

3087. 2019-07-03_18:11:15_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.4	6.4	0.5 ms	4.0	0.2	0.5	0.2	13.0
Simulation, STEP	0.2	1.2	6.2	0.7 ms	3.9	3.0	0.5	0.2	15.4
Simulation, STL	0.3	1.2	6.2	0.6 ms	4.0	0.3	0.5	0.2	12.7
Simulation, OBJ	0.2	1.3	6.1	0.8 ms	3.9	6.4	0.5	0.2	18.8
Visual, GLB	0.3	1.3	6.4	0.5 ms	7.4	0.1	0.6	0.2	16.3
Visual, OBJ	0.2	1.2	6.2	0.5 ms	7.5	3.3	0.6	0.2	19.2

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-03_18:11:15_fpga_hat.kicad_pcb Folder timelapse Complexity 287 / 1000 (size 252, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 842, 32 Triangles, simulation 1,214,866 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 41 MB 475 MB STEP 206 MB 591 MB STL 61 MB 490 MB OBJ 126 MB 851 MB Visual GLB 23 MB 550 MB OBJ 70 MB 613 MB

3088. 2019-07-03_18:30:05_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.7	8.1	0.8 ms	5.3	0.2	0.7	0.3	16.6
Simulation, STEP	0.3	1.8	7.9	0.6 ms	5.4	4.0	0.6	0.3	20.3
Simulation, STL	0.3	1.8	8.0	0.8 ms	5.1	0.5	0.6	0.2	16.6
Simulation, OBJ	0.3	1.6	7.4	0.6 ms	5.0	7.5	0.7	0.3	22.8
Visual, GLB	0.3	1.7	7.5	0.6 ms	10.0	0.1	1.1	0.2	21.0
Visual, OBJ	0.3	1.6	8.1	1.0 ms	10.3	4.2	1.3	0.2	26.1

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-03_18:30:05_fpga_hat.kicad_pcb Folder timelapse Complexity 287 / 1000 (size 252, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 853, 32 Triangles, simulation 1,216,442 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 41 MB 484 MB STEP 206 MB 595 MB STL 61 MB 507 MB OBJ 126 MB 880 MB Visual GLB 24 MB 608 MB OBJ 70 MB 589 MB

3089. 2019-07-03_18:34:30_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.3	6.0	0.7 ms	4.2	0.2	0.5	0.2	12.8
Simulation, STEP	0.3	1.4	5.8	0.6 ms	4.1	3.3	0.6	0.2	15.6
Simulation, STL	0.2	1.4	6.0	0.6 ms	4.2	0.4	0.6	0.2	12.9
Simulation, OBJ	0.3	1.3	6.1	0.6 ms	4.3	5.4	0.6	0.3	18.2
Visual, GLB	0.3	1.3	6.3	0.9 ms	9.5	99 ms	1.0	0.3	18.7
Visual, OBJ	0.2	1.4	6.8	0.9 ms	8.6	3.1	1.1	0.2	21.4

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-03_18:34:30_fpga_hat.kicad_pcb Folder timelapse Complexity 287 / 1000 (size 252, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 853, 32 Triangles, simulation 1,216,442 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 41 MB 502 MB STEP 206 MB 576 MB STL 61 MB 487 MB OBJ 126 MB 839 MB Visual GLB 24 MB 542 MB OBJ 70 MB 579 MB

3090. 2019-07-05_20:45:15_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.2	5.9	0.5 ms	4.1	0.2	0.6	0.2	12.4
Simulation, STEP	0.3	1.3	5.9	0.6 ms	4.1	3.1	0.5	0.2	15.5
Simulation, STL	0.3	1.3	6.3	0.9 ms	4.4	0.4	0.5	0.2	13.4
Simulation, OBJ	0.2	1.4	5.8	0.6 ms	3.9	5.3	0.6	0.2	17.5
Visual, GLB	0.3	1.2	6.6	0.5 ms	7.6	92 ms	0.7	0.2	16.6
Visual, OBJ	0.2	1.3	6.0	0.6 ms	7.6	2.8	0.9	0.2	19.2

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-05_20:45:15_fpga_hat.kicad_pcb Folder timelapse Complexity 307 / 1000 (size 252, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 856, 32 Triangles, simulation 1,277,596 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 44 MB 505 MB STEP 214 MB 581 MB STL 64 MB 487 MB OBJ 133 MB 881 MB Visual GLB 24 MB 594 MB OBJ 70 MB 591 MB

3091. 2019-07-05_21:08:22_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.3	6.5	0.6 ms	4.3	0.2	0.6	0.2	13.3
Simulation, STEP	0.3	1.3	6.7	0.5 ms	4.2	3.3	0.6	0.2	16.6
Simulation, STL	0.3	1.4	6.4	0.5 ms	4.1	0.4	0.6	0.2	13.4
Simulation, OBJ	0.3	1.3	6.5	0.5 ms	4.1	6.3	0.6	0.2	19.3
Visual, GLB	0.2	1.3	6.3	0.5 ms	8.2	99 ms	0.8	0.2	17.2
Visual, OBJ	0.3	1.3	6.4	0.6 ms	8.3	3.4	0.8	0.2	20.7

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-05_21:08:22_fpga_hat.kicad_pcb Folder timelapse Complexity 287 / 1000 (size 252, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 867, 32 Triangles, simulation 1,206,662 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 41 MB 509 MB STEP 205 MB 582 MB STL 60 MB 471 MB OBJ 125 MB 874 MB Visual GLB 23 MB 591 MB OBJ 69 MB 555 MB

3092. 2019-07-05_21:29:37_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.5	6.2	0.5 ms	4.1	0.2	0.5	0.2	13.0
Simulation, STEP	0.3	1.3	6.4	0.5 ms	4.1	3.1	0.5	0.2	15.9
Simulation, STL	0.3	1.4	6.5	0.6 ms	4.3	0.4	0.6	0.2	13.5
Simulation, OBJ	0.3	1.4	6.4	0.5 ms	4.2	6.1	0.6	0.3	19.3
Visual, GLB	0.2	1.3	6.2	0.6 ms	8.4	98 ms	0.8	0.2	17.2
Visual, OBJ	0.3	1.5	6.4	0.5 ms	8.2	3.5	1.0	0.2	21.0

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-05_21:29:37_fpga_hat.kicad_pcb Folder timelapse Complexity 287 / 1000 (size 252, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 81, 858, 32 Triangles, simulation 1,204,912 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 41 MB 490 MB STEP 204 MB 592 MB STL 60 MB 485 MB OBJ 125 MB 854 MB Visual GLB 23 MB 596 MB OBJ 69 MB 595 MB

3093. 2019-07-05_21:40:20_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.4	6.6	0.7 ms	4.5	0.2	0.6	0.3	13.9
Simulation, STEP	0.4	1.4	6.5	0.9 ms	4.5	3.4	0.6	0.2	16.9
Simulation, STL	0.3	1.5	6.6	0.9 ms	4.6	0.5	0.6	0.3	14.3
Simulation, OBJ	0.3	1.5	6.7	0.7 ms	4.6	5.8	0.6	0.3	19.8
Visual, GLB	0.3	1.5	6.6	0.7 ms	8.9	99 ms	1.0	0.2	18.7
Visual, OBJ	0.3	1.5	7.0	0.8 ms	9.3	3.6	1.0	0.3	23.0

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-05_21:40:20_fpga_hat.kicad_pcb Folder timelapse Complexity 287 / 1000 (size 252, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 858, 32 Triangles, simulation 1,208,428 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 41 MB 498 MB STEP 205 MB 572 MB STL 60 MB 486 MB OBJ 125 MB 859 MB Visual GLB 23 MB 553 MB OBJ 69 MB 592 MB

3094. 2019-07-05_22:03:31_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.7	6.7	1 ms	4.4	0.2	0.6	0.3	14.2
Simulation, STEP	0.3	1.6	6.8	0.6 ms	4.7	3.4	0.7	0.2	17.8
Simulation, STL	0.3	1.5	6.7	0.7 ms	4.3	0.4	0.6	0.2	14.0
Simulation, OBJ	0.2	1.5	6.6	0.6 ms	4.6	6.7	0.7	0.3	20.5
Visual, GLB	0.3	1.7	6.8	0.6 ms	9.9	93 ms	1.5	0.2	20.5
Visual, OBJ	0.4	1.8	7.5	0.8 ms	9.7	3.6	1.3	0.3	24.5

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-05_22:03:31_fpga_hat.kicad_pcb Folder timelapse Complexity 289 / 1000 (size 254, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 937, 48 Triangles, simulation 1,267,728 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 43 MB 505 MB STEP 212 MB 600 MB STL 63 MB 504 MB OBJ 132 MB 893 MB Visual GLB 24 MB 592 MB OBJ 73 MB 607 MB

3095. 2019-07-05_22:15:17_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.6	7.0	0.5 ms	4.7	0.2	0.7	0.3	14.8
Simulation, STEP	0.3	1.6	6.8	0.5 ms	4.9	3.6	0.7	0.3	18.0
Simulation, STL	0.3	1.6	6.3	0.6 ms	4.7	0.4	0.7	0.3	14.3
Simulation, OBJ	0.3	1.6	6.7	0.6 ms	4.8	6.4	0.6	0.2	20.6
Visual, GLB	0.3	1.6	6.8	0.4 ms	9.8	0.1	1.2	0.3	20.1
Visual, OBJ	0.3	1.7	6.8	0.5 ms	9.6	3.4	1.0	0.2	23.1

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-05_22:15:17_fpga_hat.kicad_pcb Folder timelapse Complexity 291 / 1000 (size 256, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 996, 57 Triangles, simulation 1,303,642 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 44 MB 555 MB STEP 216 MB 610 MB STL 65 MB 527 MB OBJ 135 MB 914 MB Visual GLB 25 MB 617 MB OBJ 76 MB 595 MB

3096. 2019-07-05_22:26:53_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.5	5.9	0.5 ms	4.1	0.2	0.6	0.2	12.8
Simulation, STEP	0.2	1.3	5.9	0.4 ms	4.1	3.1	0.6	0.2	15.5
Simulation, STL	0.2	1.4	6.1	0.4 ms	4.2	0.3	0.6	0.2	13.0
Simulation, OBJ	0.2	1.3	6.1	0.4 ms	4.1	5.3	0.6	0.2	17.8
Visual, GLB	0.2	1.3	5.9	0.7 ms	8.8	0.1	1.2	0.3	17.8
Visual, OBJ	0.2	1.4	5.9	0.7 ms	8.6	3.2	1.0	0.3	20.7

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-05_22:26:53_fpga_hat.kicad_pcb Folder timelapse Complexity 291 / 1000 (size 256, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,011, 58 Triangles, simulation 1,310,084 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 44 MB 555 MB STEP 217 MB 606 MB STL 66 MB 525 MB OBJ 136 MB 923 MB Visual GLB 25 MB 601 MB OBJ 76 MB 587 MB

3097. 2019-07-06_11:05:02_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	2.0	9.3	0.9 ms	7.1	0.3	1.1	0.3	20.5
Simulation, STEP	0.4	1.9	9.3	0.5 ms	7.2	5.3	1.0	0.3	25.4
Simulation, STL	0.4	1.9	9.4	0.8 ms	7.3	0.5	1.0	0.3	20.8
Simulation, OBJ	0.4	1.9	9.3	0.5 ms	7.5	10.0	1.1	0.2	30.5
Visual, GLB	0.4	1.9	9.0	0.8 ms	14.3	0.2	1.8	0.3	27.9
Visual, OBJ	0.5	2.0	9.2	0.5 ms	15.0	5.7	1.9	0.3	34.4

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-06_11:05:02_fpga_hat.kicad_pcb Folder timelapse Complexity 312 / 1000 (size 257, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,020, 89 Triangles, simulation 1,864,436 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 65 MB 673 MB STEP 308 MB 812 MB STL 93 MB 703 MB OBJ 196 MB 1.3 GB Visual GLB 38 MB 775 MB OBJ 115 MB 924 MB

3098. 2019-07-06_11:24:12_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.6	7.5	0.5 ms	6.4	0.3	0.9	0.2	17.3
Simulation, STEP	0.4	1.6	7.9	0.4 ms	6.5	4.4	0.9	0.3	22.0
Simulation, STL	0.3	1.6	7.6	0.4 ms	6.1	0.6	0.8	0.2	17.3
Simulation, OBJ	0.3	1.6	7.5	0.5 ms	6.2	8.0	0.8	0.2	24.7
Visual, GLB	0.3	1.6	7.8	0.4 ms	12.5	0.2	1.6	0.2	24.1
Visual, OBJ	0.3	1.6	7.8	0.5 ms	12.8	5.0	1.7	0.2	29.5

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-06_11:24:12_fpga_hat.kicad_pcb Folder timelapse Complexity 314 / 1000 (size 259, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,065, 110 Triangles, simulation 1,938,966 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 67 MB 739 MB STEP 317 MB 853 MB STL 97 MB 754 MB OBJ 204 MB 1.3 GB Visual GLB 40 MB 760 MB OBJ 121 MB 935 MB

3099. 2019-07-06_11:30:20_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	2.0	8.7	1 ms	7.5	0.3	1.1	0.3	20.3
Simulation, STEP	0.4	2.0	9.3	0.7 ms	7.5	5.6	1.0	0.3	26.1
Simulation, STL	0.4	2.0	9.9	0.5 ms	7.6	0.5	1.0	0.3	21.8
Simulation, OBJ	0.4	2.0	9.6	0.9 ms	7.5	10.6	1.0	0.2	31.3
Visual, GLB	0.4	2.1	9.6	0.9 ms	15.6	0.2	1.9	0.3	29.9
Visual, OBJ	0.5	2.0	9.5	0.6 ms	15.2	5.7	2.2	0.3	35.4

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-06_11:30:20_fpga_hat.kicad_pcb Folder timelapse Complexity 314 / 1000 (size 259, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,082, 113 Triangles, simulation 1,942,906 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 67 MB 716 MB STEP 317 MB 846 MB STL 97 MB 737 MB OBJ 205 MB 1.3 GB Visual GLB 40 MB 955 MB OBJ 121 MB 949 MB

3100. 2019-07-06_11:52:16_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.9	8.6	0.6 ms	7.9	0.3	0.9	0.2	20.2
Simulation, STEP	0.4	1.7	8.7	0.6 ms	6.8	5.3	0.9	0.2	24.0
Simulation, STL	0.4	1.9	8.9	0.6 ms	6.9	0.7	0.9	0.2	19.8
Simulation, OBJ	0.4	1.7	8.4	0.6 ms	6.7	10.2	0.9	0.2	28.5
Visual, GLB	0.4	1.8	8.4	0.6 ms	13.2	0.2	1.4	0.2	25.6
Visual, OBJ	0.4	1.8	8.9	0.8 ms	13.2	7.5	1.4	0.3	33.4

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-06_11:52:16_fpga_hat.kicad_pcb Folder timelapse Complexity 314 / 1000 (size 259, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,099, 117 Triangles, simulation 1,963,140 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 68 MB 733 MB STEP 320 MB 846 MB STL 98 MB 764 MB OBJ 207 MB 1.4 GB Visual GLB 41 MB 753 MB OBJ 123 MB 949 MB

3101. 2019-07-06_12:26:53_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.8	8.3	0.6 ms	6.7	0.3	0.9	0.2	18.6
Simulation, STEP	0.4	1.8	8.4	0.6 ms	6.8	5.3	1.0	0.2	23.9
Simulation, STL	0.4	1.8	8.4	0.6 ms	7.0	0.5	1.0	0.3	19.3
Simulation, OBJ	0.3	1.9	8.4	0.8 ms	6.8	9.6	1.1	0.2	28.4
Visual, GLB	0.4	1.9	8.3	0.9 ms	13.6	0.2	1.7	0.2	26.4
Visual, OBJ	0.4	1.8	8.6	0.8 ms	13.9	5.6	1.7	0.2	32.2

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-06_12:26:53_fpga_hat.kicad_pcb Folder timelapse Complexity 314 / 1000 (size 259, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,098, 119 Triangles, simulation 1,966,700 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 68 MB 699 MB STEP 320 MB 816 MB STL 98 MB 721 MB OBJ 207 MB 1.3 GB Visual GLB 41 MB 793 MB OBJ 122 MB 928 MB

3102. 2019-07-06_12:29:23_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.7	7.9	0.6 ms	6.3	0.3	0.9	0.3	17.7
Simulation, STEP	0.3	1.6	7.6	0.9 ms	6.1	4.4	0.8	0.2	21.1
Simulation, STL	0.3	1.8	7.6	0.6 ms	6.0	0.4	0.8	0.2	17.1
Simulation, OBJ	0.3	1.5	7.3	0.5 ms	6.1	8.0	0.8	0.2	24.2
Visual, GLB	0.3	1.7	7.3	0.8 ms	12.3	0.2	1.3	0.2	23.3
Visual, OBJ	0.4	1.6	7.5	0.8 ms	12.4	5.0	1.6	0.3	28.7

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-06_12:29:23_fpga_hat.kicad_pcb Folder timelapse Complexity 314 / 1000 (size 259, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,098, 122 Triangles, simulation 1,968,922 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 68 MB 704 MB STEP 320 MB 848 MB STL 98 MB 713 MB OBJ 208 MB 1.3 GB Visual GLB 41 MB 857 MB OBJ 123 MB 877 MB

3103. 2019-07-06_12:41:44_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	2.0	8.7	0.7 ms	6.1	0.3	0.9	0.3	18.6
Simulation, STEP	0.3	2.2	9.0	0.8 ms	6.3	4.6	0.8	0.3	23.5
Simulation, STL	0.4	2.1	8.9	0.8 ms	6.6	0.5	0.9	0.3	19.5
Simulation, OBJ	0.4	2.1	9.1	0.9 ms	6.3	10.2	0.9	0.3	29.2
Visual, GLB	0.3	2.1	9.1	0.8 ms	12.8	0.2	1.2	0.3	26.0
Visual, OBJ	0.3	2.2	8.8	1.0 ms	13.0	6.0	1.4	0.3	32.0

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-06_12:41:44_fpga_hat.kicad_pcb Folder timelapse Complexity 294 / 1000 (size 259, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,098, 122 Triangles, simulation 1,596,396 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 55 MB 617 MB STEP 255 MB 681 MB STL 80 MB 647 MB OBJ 167 MB 1.1 GB Visual GLB 32 MB 721 MB OBJ 98 MB 721 MB

3104. 2019-07-06_12:52:32_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	2.0	8.4	0.8 ms	6.6	0.3	0.8	0.3	18.7
Simulation, STEP	0.3	1.9	8.0	0.9 ms	6.3	4.2	0.8	0.3	21.9
Simulation, STL	0.3	1.8	8.2	0.8 ms	6.2	0.5	0.8	0.2	18.1
Simulation, OBJ	0.3	1.9	8.3	1.0 ms	6.1	8.2	0.9	0.3	26.0
Visual, GLB	0.3	1.9	8.2	0.8 ms	12.9	0.1	1.8	0.3	25.5
Visual, OBJ	0.3	1.8	8.2	0.9 ms	13.1	4.6	1.6	0.2	29.8

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-06_12:52:32_fpga_hat.kicad_pcb Folder timelapse Complexity 294 / 1000 (size 259, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,098, 122 Triangles, simulation 1,583,024 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 55 MB 624 MB STEP 252 MB 670 MB STL 79 MB 633 MB OBJ 165 MB 1.0 GB Visual GLB 32 MB 729 MB OBJ 96 MB 729 MB

3105. 2019-07-06_12:56:05_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.7	7.5	0.7 ms	5.9	0.2	0.7	0.2	16.6
Simulation, STEP	0.3	1.7	8.0	0.8 ms	6.0	3.9	0.8	0.2	20.9
Simulation, STL	0.3	1.8	7.9	1.0 ms	5.8	0.5	0.8	0.3	17.3
Simulation, OBJ	0.3	2.0	8.1	1.0 ms	6.0	8.1	0.8	0.2	25.6
Visual, GLB	0.3	1.8	7.5	0.7 ms	11.8	0.1	1.4	0.2	23.2
Visual, OBJ	0.3	1.7	7.4	0.7 ms	12.0	5.2	1.3	0.2	28.2

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-06_12:56:05_fpga_hat.kicad_pcb Folder timelapse Complexity 294 / 1000 (size 259, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,098, 122 Triangles, simulation 1,577,382 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 55 MB 551 MB STEP 250 MB 672 MB STL 79 MB 567 MB OBJ 165 MB 1.1 GB Visual GLB 32 MB 676 MB OBJ 96 MB 728 MB

3106. 2019-07-06_13:01:21_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.6	7.0	0.7 ms	5.2	0.2	0.6	0.3	15.2
Simulation, STEP	0.2	1.6	6.7	0.8 ms	5.1	3.7	0.7	0.2	18.3
Simulation, STL	0.2	1.5	6.5	0.7 ms	5.0	0.5	0.7	0.3	14.7
Simulation, OBJ	0.3	1.6	6.6	0.8 ms	5.1	7.2	0.6	0.3	21.7
Visual, GLB	0.2	1.8	6.9	0.7 ms	10.4	0.1	1.1	0.3	20.8
Visual, OBJ	0.2	1.7	6.5	0.7 ms	10.7	3.9	1.5	0.2	24.7

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-06_13:01:21_fpga_hat.kicad_pcb Folder timelapse Complexity 294 / 1000 (size 259, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,098, 122 Triangles, simulation 1,545,620 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 53 MB 644 MB STEP 240 MB 681 MB STL 77 MB 617 MB OBJ 161 MB 1.1 GB Visual GLB 31 MB 698 MB OBJ 93 MB 683 MB

3107. 2019-07-06_13:25:29_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.9	8.8	1 ms	7.1	0.3	0.9	0.3	19.6
Simulation, STEP	0.4	1.9	8.7	1 ms	6.8	5.4	1.0	0.3	24.5
Simulation, STL	0.4	1.8	8.0	1 ms	7.1	0.5	1.0	0.2	19.0
Simulation, OBJ	0.4	1.8	8.1	0.6 ms	7.1	9.6	1.1	0.2	28.3
Visual, GLB	0.4	1.9	8.2	0.9 ms	14.7	0.2	1.8	0.3	27.6
Visual, OBJ	0.4	2.0	8.6	0.7 ms	14.9	5.9	2.1	0.2	34.2

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-06_13:25:29_fpga_hat.kicad_pcb Folder timelapse Complexity 314 / 1000 (size 259, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,098, 122 Triangles, simulation 1,959,772 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 68 MB 745 MB STEP 315 MB 842 MB STL 98 MB 715 MB OBJ 207 MB 1.4 GB Visual GLB 41 MB 809 MB OBJ 123 MB 932 MB

3108. 2019-07-06_13:40:41_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	2.2	9.8	0.9 ms	7.8	0.3	1.2	0.3	22.1
Simulation, STEP	0.5	2.2	9.8	0.5 ms	7.8	6.0	1.2	0.3	27.7
Simulation, STL	0.5	2.1	9.8	0.7 ms	7.7	0.8	1.1	0.2	22.3
Simulation, OBJ	0.5	2.1	9.8	1.0 ms	7.8	11.7	1.1	0.3	33.4
Visual, GLB	0.4	2.1	9.6	1.0 ms	14.9	0.2	1.6	0.2	29.0
Visual, OBJ	0.5	2.1	9.8	1 ms	15.3	6.9	1.8	0.3	36.7

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-06_13:40:41_fpga_hat.kicad_pcb Folder timelapse Complexity 314 / 1000 (size 259, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,098, 122 Triangles, simulation 1,951,140 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 68 MB 757 MB STEP 312 MB 842 MB STL 98 MB 729 MB OBJ 206 MB 1.3 GB Visual GLB 41 MB 907 MB OBJ 122 MB 929 MB

3109. 2019-07-06_13:40:48_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	2.3	10.7	0.8 ms	8.8	0.5	1.2	0.3	24.3
Simulation, STEP	0.5	2.4	10.6	1 ms	8.4	6.4	1.3	0.3	29.9
Simulation, STL	0.5	2.4	11.0	1 ms	8.6	0.8	1.3	0.3	24.9
Simulation, OBJ	0.6	2.3	10.5	2 ms	8.4	12.4	1.3	0.3	35.8
Visual, GLB	0.6	2.4	10.5	0.8 ms	17.4	0.2	1.7	0.3	33.1
Visual, OBJ	0.5	2.3	10.4	0.8 ms	15.7	7.3	1.7	0.3	38.1

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-06_13:40:48_fpga_hat.kicad_pcb Folder timelapse Complexity 314 / 1000 (size 259, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 10th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,098, 122 Triangles, simulation 1,951,140 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 68 MB 737 MB STEP 312 MB 841 MB STL 98 MB 723 MB OBJ 206 MB 1.3 GB Visual GLB 41 MB 770 MB OBJ 122 MB 861 MB

3110. 2019-07-07_12:53:39_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	2.0	7.4	0.9 ms	5.5	0.2	0.8	0.3	16.5
Simulation, STEP	0.3	1.9	7.6	1 ms	5.7	4.2	0.8	0.3	20.8
Simulation, STL	0.3	1.9	7.5	0.9 ms	5.7	0.7	0.8	0.3	17.1
Simulation, OBJ	0.3	2.0	7.5	0.9 ms	5.6	7.7	0.7	0.3	24.1
Visual, GLB	0.3	1.9	7.3	1 ms	12.7	0.1	1.6	0.2	24.2
Visual, OBJ	0.3	1.9	7.7	1 ms	12.9	4.4	1.6	0.3	29.1

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-07_12:53:39_fpga_hat.kicad_pcb Folder timelapse Complexity 294 / 1000 (size 259, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,101, 122 Triangles, simulation 1,560,228 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 54 MB 643 MB STEP 243 MB 656 MB STL 78 MB 596 MB OBJ 163 MB 1.1 GB Visual GLB 32 MB 667 MB OBJ 95 MB 713 MB

3111. 2019-07-07_13:11:04_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.8	8.1	1 ms	5.9	0.3	0.9	0.3	17.7
Simulation, STEP	0.3	2.1	8.7	0.7 ms	5.8	4.5	0.9	0.3	22.6
Simulation, STL	0.4	1.9	9.0	1.0 ms	6.6	0.4	0.8	0.3	19.4
Simulation, OBJ	0.3	1.9	8.1	1 ms	6.2	9.0	0.8	0.3	26.6
Visual, GLB	0.3	2.0	8.0	0.9 ms	12.4	0.1	1.2	0.2	24.2
Visual, OBJ	0.3	1.9	8.2	0.7 ms	12.5	5.1	1.4	0.2	29.7

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-07_13:11:04_fpga_hat.kicad_pcb Folder timelapse Complexity 294 / 1000 (size 259, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,101, 122 Triangles, simulation 1,573,622 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 54 MB 601 MB STEP 246 MB 680 MB STL 79 MB 620 MB OBJ 164 MB 1.1 GB Visual GLB 32 MB 700 MB OBJ 97 MB 780 MB

3112. 2019-07-07_13:19:32_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	2.0	9.2	0.9 ms	7.4	0.3	1.1	0.3	20.8
Simulation, STEP	0.4	2.2	9.6	0.8 ms	7.6	5.4	1.0	0.3	26.6
Simulation, STL	0.4	2.1	9.2	0.9 ms	7.5	0.6	1.0	0.3	21.2
Simulation, OBJ	0.4	2.2	9.5	0.9 ms	7.5	10.7	1.2	0.3	31.8
Visual, GLB	0.5	2.2	9.3	0.8 ms	16.0	0.2	1.7	0.3	30.1
Visual, OBJ	0.4	2.0	9.1	0.8 ms	16.5	6.4	2.2	0.2	36.9

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-07_13:19:32_fpga_hat.kicad_pcb Folder timelapse Complexity 314 / 1000 (size 259, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,098, 122 Triangles, simulation 1,972,848 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 69 MB 693 MB STEP 317 MB 851 MB STL 99 MB 732 MB OBJ 208 MB 1.3 GB Visual GLB 42 MB 904 MB OBJ 126 MB 937 MB

3113. 2019-07-07_13:36:48_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.7	8.0	0.7 ms	6.8	0.3	0.9	0.2	18.3
Simulation, STEP	0.4	1.8	8.3	0.7 ms	6.5	5.0	0.9	0.2	23.3
Simulation, STL	0.4	1.8	7.7	0.8 ms	6.6	0.6	0.8	0.3	18.2
Simulation, OBJ	0.4	1.7	7.8	0.7 ms	6.7	9.2	0.9	0.3	26.9
Visual, GLB	0.4	1.7	7.8	0.8 ms	13.9	0.2	1.5	0.2	25.7
Visual, OBJ	0.3	1.7	7.5	0.6 ms	14.1	5.9	1.8	0.2	31.5

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-07_13:36:48_fpga_hat.kicad_pcb Folder timelapse Complexity 314 / 1000 (size 259, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,081, 122 Triangles, simulation 1,969,958 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 69 MB 738 MB STEP 316 MB 851 MB STL 99 MB 731 MB OBJ 208 MB 1.3 GB Visual GLB 42 MB 893 MB OBJ 125 MB 975 MB

3114. 2019-07-07_17:06:09_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.7	8.0	1.0 ms	6.4	0.3	1.0	0.3	18.2
Simulation, STEP	0.3	1.7	8.1	0.5 ms	6.7	4.7	0.9	0.2	22.7
Simulation, STL	0.5	1.8	8.6	0.5 ms	6.8	0.7	1.0	0.3	19.6
Simulation, OBJ	0.4	1.9	8.0	0.5 ms	6.5	8.6	1.0	0.3	26.6
Visual, GLB	0.4	1.9	8.3	0.4 ms	13.1	0.2	1.4	0.2	25.5
Visual, OBJ	0.4	1.8	8.0	0.4 ms	13.3	5.1	1.4	0.2	30.2

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-07_17:06:09_fpga_hat.kicad_pcb Folder timelapse Complexity 315 / 1000 (size 260, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,080, 157 Triangles, simulation 2,050,632 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 71 MB 768 MB STEP 319 MB 875 MB STL 103 MB 772 MB OBJ 216 MB 1.4 GB Visual GLB 43 MB 774 MB OBJ 129 MB 945 MB

3115. 2019-07-07_17:15:58_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	2.2	9.5	0.7 ms	7.5	0.3	1.2	0.3	21.4
Simulation, STEP	0.4	2.0	9.5	0.5 ms	7.6	5.8	1.1	0.3	26.7
Simulation, STL	0.4	2.1	8.8	0.6 ms	7.5	0.6	1.2	0.2	20.8
Simulation, OBJ	0.5	2.1	9.3	0.4 ms	7.4	10.0	1.1	0.3	30.7
Visual, GLB	0.4	2.0	9.2	1 ms	15.8	0.2	1.8	0.2	29.7
Visual, OBJ	0.4	2.2	9.8	0.5 ms	15.6	6.2	2.1	0.3	36.6

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-07_17:15:58_fpga_hat.kicad_pcb Folder timelapse Complexity 316 / 1000 (size 261, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,080, 164 Triangles, simulation 2,064,160 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 72 MB 786 MB STEP 319 MB 897 MB STL 103 MB 767 MB OBJ 218 MB 1.4 GB Visual GLB 43 MB 861 MB OBJ 130 MB 963 MB

3116. 2019-07-07_18:08:38_fpga_hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	2.0	9.3	0.4 ms	7.1	0.4	1.0	0.2	20.4
Simulation, STEP	0.5	2.0	8.8	0.7 ms	7.4	5.6	1.1	0.2	25.6
Simulation, STL	0.4	2.0	9.0	0.5 ms	7.3	0.5	0.9	0.2	20.4
Simulation, OBJ	0.4	2.0	9.2	0.4 ms	7.2	10.6	1.0	0.2	30.6
Visual, GLB	0.4	2.1	9.5	0.6 ms	13.9	0.2	1.4	0.2	27.8
Visual, OBJ	0.4	1.9	8.9	0.4 ms	14.4	6.6	1.6	0.3	34.2

Board Repo: Wren6991/Snowflake-FPGA Board: 2019-07-07_18:08:38_fpga_hat.kicad_pcb Folder timelapse Complexity 316 / 1000 (size 261, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,080, 164 Triangles, simulation 2,069,672 in 150 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 72 MB 811 MB STEP 320 MB 860 MB STL 103 MB 778 MB OBJ 219 MB 1.4 GB Visual GLB 43 MB 788 MB OBJ 131 MB 952 MB

3117. CAT

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	2.6	12.0	2 ms	10.2	0.5	1.4	0.3	27.7
Simulation, STEP	0.7	2.6	12.1	0.9 ms	10.0	7.2	1.5	0.2	34.3
Simulation, STL	0.7	2.7	12.4	0.9 ms	10.4	1.1	1.6	0.3	29.2
Simulation, OBJ	0.7	2.8	12.3	1 ms	10.3	16.6	1.6	0.2	44.4
Visual, GLB	0.7	2.7	12.1	1 ms	21.3	0.3	2.3	0.3	39.6
Visual, OBJ	0.7	2.8	12.8	2 ms	21.7	9.9	2.9	0.2	51.0

Board Repo: xesscorp/CAT-Board Board: CAT.kicad_pcb Folder pcb Complexity 319 / 1000 (size 264, features 55) KESE features through vias, drill offsets, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 107, 1,919, 174 Triangles, simulation 2,714,340 in 182 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 94 MB 908 MB STEP 426 MB 998 MB STL 136 MB 893 MB OBJ 288 MB 1.8 GB Visual GLB 59 MB 1.1 GB OBJ 181 MB 1.3 GB

3118. hw-openmower-sabo

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	3.4	13.2	50.2	3 ms	53.2	2.8	7.4	0.7	131.0
Simulation, STEP	3.7	13.0	50.0	2 ms	48.3	27.4	7.2	0.5	150.1
Simulation, STL	3.7	12.8	48.9	3 ms	47.3	5.4	8.1	0.5	126.7
Simulation, OBJ	3.7	13.3	52.9	3 ms	53.4	86.0	6.8	0.5	216.6
Visual, GLB	3.6	13.5	49.5	2 ms	112.5	0.9	10.1	0.4	190.3
Visual, OBJ	3.7	13.1	48.6	4 ms	106.9	31.9	10.2	0.4	214.7

Board Repo: xtech/hw-openmower-sabo Board: hw-openmower-sabo.kicad_pcb Complexity 419 / 1000 (size 249, features 170) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, drill offsets, filled zones, copper drawings, knockout text, TrueType text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 6 File format KiCad 10 (20260206) Parts, tracks, vias 324, 2,730, 1,177 Triangles, simulation 11,081,862 in 442 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 368 MB 3.1 GB STEP 1.4 GB 3.8 GB STL 554 MB 3.1 GB OBJ 1.2 GB 6.9 GB Visual GLB 179 MB 3.1 GB OBJ 582 MB 3.8 GB

3119. hw-openmower-universal

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.8	9.9	37.0	1 ms	29.8	1.7	4.4	0.4	85.9
Simulation, STEP	2.7	9.3	36.0	1 ms	29.1	18.6	4.2	0.3	100.3
Simulation, STL	2.7	9.5	38.4	1 ms	29.6	3.4	5.1	0.4	89.1
Simulation, OBJ	2.5	9.5	36.6	2 ms	29.3	53.9	4.6	0.4	136.8
Visual, GLB	2.7	10.1	37.2	2 ms	70.2	0.7	7.9	0.3	129.1
Visual, OBJ	2.7	9.7	36.6	1 ms	68.3	24.2	8.2	0.3	149.9

Board Repo: xtech/hw-openmower-universal Board: hw-openmower-universal.kicad_pcb Complexity 358 / 1000 (size 238, features 120) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, drill offsets, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 382, 2,241, 928 Triangles, simulation 8,494,312 in 357 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 286 MB 2.3 GB STEP 993 MB 3.0 GB STL 425 MB 2.4 GB OBJ 899 MB 5.4 GB Visual GLB 149 MB 2.6 GB OBJ 479 MB 3.1 GB

3120. hw-openmower-yardforce

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.8	5.3	21.8	1 ms	20.0	0.9	2.8	0.3	52.9
Simulation, STEP	1.8	5.1	22.0	1 ms	21.1	13.3	2.9	0.4	66.5
Simulation, STL	1.8	5.2	21.5	2 ms	20.3	2.0	3.0	0.4	54.3
Simulation, OBJ	1.7	5.4	21.9	1 ms	21.3	28.3	2.9	0.4	81.9
Visual, GLB	2.0	5.4	21.9	3 ms	47.3	0.5	6.7	0.3	84.0
Visual, OBJ	1.8	5.0	22.1	1 ms	47.4	15.9	6.9	0.3	99.4

Board Repo: xtech/hw-openmower-yardforce Board: hw-openmower-yardforce.kicad_pcb Complexity 356 / 1000 (size 231, features 125) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, drill offsets, filled zones, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 253, 2,513, 641 Triangles, simulation 6,269,352 in 356 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 213 MB 1.8 GB STEP 804 MB 2.3 GB STL 313 MB 1.8 GB OBJ 667 MB 4.0 GB Visual GLB 119 MB 2.1 GB OBJ 381 MB 2.6 GB

3121. Prism

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.2	6.1	21.0	1 ms	22.9	1.2	3.3	0.3	57.1
Simulation, STEP	2.4	6.6	21.1	0.9 ms	22.4	13.0	3.1	0.4	69.0
Simulation, STL	2.2	6.4	21.5	1 ms	22.5	2.8	3.3	0.4	59.1
Simulation, OBJ	2.3	6.6	21.1	1.0 ms	22.2	31.0	2.8	0.4	86.4
Visual, GLB	2.1	6.1	20.9	1 ms	52.7	0.5	6.2	0.3	88.7
Visual, OBJ	2.1	6.3	20.2	1 ms	51.9	16.6	6.3	0.3	103.7

Board Repo: y10-labs/prism-pcb Board: Prism.kicad_pcb Complexity 422 / 1000 (size 322, features 100) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 8 File format KiCad 8 (20240108) Parts, tracks, vias 229, 8,893, 833 Triangles, simulation 6,877,892 in 355 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 226 MB 1.6 GB STEP 992 MB 2.2 GB STL 344 MB 1.6 GB OBJ 753 MB 4.4 GB Visual GLB 127 MB 2.2 GB OBJ 426 MB 2.8 GB

3122. 2063-Z80

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.2	6.7	29.5	1 ms	23.0	1.2	3.5	0.3	65.6
Simulation, STEP	1.2	6.4	28.4	0.7 ms	22.5	15.5	3.3	0.3	77.7
Simulation, STL	1.3	6.7	29.0	0.9 ms	23.6	2.7	3.4	0.3	67.0
Simulation, OBJ	1.3	6.9	29.6	0.8 ms	24.5	43.4	3.6	0.3	109.6
Visual, GLB	1.2	6.7	28.7	1 ms	49.6	0.5	5.3	0.3	92.5
Visual, OBJ	1.2	6.7	29.6	0.7 ms	50.5	21.1	4.9	0.3	114.2

Board Repo: Z80-Retro/2063-Z80 Board: 2063-Z80.kicad_pcb Complexity 286 / 1000 (size 211, features 75) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, drill offsets, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 80, 1,997, 244 Triangles, simulation 6,315,170 in 166 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 216 MB 1.6 GB STEP 878 MB 2.0 GB STL 316 MB 1.6 GB OBJ 677 MB 4.1 GB Visual GLB 117 MB 1.9 GB OBJ 373 MB 2.4 GB

3123. pcb

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.4	6.3	16.7	1 ms	25.5	1.1	3.0	0.4	54.4
Simulation, STEP	1.3	6.4	18.2	3 ms	27.0	15.6	3.2	0.4	72.0
Simulation, STL	1.3	6.2	16.7	1 ms	25.8	2.3	3.6	0.3	56.2
Simulation, OBJ	1.3	6.2	17.8	2 ms	26.8	40.7	3.3	0.3	96.4
Visual, GLB	1.3	6.7	17.2	2 ms	53.8	0.8	6.8	0.3	86.8
Visual, OBJ	1.4	6.2	16.5	2 ms	54.2	23.2	7.2	0.3	109.0

Board Repo: zephray/Fobu Board: pcb.kicad_pcb Folder hardware / pcb Complexity 465 / 1000 (size 325, features 140) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 6 File format KiCad 6 (20211014) Parts, tracks, vias 255, 6,378, 920 Triangles, simulation 7,037,632 in 519 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 236 MB 1.8 GB STEP 827 MB 2.4 GB STL 352 MB 1.8 GB OBJ 754 MB 4.5 GB Visual GLB 136 MB 2.3 GB OBJ 456 MB 2.9 GB

3124. adapter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.5	0.2 ms	1.1	40 ms	0.1	0.2	2.3
Simulation, STEP	0.2	0.2	0.5	0.2 ms	1.1	1.2	0.1	0.3	3.6
Simulation, STL	0.1	0.2	0.6	0.3 ms	1.1	57 ms	0.1	0.2	2.3
Simulation, OBJ	0.1	0.2	0.6	0.2 ms	1.1	0.9	0.1	0.2	3.2
Visual, GLB	0.1	0.2	0.5	0.2 ms	1.8	24 ms	0.1	0.2	3.0
Visual, OBJ	0.1	0.2	0.5	0.2 ms	1.8	0.7	0.1	0.2	3.7

Board Repo: zephray/nekoink Board: adapter.kicad_pcb Folder pcb / 34p-a-adapter Complexity 211 / 1000 (size 136, features 75) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 6 (20211014) Parts, tracks, vias 9, 186, 43 Triangles, simulation 151,366 in 49 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 5.3 MB 212 MB STEP 27 MB 226 MB STL 7.6 MB 213 MB OBJ 15 MB 211 MB Visual GLB 4.4 MB 198 MB OBJ 12 MB 195 MB

3125. pcb

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.3	5.2	15.1	2 ms	19.8	0.6	2.4	0.3	44.7
Simulation, STEP	1.3	5.4	14.8	0.9 ms	20.1	12.4	2.3	0.4	56.6
Simulation, STL	1.4	5.1	14.8	2 ms	19.4	1.5	2.6	0.3	45.2
Simulation, OBJ	1.3	5.4	15.6	2 ms	20.6	23.8	2.5	0.4	69.6
Visual, GLB	1.3	5.3	15.7	2 ms	41.3	0.5	5.5	0.3	69.8
Visual, OBJ	1.3	5.2	15.8	2 ms	40.4	15.3	5.9	0.3	84.2

Board Repo: zephray/nekoink Board: pcb.kicad_pcb Folder pcb / mainboard_gen1 Complexity 441 / 1000 (size 301, features 140) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 6 (20211014) Parts, tracks, vias 231, 6,227, 606 Triangles, simulation 4,542,078 in 352 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 154 MB 1.4 GB STEP 721 MB 1.8 GB STL 227 MB 1.4 GB OBJ 482 MB 2.9 GB Visual GLB 100 MB 1.7 GB OBJ 318 MB 2.1 GB

3126. pcb

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	5.1	19.0	1 ms	19.0	0.8	1.8	0.3	46.7
Simulation, STEP	0.9	5.1	18.1	1 ms	18.9	10.7	1.8	0.3	55.7
Simulation, STL	0.9	5.0	18.7	2 ms	19.8	1.7	1.8	0.3	48.2
Simulation, OBJ	0.9	5.4	19.7	1 ms	19.7	25.7	1.9	0.3	73.5
Visual, GLB	0.9	5.0	19.6	1 ms	38.6	0.4	4.0	0.3	68.8
Visual, OBJ	1.0	5.4	18.8	1 ms	37.7	14.1	4.5	0.3	81.9

Board Repo: zephray/nekoink Board: pcb.kicad_pcb Folder pcb / mainboard_gen2 Complexity 398 / 1000 (size 308, features 90) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, copper drawings, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 6 File format KiCad 7 (20221018) Parts, tracks, vias 241, 4,190, 464 Triangles, simulation 4,419,766 in 427 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 150 MB 1.2 GB STEP 623 MB 1.5 GB STL 221 MB 1.2 GB OBJ 469 MB 2.8 GB Visual GLB 83 MB 1.7 GB OBJ 266 MB 1.9 GB

3127. 18650_pcb

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.4	0.8	0.1 ms	0.8	29 ms	60 ms	0.3	2.5
Simulation, STEP	0.2	0.4	0.7	0.1 ms	0.8	1.5	74 ms	0.2	3.8
Simulation, STL	0.2	0.4	0.7	0.1 ms	0.8	43 ms	65 ms	0.3	2.4
Simulation, OBJ	0.2	0.4	0.8	0.2 ms	0.8	0.8	94 ms	0.2	3.2
Visual, GLB	0.2	0.3	0.8	0.1 ms	1.7	25 ms	0.2	0.3	3.4
Visual, OBJ	0.2	0.4	0.7	0.1 ms	1.7	0.8	0.2	0.3	4.2

Board Repo: ZeroPhone/ZeroPhone-PCBs Board: 18650_pcb.kicad_pcb Folder 18650_pcb Complexity 118 / 1000 (size 88, features 30) KESE features filled zones, curved board outline Tested 10th November 2026 Copper layers 2 File format KiCad 4 (4) Parts, tracks, vias 4, 26, 0 Triangles, simulation 141,022 in 14 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 5.3 MB 211 MB STEP 26 MB 224 MB STL 7.1 MB 212 MB OBJ 15 MB 211 MB Visual GLB 4.6 MB 183 MB OBJ 13 MB 181 MB

3128. 6p_separator

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	3 ms	17 ms	50 ms	0.1 ms	0.1	4 ms	13 ms	0.2	0.4
Simulation, STEP	5 ms	26 ms	37 ms	0.1 ms	0.1	0.2	13 ms	0.2	0.6
Simulation, STL	3 ms	24 ms	49 ms	0.1 ms	0.1	6 ms	12 ms	0.2	0.4
Simulation, OBJ	4 ms	26 ms	40 ms	0.1 ms	0.1	91 ms	13 ms	0.2	0.5
Visual, GLB	3 ms	23 ms	47 ms	0.1 ms	0.2	3 ms	38 ms	0.2	0.5
Visual, OBJ	3 ms	28 ms	46 ms	0.1 ms	0.2	54 ms	39 ms	0.2	0.6

Board Repo: ZeroPhone/ZeroPhone-PCBs Board: 6p_separator.kicad_pcb Folder 6p_separator Complexity 24 / 1000 (size 24, features 0) Tested 9th November 2026 Copper layers 2 File format KiCad 4 (4) Parts, tracks, vias 1, 0, 0 Triangles, simulation 18,436 in 9 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 598 kB 41 MB STEP 2.3 MB 43 MB STL 923 kB 41 MB OBJ 1.7 MB 44 MB Visual GLB 410 kB 69 MB OBJ 1.1 MB 58 MB

3129. back_pcb

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.5	7.3	0.3 ms	6.9	0.3	0.8	0.2	17.3
Simulation, STEP	0.4	1.6	7.1	0.5 ms	6.4	4.2	0.8	0.3	20.9
Simulation, STL	0.4	1.6	7.7	0.4 ms	6.6	0.5	0.8	0.3	17.8
Simulation, OBJ	0.5	1.4	7.6	0.4 ms	6.9	7.5	0.8	0.2	24.8
Visual, GLB	0.4	1.6	7.5	0.3 ms	16.3	0.2	1.8	0.2	28.1
Visual, OBJ	0.3	1.3	7.4	0.4 ms	16.9	5.7	2.0	0.3	33.9

Board Repo: ZeroPhone/ZeroPhone-PCBs Board: back_pcb.kicad_pcb Folder back_pcb Complexity 248 / 1000 (size 193, features 55) KESE features through vias, drill offsets, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 4 (4) Parts, tracks, vias 94, 1,491, 252 Triangles, simulation 1,666,214 in 94 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 59 MB 724 MB STEP 309 MB 758 MB STL 83 MB 724 MB OBJ 176 MB 1.2 GB Visual GLB 46 MB 820 MB OBJ 139 MB 984 MB

3130. front_prototype

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.8	11.7	0.9 ms	11.9	0.4	1.3	0.3	27.8
Simulation, STEP	0.4	1.7	11.8	0.8 ms	12.3	5.5	1.3	0.2	33.2
Simulation, STL	0.4	1.7	11.8	0.7 ms	12.1	0.8	1.4	0.3	28.4
Simulation, OBJ	0.4	1.7	11.8	0.7 ms	12.5	11.6	1.3	0.3	39.5
Visual, GLB	0.4	1.7	11.8	0.7 ms	23.9	0.2	2.4	0.3	40.6
Visual, OBJ	0.4	1.7	12.1	0.7 ms	24.2	8.1	2.5	0.3	49.3

Board Repo: ZeroPhone/ZeroPhone-PCBs Board: front_prototype.kicad_pcb Folder front_pcb Complexity 289 / 1000 (size 234, features 55) KESE features through vias, drill offsets, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 4 (4) Parts, tracks, vias 82, 1,522, 402 Triangles, simulation 2,078,644 in 97 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 75 MB 753 MB STEP 401 MB 905 MB STL 104 MB 795 MB OBJ 226 MB 1.5 GB Visual GLB 53 MB 999 MB OBJ 162 MB 1.1 GB

3131. keypad_pcb

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.7	2.5	0.3 ms	1.7	97 ms	0.3	0.2	5.7
Simulation, STEP	0.3	0.8	2.8	0.2 ms	1.7	1.8	0.3	0.3	7.9
Simulation, STL	0.3	0.8	2.4	0.2 ms	1.8	0.2	0.3	0.3	6.1
Simulation, OBJ	0.2	0.7	2.7	0.4 ms	1.7	3.2	0.3	0.3	9.2
Visual, GLB	0.3	0.8	2.7	0.2 ms	5.1	96 ms	0.7	0.3	10.0
Visual, OBJ	0.2	0.7	2.4	0.5 ms	5.0	2.8	0.8	0.2	12.2

Board Repo: ZeroPhone/ZeroPhone-PCBs Board: keypad_pcb.kicad_pcb Folder keypad_pcb Complexity 189 / 1000 (size 164, features 25) KESE features through vias, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 4 (4) Parts, tracks, vias 31, 472, 104 Triangles, simulation 514,642 in 30 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 18 MB 330 MB STEP 87 MB 353 MB STL 26 MB 348 MB OBJ 54 MB 397 MB Visual GLB 16 MB 393 MB OBJ 47 MB 400 MB

3132. speaker_adapter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	83 ms	33 ms	0.1	0.1 ms	0.2	5 ms	20 ms	0.2	0.7
Simulation, STEP	77 ms	34 ms	0.1	0.1 ms	0.2	0.2	26 ms	0.2	0.9
Simulation, STL	76 ms	36 ms	0.1	0.1 ms	0.2	6 ms	25 ms	0.2	0.7
Simulation, OBJ	76 ms	35 ms	0.1	0.1 ms	0.2	90 ms	27 ms	0.3	0.8
Visual, GLB	75 ms	34 ms	0.1	0.1 ms	0.3	4 ms	34 ms	0.3	0.9
Visual, OBJ	74 ms	36 ms	0.1	0.1 ms	0.3	79 ms	32 ms	0.2	0.9

Board Repo: ZeroPhone/ZeroPhone-PCBs Board: speaker_adapter.kicad_pcb Folder speaker_adapter Complexity 98 / 1000 (size 63, features 35) KESE features through vias, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 4 (4) Parts, tracks, vias 0, 10, 2 Triangles, simulation 15,552 in 13 parts Note no components Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 573 kB 61 MB STEP 2.5 MB 65 MB STL 779 kB 62 MB OBJ 1.5 MB 64 MB Visual GLB 425 kB 76 MB OBJ 1.1 MB 81 MB

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