Corpus Testing 28

Corpus Page 28

Part 28 of 29 of Corpus Testing: boards 2,917 to 3,024, six runs each, one file format a run, as Corpus Testing describes.

2917. SystemBoardPLCC

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.3	6.6	0.7 ms	5.2	0.2	0.8	0.2	14.5
Simulation, STEP	0.3	1.2	6.5	0.6 ms	5.2	4.4	0.9	0.2	18.9
Simulation, STL	0.3	1.2	6.9	0.6 ms	5.4	0.4	0.8	0.2	15.2
Simulation, OBJ	0.3	1.3	6.5	0.6 ms	5.3	8.7	0.7	0.2	23.1
Visual, GLB	0.3	1.3	6.5	0.5 ms	10.9	0.2	1.1	0.2	20.5
Visual, OBJ	0.3	1.2	6.5	0.6 ms	10.6	5.4	1.4	0.2	25.7

Board Repo: transistorfet/retroverse Board: SystemBoardPLCC.kicad_pcb Folder components / systemboard / hardware / SystemBoardPLCC Complexity 308 / 1000 (size 208, features 100) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 33, 568, 138 Triangles, simulation 1,694,846 in 126 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 57 MB 770 MB STEP 239 MB 787 MB STL 85 MB 783 MB OBJ 173 MB 1.1 GB Visual GLB 36 MB 725 MB OBJ 110 MB 844 MB

2918. SystemBoardSMT

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.8	5.6	0.8 ms	6.1	0.3	1.0	0.2	15.5
Simulation, STEP	0.4	2.0	6.1	0.9 ms	6.6	5.4	0.9	0.3	21.7
Simulation, STL	0.4	2.0	5.9	0.9 ms	6.6	0.5	1.0	0.2	16.6
Simulation, OBJ	0.4	2.0	5.9	0.9 ms	6.5	11.8	1.1	0.3	28.0
Visual, GLB	0.4	2.1	6.0	0.9 ms	15.1	0.2	1.6	0.3	25.7
Visual, OBJ	0.4	1.8	5.9	0.8 ms	14.9	7.0	1.7	0.2	31.9

Board Repo: transistorfet/retroverse Board: SystemBoardSMT.kicad_pcb Folder components / systemboard / hardware / SystemBoardSMT Complexity 332 / 1000 (size 232, features 100) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 32, 896, 220 Triangles, simulation 2,137,672 in 128 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 72 MB 676 MB STEP 255 MB 839 MB STL 107 MB 687 MB OBJ 221 MB 1.4 GB Visual GLB 40 MB 805 MB OBJ 124 MB 978 MB

2919. CYM1A113

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.6	7.4	0.5 ms	7.1	0.3	0.8	0.2	17.9
Simulation, STEP	0.5	1.7	7.2	0.5 ms	7.1	4.4	0.8	0.2	21.9
Simulation, STL	0.6	1.7	7.1	0.6 ms	7.2	0.5	0.8	0.2	17.9
Simulation, OBJ	0.5	1.6	7.1	0.5 ms	6.9	9.0	0.8	0.2	26.2
Visual, GLB	0.5	1.7	7.1	0.6 ms	11.8	0.2	1.2	0.2	22.7
Visual, OBJ	0.5	1.7	7.4	0.6 ms	12.3	6.2	1.4	0.3	29.8

Board Repo: trezor/trezor-hardware Board: CYM1A113.kicad_pcb Folder electronics / trezor_model_t / kicad Complexity 339 / 1000 (size 244, features 95) KESE features through vias, microvias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 10th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 105, 971, 177 Triangles, simulation 1,570,744 in 133 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 55 MB 588 MB STEP 230 MB 743 MB STL 79 MB 601 MB OBJ 164 MB 1.1 GB Visual GLB 34 MB 754 MB OBJ 103 MB 818 MB

2920. trezor_v1.1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.6	3.0	0.4 ms	4.8	0.3	0.9	0.3	11.2
Simulation, STEP	0.3	1.8	3.0	0.4 ms	4.5	2.8	0.8	0.3	13.5
Simulation, STL	0.4	1.5	2.8	0.3 ms	4.3	0.4	0.7	0.3	10.4
Simulation, OBJ	0.2	1.4	2.6	0.4 ms	4.2	7.9	0.8	0.3	17.4
Visual, GLB	0.2	1.5	2.8	0.3 ms	7.8	96 ms	0.5	0.3	13.1
Visual, OBJ	0.3	1.4	2.6	0.4 ms	7.1	3.1	0.7	0.3	15.3

Board Repo: trezor/trezor-hardware Board: trezor_v1.1.kicad_pcb Folder electronics / trezor_one / kicad Complexity 301 / 1000 (size 256, features 45) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 16 File format KiCad 5 (20171130) Parts, tracks, vias 37, 545, 89 Triangles, simulation 1,305,058 in 88 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 39 MB 480 MB STEP 99 MB 563 MB STL 65 MB 470 MB OBJ 134 MB 854 MB Visual GLB 17 MB 446 MB OBJ 51 MB 439 MB

2921. iMX6 Demo Board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.1	7.7	23.9	2 ms	37.0	1.7	5.2	0.4	78.0
Simulation, STEP	2.2	7.9	24.6	3 ms	36.6	23.4	5.3	0.4	100.5
Simulation, STL	2.3	7.7	23.9	2 ms	36.9	3.6	5.5	0.5	80.5
Simulation, OBJ	2.4	8.1	24.1	2 ms	37.4	52.7	5.4	0.5	130.6
Visual, GLB	2.4	8.1	23.9	3 ms	85.6	1.1	9.9	0.4	131.3
Visual, OBJ	2.7	8.2	25.0	2 ms	86.4	30.0	10.3	0.4	162.8

Board Repo: ts-manuel/imx6-demo-board Board: iMX6 Demo Board.kicad_pcb Folder kicad Complexity 511 / 1000 (size 326, features 185) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 458, 7,806, 973 Triangles, simulation 9,038,324 in 603 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 306 MB 2.4 GB STEP 1.4 GB 3.2 GB STL 452 MB 2.5 GB OBJ 982 MB 5.7 GB Visual GLB 179 MB 2.9 GB OBJ 598 MB 3.7 GB

2922. iMX6 Demo Board_from_REF

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.3	4.3	11.5	3 ms	13.9	0.5	1.6	0.3	33.4
Simulation, STEP	1.4	4.2	11.6	1 ms	13.2	8.9	1.4	0.3	41.0
Simulation, STL	1.3	4.1	11.2	1.0 ms	14.2	0.9	1.5	0.3	33.7
Simulation, OBJ	1.4	4.3	11.6	1 ms	14.4	18.6	1.7	0.3	52.2
Visual, GLB	1.5	4.4	12.2	1 ms	32.1	0.3	2.6	0.3	53.3
Visual, OBJ	1.4	4.5	11.7	1 ms	30.9	11.4	2.9	0.3	63.2

Board Repo: ts-manuel/imx6-demo-board Board: iMX6 Demo Board_from_REF.kicad_pcb Folder kicad Complexity 433 / 1000 (size 313, features 120) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 6 File format KiCad 8 (20240108) Parts, tracks, vias 468, 3,672, 333 Triangles, simulation 3,165,490 in 480 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 107 MB 1.0 GB STEP 465 MB 1.3 GB STL 158 MB 1.0 GB OBJ 340 MB 2.1 GB Visual GLB 63 MB 1.4 GB OBJ 209 MB 1.5 GB

2923. RP2040_debugger

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	0.9	3.5	0.4 ms	3.9	0.2	0.7	0.2	9.8
Simulation, STEP	0.4	1.0	3.5	0.5 ms	4.2	3.6	0.7	0.2	13.5
Simulation, STL	0.4	1.0	3.6	0.4 ms	4.2	0.3	0.7	0.2	10.4
Simulation, OBJ	0.4	1.0	3.6	0.5 ms	4.1	6.0	0.6	0.3	16.0
Visual, GLB	0.4	1.0	3.7	0.6 ms	8.2	0.1	1.3	0.2	15.0
Visual, OBJ	0.4	1.0	3.6	0.4 ms	8.1	4.0	1.2	0.3	18.5

Board Repo: twisted-fields/rp2040-motor-controller Board: RP2040_debugger.kicad_pcb Folder debugger Complexity 322 / 1000 (size 227, features 95) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 57, 560, 87 Triangles, simulation 1,002,398 in 78 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 34 MB 433 MB STEP 156 MB 532 MB STL 50 MB 440 MB OBJ 101 MB 742 MB Visual GLB 24 MB 590 MB OBJ 72 MB 595 MB

2924. driver_module

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.1	3.7	0.4 ms	3.5	0.2	0.4	0.3	9.5
Simulation, STEP	0.4	1.1	3.4	0.3 ms	3.6	2.8	0.5	0.2	12.0
Simulation, STL	0.4	1.0	3.5	0.4 ms	3.5	0.3	0.4	0.2	9.4
Simulation, OBJ	0.3	1.2	3.5	0.3 ms	3.4	5.3	0.4	0.3	14.5
Visual, GLB	0.4	1.2	3.5	0.5 ms	9.1	0.1	1.0	0.3	15.6
Visual, OBJ	0.3	1.1	3.6	0.4 ms	9.7	3.3	1.0	0.3	19.4

Board Repo: twisted-fields/rp2040-motor-controller Board: driver_module.kicad_pcb Folder driver_module Complexity 294 / 1000 (size 199, features 95) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 106, 640, 162 Triangles, simulation 1,087,146 in 74 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 37 MB 436 MB STEP 137 MB 548 MB STL 54 MB 442 MB OBJ 111 MB 780 MB Visual GLB 24 MB 603 MB OBJ 73 MB 592 MB

2925. RP2040_base

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.2	4.1	13.9	1 ms	14.3	0.7	1.9	0.3	36.5
Simulation, STEP	1.1	4.3	13.4	0.6 ms	14.8	11.1	1.9	0.3	46.9
Simulation, STL	1.1	4.2	13.7	0.8 ms	14.7	1.3	1.8	0.3	37.0
Simulation, OBJ	1.2	4.5	14.1	1 ms	15.3	24.1	2.1	0.3	61.7
Visual, GLB	1.1	4.7	14.4	0.7 ms	42.0	0.5	4.6	0.3	67.6
Visual, OBJ	1.1	4.3	14.0	0.7 ms	42.1	16.8	4.5	0.3	83.1

Board Repo: twisted-fields/rp2040-motor-controller Board: RP2040_base.kicad_pcb Folder RP2040_base Complexity 418 / 1000 (size 283, features 135) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ Tested 10th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 257, 4,544, 553 Triangles, simulation 4,250,826 in 226 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 145 MB 1.2 GB STEP 592 MB 1.6 GB STL 213 MB 1.2 GB OBJ 456 MB 2.7 GB Visual GLB 100 MB 1.6 GB OBJ 319 MB 2.0 GB

2926. rp2040_encoder

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.1	0.4	0.1 ms	0.6	21 ms	79 ms	0.2	1.6
Simulation, STEP	0.1	0.2	0.4	0.2 ms	0.5	0.8	59 ms	0.2	2.3
Simulation, STL	0.1	0.2	0.4	0.1 ms	0.6	33 ms	73 ms	0.2	1.6
Simulation, OBJ	0.1	0.1	0.5	0.2 ms	0.6	0.6	72 ms	0.2	2.2
Visual, GLB	0.1	0.1	0.4	0.1 ms	1.3	18 ms	0.1	0.2	2.3
Visual, OBJ	0.1	0.1	0.5	0.1 ms	1.3	0.5	0.1	0.2	2.8

Board Repo: twisted-fields/rp2040-motor-controller Board: rp2040_encoder.kicad_pcb Folder rp2040_encoder Complexity 185 / 1000 (size 110, features 75) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 10, 47, 4 Triangles, simulation 126,086 in 22 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 4.4 MB 188 MB STEP 22 MB 204 MB STL 6.3 MB 189 MB OBJ 12 MB 189 MB Visual GLB 3.8 MB 168 MB OBJ 10 MB 164 MB

2927. user_interface

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.5	1.4	0.6 ms	1.5	72 ms	0.3	0.3	4.3
Simulation, STEP	0.3	0.6	1.5	0.2 ms	1.4	1.6	0.3	0.2	6.0
Simulation, STL	0.2	0.5	1.5	0.7 ms	1.5	0.2	0.3	0.3	4.4
Simulation, OBJ	0.2	0.6	1.5	0.2 ms	1.4	2.5	0.3	0.2	6.7
Visual, GLB	0.2	0.5	1.6	0.3 ms	4.4	56 ms	0.5	0.3	7.5
Visual, OBJ	0.2	0.5	1.5	0.3 ms	4.1	1.6	0.6	0.3	8.6

Board Repo: twisted-fields/rp2040-motor-controller Board: user_interface.kicad_pcb Folder user_interface Complexity 262 / 1000 (size 177, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 38, 386, 62 Triangles, simulation 492,310 in 40 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 17 MB 282 MB STEP 64 MB 336 MB STL 25 MB 292 MB OBJ 50 MB 390 MB Visual GLB 12 MB 330 MB OBJ 35 MB 331 MB

2928. Board-DjinnBase

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	76 ms	0.1	0.5	0.1 ms	0.6	29 ms	65 ms	0.2	1.5
Simulation, STEP	71 ms	0.1	0.4	0.1 ms	0.6	0.9	58 ms	0.2	2.4
Simulation, STL	73 ms	0.1	0.4	0.1 ms	0.6	41 ms	74 ms	0.2	1.6
Simulation, OBJ	92 ms	0.1	0.5	0.1 ms	0.6	0.8	61 ms	0.2	2.4
Visual, GLB	83 ms	0.1	0.4	0.1 ms	1.5	33 ms	0.2	0.2	2.5
Visual, OBJ	96 ms	0.1	0.5	0.1 ms	1.4	0.6	0.1	0.2	3.1

Board Repo: tzarc/keyboards Board: Board-DjinnBase.kicad_pcb Folder Djinn / Rev1 / Board-DjinnBase Complexity 54 / 1000 (size 24, features 30) KESE features filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 1, 0, 0 Triangles, simulation 177,144 in 12 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 5.9 MB 184 MB STEP 29 MB 197 MB STL 8.9 MB 187 MB OBJ 17 MB 191 MB Visual GLB 4.5 MB 139 MB OBJ 13 MB 159 MB

2929. Board-DjinnPlate

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	0.6	0.1 ms	1.0	55 ms	0.1	0.2	2.5
Simulation, STEP	0.2	0.3	0.6	0.1 ms	1.0	1.3	0.1	0.2	3.7
Simulation, STL	0.2	0.2	0.6	0.1 ms	1.0	80 ms	91 ms	0.2	2.3
Simulation, OBJ	0.2	0.3	0.6	0.1 ms	1.1	1.6	0.1	0.2	4.1
Visual, GLB	0.2	0.3	0.6	0.2 ms	2.4	43 ms	0.4	0.2	4.2
Visual, OBJ	0.2	0.4	0.6	0.1 ms	2.3	1.2	0.3	0.2	5.1

Board Repo: tzarc/keyboards Board: Board-DjinnPlate.kicad_pcb Folder Djinn / Rev1 / Board-DjinnPlate Complexity 69 / 1000 (size 29, features 40) KESE features slotted holes, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 2, 0, 0 Triangles, simulation 347,412 in 12 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 12 MB 272 MB STEP 69 MB 314 MB STL 17 MB 297 MB OBJ 35 MB 294 MB Visual GLB 9.6 MB 272 MB OBJ 28 MB 281 MB

2930. Djinn

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.4	12.4	30.0	0.9 ms	32.8	1.2	4.0	0.3	83.1
Simulation, STEP	2.4	12.1	29.7	1 ms	32.6	22.3	3.8	0.3	103.3
Simulation, STL	2.4	12.4	29.8	0.7 ms	32.2	2.5	3.7	0.3	83.3
Simulation, OBJ	2.4	12.2	29.5	1.0 ms	32.9	44.9	3.8	0.3	125.9
Visual, GLB	2.4	12.0	30.4	2 ms	91.8	1.0	10.4	0.3	148.2
Visual, OBJ	2.4	12.1	29.9	0.7 ms	89.8	38.1	9.9	0.3	182.7

Board Repo: tzarc/keyboards Board: Djinn.kicad_pcb Folder Djinn / Rev1 Complexity 345 / 1000 (size 255, features 90) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 230, 2,956, 630 Triangles, simulation 7,553,280 in 180 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 258 MB 2.7 GB STEP 1.4 GB 3.1 GB STL 378 MB 2.6 GB OBJ 807 MB 4.8 GB Visual GLB 234 MB 3.4 GB OBJ 749 MB 4.5 GB

2931. Djinn

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.5	13.9	33.8	2 ms	33.7	1.2	4.8	0.4	90.2
Simulation, STEP	2.6	14.2	34.0	2 ms	35.2	22.4	5.1	0.3	113.8
Simulation, STL	2.6	14.5	35.4	2 ms	35.6	2.6	4.6	0.3	95.6
Simulation, OBJ	2.7	13.9	34.4	2 ms	33.6	48.2	4.6	0.3	137.6
Visual, GLB	2.6	14.4	34.5	2 ms	100.0	1.3	12.1	0.3	165.1
Visual, OBJ	2.7	14.5	35.5	2 ms	101.8	40.9	12.0	0.3	207.6

Board Repo: tzarc/keyboards Board: Djinn.kicad_pcb Folder Djinn / Rev2a Complexity 353 / 1000 (size 263, features 90) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 230, 3,274, 711 Triangles, simulation 7,974,724 in 196 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 273 MB 2.9 GB STEP 1.5 GB 3.2 GB STL 399 MB 2.8 GB OBJ 856 MB 5.0 GB Visual GLB 245 MB 3.6 GB OBJ 787 MB 4.7 GB

2932. ExtraBoard-Base

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	2.4	0.3 ms	2.0	75 ms	0.2	0.3	5.5
Simulation, STEP	0.1	0.3	2.7	0.3 ms	1.6	1.9	0.3	0.2	7.2
Simulation, STL	0.2	0.3	2.6	0.2 ms	1.7	0.1	0.2	0.2	5.4
Simulation, OBJ	0.1	0.3	2.5	0.2 ms	1.7	2.4	0.3	0.3	7.7
Visual, GLB	0.1	0.3	2.4	0.4 ms	2.7	45 ms	0.3	0.3	6.2
Visual, OBJ	0.1	0.3	2.7	0.3 ms	3.1	1.1	0.3	0.3	7.8

Board Repo: tzarc/keyboards Board: ExtraBoard-Base.kicad_pcb Folder Djinn / Rev2a / ExtraBoard-Base Complexity 74 / 1000 (size 44, features 30) KESE features filled zones, curved board outline Tested 10th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 11, 0, 0 Triangles, simulation 382,012 in 12 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 13 MB 249 MB STEP 57 MB 272 MB STL 19 MB 250 MB OBJ 38 MB 283 MB Visual GLB 6.2 MB 198 MB OBJ 18 MB 216 MB

2933. ExtraBoard-Plate

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	0.8	2.6	0.4 ms	2.6	0.1	0.3	0.3	7.0
Simulation, STEP	0.3	0.6	2.5	0.4 ms	2.4	2.3	0.3	0.2	8.6
Simulation, STL	0.3	0.7	2.7	0.6 ms	2.5	0.3	0.3	0.2	7.0
Simulation, OBJ	0.3	0.7	2.7	0.6 ms	2.5	4.0	0.3	0.3	10.8
Visual, GLB	0.4	0.7	2.6	0.4 ms	5.3	82 ms	0.9	0.2	10.2
Visual, OBJ	0.3	0.8	2.6	0.3 ms	4.9	2.3	0.8	0.2	12.0

Board Repo: tzarc/keyboards Board: ExtraBoard-Plate.kicad_pcb Folder Djinn / Rev2a / ExtraBoard-Plate Complexity 85 / 1000 (size 45, features 40) KESE features slotted holes, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 13, 0, 0 Triangles, simulation 743,632 in 12 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 25 MB 442 MB STEP 141 MB 486 MB STL 37 MB 445 MB OBJ 75 MB 560 MB Visual GLB 17 MB 432 MB OBJ 50 MB 432 MB

2934. ghoul

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.4	5.6	17.5	1 ms	19.7	0.7	2.0	0.3	47.2
Simulation, STEP	1.5	5.9	17.6	1 ms	20.5	13.1	2.0	0.3	60.9
Simulation, STL	1.5	5.9	17.6	0.9 ms	21.6	1.3	2.2	0.3	50.4
Simulation, OBJ	1.5	6.2	18.2	1 ms	20.2	23.8	2.1	0.3	72.4
Visual, GLB	1.5	6.2	18.6	0.9 ms	44.5	0.6	5.7	0.3	77.4
Visual, OBJ	1.5	6.2	18.6	1 ms	45.1	20.1	5.8	0.3	97.5

Board Repo: tzarc/keyboards Board: ghoul.kicad_pcb Folder Ghoul / v1.0 Complexity 326 / 1000 (size 206, features 120) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ Tested 10th November 2026 Copper layers 2 File format KiCad 6 (20211014) Parts, tracks, vias 166, 2,087, 497 Triangles, simulation 3,894,076 in 191 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 134 MB 1.5 GB STEP 737 MB 1.8 GB STL 195 MB 1.5 GB OBJ 417 MB 2.6 GB Visual GLB 116 MB 1.8 GB OBJ 371 MB 2.5 GB

2935. half-plate

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.2	0.1	0.1 ms	0.9	27 ms	49 ms	0.2	1.7
Simulation, STEP	0.1	0.2	0.1	0.1 ms	0.9	1.0	56 ms	0.2	2.6
Simulation, STL	0.1	0.2	0.1	0.1 ms	0.9	44 ms	48 ms	0.2	1.7
Simulation, OBJ	0.1	0.2	0.2	0.1 ms	0.9	0.9	63 ms	0.2	2.6
Visual, GLB	0.1	0.2	0.2	0.1 ms	1.4	29 ms	0.2	0.2	2.3
Visual, OBJ	0.2	0.2	0.1	0.1 ms	1.4	0.8	0.2	0.2	3.0

Board Repo: tzarc/keyboards Board: half-plate.kicad_pcb Folder Ghoul / v1.0 / half-plate Complexity 47 / 1000 (size 17, features 30) KESE features filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 6 (20211014) Parts, tracks, vias 0, 0, 0 Triangles, simulation 173,544 in 6 parts Note no components Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 6.1 MB 230 MB STEP 32 MB 249 MB STL 8.7 MB 227 MB OBJ 17 MB 234 MB Visual GLB 5.0 MB 191 MB OBJ 14 MB 191 MB

2936. Kobold

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	2.2	7.5	0.5 ms	8.8	0.4	1.1	0.3	21.0
Simulation, STEP	0.7	2.1	7.4	0.6 ms	9.2	6.9	1.1	0.2	27.6
Simulation, STL	0.7	2.1	7.7	0.5 ms	9.5	0.9	1.1	0.2	22.2
Simulation, OBJ	0.6	2.1	7.2	0.5 ms	9.4	15.1	1.1	0.3	35.8
Visual, GLB	0.7	2.2	7.5	0.5 ms	19.3	0.3	2.5	0.2	32.7
Visual, OBJ	0.7	2.1	7.4	0.5 ms	19.2	9.8	2.5	0.3	42.1

Board Repo: tzarc/keyboards Board: Kobold.kicad_pcb Folder Kobold / R1 Complexity 339 / 1000 (size 244, features 95) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 95, 971, 220 Triangles, simulation 2,671,456 in 99 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 92 MB 904 MB STEP 424 MB 1.1 GB STL 134 MB 861 MB OBJ 282 MB 1.7 GB Visual GLB 59 MB 1.0 GB OBJ 183 MB 1.2 GB

2937. APPS final

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	30 ms	91 ms	0.5	0.2 ms	0.6	26 ms	74 ms	0.2	1.5
Simulation, STEP	28 ms	93 ms	0.5	0.1 ms	0.6	0.7	77 ms	0.2	2.2
Simulation, STL	31 ms	0.1	0.6	0.1 ms	0.6	33 ms	73 ms	0.2	1.5
Simulation, OBJ	30 ms	99 ms	0.5	0.1 ms	0.6	0.6	92 ms	0.2	2.1
Visual, GLB	30 ms	91 ms	0.5	0.2 ms	1.2	12 ms	82 ms	0.2	2.1
Visual, OBJ	30 ms	0.1	0.5	0.2 ms	1.2	0.3	74 ms	0.2	2.4

Board Repo: ucdfs/circuits Board: APPS final.kicad_pcb Folder APPS_KR Complexity 169 / 1000 (size 99, features 70) KESE features rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 12, 26, 0 Triangles, simulation 151,248 in 19 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 5.2 MB 182 MB STEP 24 MB 184 MB STL 7.6 MB 182 MB OBJ 15 MB 180 MB Visual GLB 2.8 MB 139 MB OBJ 7.9 MB 140 MB

2938. Battery Temperature Sensor

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.6	2.7	0.3 ms	3.8	0.1	0.4	0.2	8.2
Simulation, STEP	0.3	0.6	2.9	0.2 ms	3.8	3.1	0.4	0.2	11.3
Simulation, STL	0.4	0.6	2.9	0.2 ms	3.9	0.4	0.4	0.2	8.9
Simulation, OBJ	0.3	0.6	2.9	0.3 ms	4.2	3.5	0.4	0.2	12.2
Visual, GLB	0.3	0.5	2.8	0.4 ms	6.2	0.1	1.0	0.2	11.2
Visual, OBJ	0.3	0.6	2.8	0.3 ms	6.2	2.6	1.0	0.3	13.8

Board Repo: ucdfs/circuits Board: Battery Temperature Sensor.kicad_pcb Folder Archive / Battery Temperature Sensor_KR Complexity 257 / 1000 (size 172, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 107, 419, 58 Triangles, simulation 735,112 in 53 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 25 MB 414 MB STEP 119 MB 450 MB STL 37 MB 417 MB OBJ 73 MB 519 MB Visual GLB 19 MB 598 MB OBJ 56 MB 603 MB

2939. LTC6812-15W

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.0	3.9	0.6 ms	4.6	0.2	0.5	0.3	11.0
Simulation, STEP	0.5	0.9	3.7	0.9 ms	4.4	3.8	0.6	0.2	14.1
Simulation, STL	0.6	0.9	3.7	0.7 ms	4.7	0.4	0.5	0.3	11.0
Simulation, OBJ	0.5	0.9	3.6	0.6 ms	4.3	6.0	0.6	0.2	16.2
Visual, GLB	0.5	0.9	3.9	0.7 ms	11.4	0.1	1.1	0.3	18.2
Visual, OBJ	0.6	0.9	3.6	0.8 ms	10.8	4.6	1.5	0.2	22.2

Board Repo: ucdfs/circuits Board: LTC6812-15W.kicad_pcb Folder ENNOID_BMS / Slave Complexity 324 / 1000 (size 244, features 80) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 246, 1,418, 64 Triangles, simulation 1,120,794 in 280 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 38 MB 580 MB STEP 189 MB 627 MB STL 56 MB 565 MB OBJ 113 MB 767 MB Visual GLB 30 MB 835 MB OBJ 92 MB 832 MB

2940. (LVE)Shutdown

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.1	6.7	0.4 ms	4.8	0.2	0.7	0.2	14.0
Simulation, STEP	0.4	1.1	6.8	0.4 ms	4.7	3.9	0.6	0.2	17.7
Simulation, STL	0.4	1.1	6.2	0.4 ms	4.9	0.4	0.6	0.2	14.0
Simulation, OBJ	0.4	1.1	6.5	0.4 ms	4.6	7.1	0.6	0.2	20.5
Visual, GLB	0.4	1.1	6.2	0.4 ms	8.8	0.1	1.0	0.2	18.0
Visual, OBJ	0.4	1.1	6.3	0.4 ms	8.8	4.2	1.1	0.2	22.0

Board Repo: ucdfs/circuits Board: (LVE)Shutdown.kicad_pcb Folder Kieran Care package / (LVE)Shutdown_KR Complexity 253 / 1000 (size 168, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 114, 410, 11 Triangles, simulation 1,386,784 in 81 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 47 MB 599 MB STEP 202 MB 693 MB STL 69 MB 608 MB OBJ 141 MB 965 MB Visual GLB 29 MB 730 MB OBJ 88 MB 728 MB

2941. BSPD KiCAD

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	0.7	3.8	0.6 ms	2.8	0.1	0.4	0.2	8.5
Simulation, STEP	0.3	0.6	3.7	0.6 ms	2.8	2.4	0.4	0.2	10.4
Simulation, STL	0.3	0.6	3.8	0.7 ms	3.0	0.3	0.4	0.2	8.7
Simulation, OBJ	0.3	0.7	3.8	0.6 ms	2.8	4.3	0.4	0.2	12.6
Visual, GLB	0.3	0.6	3.7	0.6 ms	5.7	74 ms	0.7	0.2	11.3
Visual, OBJ	0.3	0.6	3.7	0.6 ms	5.3	2.8	0.8	0.2	13.6

Board Repo: ucdfs/circuits Board: BSPD KiCAD.kicad_pcb Folder Kieran Care package / BSPD_KR Complexity 239 / 1000 (size 154, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 59, 276, 5 Triangles, simulation 878,990 in 47 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 30 MB 434 MB STEP 125 MB 503 MB STL 44 MB 434 MB OBJ 88 MB 625 MB Visual GLB 18 MB 534 MB OBJ 55 MB 456 MB

2942. Charger_Shutdown_KR

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.4	2.2	0.3 ms	1.9	76 ms	0.3	0.2	5.2
Simulation, STEP	0.2	0.3	2.1	0.7 ms	2.0	1.6	0.3	0.2	6.6
Simulation, STL	0.2	0.4	2.1	0.3 ms	2.0	0.1	0.3	0.2	5.3
Simulation, OBJ	0.2	0.4	2.2	0.4 ms	2.1	2.5	0.3	0.3	8.1
Visual, GLB	0.2	0.3	2.1	0.4 ms	3.8	50 ms	0.4	0.2	7.2
Visual, OBJ	0.2	0.4	2.1	0.4 ms	3.7	1.5	0.4	0.2	8.5

Board Repo: ucdfs/circuits Board: Charger_Shutdown_KR.kicad_pcb Folder Kieran Care package / Charger_Shutdown_KR Complexity 232 / 1000 (size 147, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 41, 209, 10 Triangles, simulation 524,408 in 45 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 17 MB 318 MB STEP 77 MB 361 MB STL 26 MB 307 MB OBJ 52 MB 389 MB Visual GLB 11 MB 343 MB OBJ 33 MB 351 MB

2943. Discharge KiCAD

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.7	0.1 ms	0.8	31 ms	0.1	0.2	2.2
Simulation, STEP	0.1	0.2	0.7	0.1 ms	0.7	0.9	0.1	0.2	3.0
Simulation, STL	0.1	0.2	0.8	0.2 ms	0.8	43 ms	0.1	0.2	2.2
Simulation, OBJ	0.1	0.2	0.8	0.1 ms	0.7	0.9	0.1	0.2	3.0
Visual, GLB	0.1	0.2	0.8	0.2 ms	1.5	26 ms	0.2	0.2	3.0
Visual, OBJ	0.1	0.2	0.8	0.2 ms	1.4	0.6	0.1	0.2	3.4

Board Repo: ucdfs/circuits Board: Discharge KiCAD.kicad_pcb Folder Kieran Care package / Discharge_KR Complexity 194 / 1000 (size 119, features 75) KESE features custom pads, rounded, trapezoid or chamfered pads, copper drawings, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 16, 80, 0 Triangles, simulation 203,798 in 22 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 6.8 MB 214 MB STEP 26 MB 228 MB STL 10 MB 219 MB OBJ 20 MB 212 MB Visual GLB 4.4 MB 188 MB OBJ 12 MB 192 MB

2944. Cell Tap Fuse Board 2x

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	91 ms	60 ms	0.1	0.1 ms	0.3	7 ms	29 ms	0.2	0.8
Simulation, STEP	87 ms	51 ms	0.1	0.1 ms	0.3	0.3	26 ms	0.2	1.1
Simulation, STL	87 ms	59 ms	0.2	0.1 ms	0.3	12 ms	26 ms	0.2	0.9
Simulation, OBJ	84 ms	45 ms	0.1	0.1 ms	0.2	0.1	32 ms	0.2	0.9
Visual, GLB	85 ms	59 ms	0.2	0.1 ms	0.4	6 ms	48 ms	0.2	1.0
Visual, OBJ	80 ms	51 ms	0.1	0.1 ms	0.4	0.1	50 ms	0.2	1.1

Board Repo: ucdfs/circuits Board: Cell Tap Fuse Board 2x.kicad_pcb Folder Kieran Care package / ENNOID_BMS - Cell Tap Fuse Board 2x Complexity 115 / 1000 (size 65, features 50) KESE features rounded, trapezoid or chamfered pads, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 2, 8, 0 Triangles, simulation 41,276 in 13 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 1.4 MB 68 MB STEP 6.3 MB 73 MB STL 2.1 MB 68 MB OBJ 3.9 MB 78 MB Visual GLB 1.0 MB 103 MB OBJ 2.7 MB 103 MB

2945. Cell Tap Fuse Board 3x

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	99 ms	83 ms	0.2	0.1 ms	0.4	11 ms	40 ms	0.2	1.1
Simulation, STEP	84 ms	73 ms	0.3	0.1 ms	0.4	0.7	32 ms	0.2	1.8
Simulation, STL	93 ms	72 ms	0.2	0.1 ms	0.5	17 ms	41 ms	0.2	1.2
Simulation, OBJ	84 ms	60 ms	0.2	0.1 ms	0.4	0.3	34 ms	0.2	1.3
Visual, GLB	86 ms	62 ms	0.2	0.1 ms	0.8	11 ms	63 ms	0.2	1.5
Visual, OBJ	77 ms	66 ms	0.3	0.1 ms	0.7	0.2	51 ms	0.2	1.6

Board Repo: ucdfs/circuits Board: Cell Tap Fuse Board 3x.kicad_pcb Folder Kieran Care package / ENNOID_BMS - Cell Tap Fuse Board 3x Complexity 131 / 1000 (size 81, features 50) KESE features rounded, trapezoid or chamfered pads, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 4, 16, 0 Triangles, simulation 69,248 in 16 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 2.2 MB 171 MB STEP 9.5 MB 173 MB STL 3.5 MB 170 MB OBJ 6.6 MB 170 MB Visual GLB 1.5 MB 151 MB OBJ 4.2 MB 150 MB

2946. BMS-Master

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	1.3	7.6	1 ms	9.8	0.3	1.0	0.3	20.9
Simulation, STEP	0.6	1.4	7.7	0.7 ms	9.8	6.6	1.0	0.3	27.4
Simulation, STL	0.7	1.4	7.7	0.7 ms	9.8	0.5	1.0	0.3	21.3
Simulation, OBJ	0.6	1.3	7.5	0.8 ms	10.1	8.5	1.0	0.3	29.3
Visual, GLB	0.6	1.4	7.3	0.7 ms	14.5	0.2	1.4	0.3	25.7
Visual, OBJ	0.6	1.4	7.5	0.9 ms	14.7	7.0	1.6	0.3	33.0

Board Repo: ucdfs/circuits Board: BMS-Master.kicad_pcb Folder Kieran Care package / ENNOID_BMS - Master Complexity 347 / 1000 (size 237, features 110) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 218, 1,289, 130 Triangles, simulation 1,469,656 in 201 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 51 MB 664 MB STEP 263 MB 774 MB STL 73 MB 691 MB OBJ 151 MB 1.0 GB Visual GLB 40 MB 869 MB OBJ 122 MB 926 MB

2947. LTC6812-15W

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	0.9	4.0	0.7 ms	5.6	0.2	0.6	0.3	12.0
Simulation, STEP	0.5	0.9	3.9	0.6 ms	5.1	4.2	0.6	0.2	15.3
Simulation, STL	0.5	0.9	3.9	0.6 ms	5.3	0.5	0.6	0.2	11.9
Simulation, OBJ	0.5	0.9	3.8	1 ms	5.3	5.7	0.6	0.3	17.0
Visual, GLB	0.5	0.8	4.0	0.8 ms	11.6	0.2	1.2	0.2	18.5
Visual, OBJ	0.5	0.9	3.8	0.8 ms	11.6	4.6	1.3	0.2	22.9

Board Repo: ucdfs/circuits Board: LTC6812-15W.kicad_pcb Folder Kieran Care package / ENNOID_BMS - Slave Complexity 344 / 1000 (size 244, features 100) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 246, 1,418, 64 Triangles, simulation 1,384,100 in 280 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 47 MB 609 MB STEP 260 MB 713 MB STL 69 MB 589 MB OBJ 142 MB 965 MB Visual GLB 39 MB 703 MB OBJ 116 MB 892 MB

2948. TSAL

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.1	6.8	0.6 ms	5.5	0.2	0.7	0.3	15.1
Simulation, STEP	0.3	1.0	6.4	1.0 ms	5.8	4.1	0.8	0.3	18.9
Simulation, STL	0.3	1.1	6.6	0.5 ms	5.6	0.4	0.8	0.3	15.2
Simulation, OBJ	0.4	1.1	6.7	0.6 ms	5.7	7.7	0.8	0.2	22.8
Visual, GLB	0.4	1.0	6.8	2 ms	10.9	0.1	1.3	0.2	20.7
Visual, OBJ	0.4	1.2	6.8	0.5 ms	10.6	4.4	1.3	0.2	24.9

Board Repo: ucdfs/circuits Board: TSAL.kicad_pcb Folder Kieran Care package / NEW_TSAL_KR Complexity 259 / 1000 (size 174, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 99, 613, 23 Triangles, simulation 1,575,932 in 88 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 53 MB 665 MB STEP 220 MB 773 MB STL 79 MB 666 MB OBJ 160 MB 1.1 GB Visual GLB 30 MB 781 MB OBJ 92 MB 730 MB

2949. PDU_KR

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	2.3	0.3 ms	1.5	97 ms	0.3	0.3	5.1
Simulation, STEP	0.3	0.4	2.3	0.5 ms	1.6	1.7	0.3	0.3	6.9
Simulation, STL	0.2	0.4	2.1	0.2 ms	1.6	0.1	0.3	0.2	4.8
Simulation, OBJ	0.2	0.4	2.4	0.2 ms	1.6	2.6	0.3	0.2	7.6
Visual, GLB	0.2	0.4	2.5	0.3 ms	3.5	49 ms	0.5	0.2	7.3
Visual, OBJ	0.2	0.4	2.3	0.3 ms	3.4	1.5	0.5	0.3	8.6

Board Repo: ucdfs/circuits Board: PDU_KR.kicad_pcb Folder Kieran Care package / PDU_KR Complexity 206 / 1000 (size 136, features 70) KESE features rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 44, 114, 0 Triangles, simulation 502,746 in 34 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 17 MB 323 MB STEP 87 MB 337 MB STL 25 MB 296 MB OBJ 51 MB 385 MB Visual GLB 10 MB 326 MB OBJ 30 MB 328 MB

2950. Pre-charge KiCAD

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.5	3.1	0.3 ms	2.2	0.1	0.4	0.2	6.9
Simulation, STEP	0.3	0.5	3.2	0.3 ms	2.1	2.0	0.4	0.2	8.8
Simulation, STL	0.3	0.6	3.1	0.3 ms	2.2	0.2	0.4	0.2	7.0
Simulation, OBJ	0.3	0.5	3.0	0.3 ms	2.2	3.7	0.5	0.2	10.4
Visual, GLB	0.3	0.6	3.2	0.4 ms	5.1	76 ms	0.6	0.2	10.1
Visual, OBJ	0.3	0.6	3.2	0.3 ms	4.7	2.5	0.7	0.3	12.3

Board Repo: ucdfs/circuits Board: Pre-charge KiCAD.kicad_pcb Folder Kieran Care package / Pre-charge_KR Complexity 264 / 1000 (size 154, features 110) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 51, 274, 13 Triangles, simulation 666,692 in 42 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 23 MB 359 MB STEP 102 MB 419 MB STL 33 MB 365 MB OBJ 67 MB 478 MB Visual GLB 15 MB 372 MB OBJ 43 MB 443 MB

2951. Breakout

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.8	5.0	0.4 ms	3.9	0.2	0.5	0.2	11.0
Simulation, STEP	0.3	0.8	5.1	0.6 ms	3.8	3.0	0.5	0.2	13.7
Simulation, STL	0.3	0.8	4.8	0.4 ms	3.7	0.3	0.5	0.2	10.7
Simulation, OBJ	0.3	0.8	4.8	0.4 ms	3.7	5.8	0.6	0.2	16.1
Visual, GLB	0.3	0.8	5.0	0.4 ms	7.2	0.1	0.8	0.2	14.5
Visual, OBJ	0.3	0.8	5.0	0.4 ms	7.2	3.4	0.9	0.2	17.9

Board Repo: ucdfs/circuits Board: Breakout.kicad_pcb Folder Kieran Care package / Teensy 4.1 Breakout Board Complexity 235 / 1000 (size 150, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 53, 218, 6 Triangles, simulation 1,096,444 in 107 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 37 MB 507 MB STEP 155 MB 559 MB STL 55 MB 481 MB OBJ 110 MB 747 MB Visual GLB 22 MB 521 MB OBJ 67 MB 590 MB

2952. Voltage_Measurement_KR

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.5	2.6	0.4 ms	2.0	96 ms	0.4	0.3	6.1
Simulation, STEP	0.2	0.5	2.7	0.4 ms	1.9	2.0	0.4	0.2	8.1
Simulation, STL	0.2	0.5	2.7	0.8 ms	2.1	0.2	0.4	0.2	6.2
Simulation, OBJ	0.2	0.5	2.7	0.4 ms	2.2	3.3	0.4	0.2	9.7
Visual, GLB	0.2	0.6	2.8	0.6 ms	4.6	63 ms	0.6	0.2	9.0
Visual, OBJ	0.3	0.5	2.8	0.5 ms	4.5	2.0	0.7	0.3	11.1

Board Repo: ucdfs/circuits Board: Voltage_Measurement_KR.kicad_pcb Folder Kieran Care package / Voltage_Measurement_KR Complexity 235 / 1000 (size 150, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 52, 225, 7 Triangles, simulation 638,094 in 38 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 21 MB 361 MB STEP 92 MB 393 MB STL 32 MB 367 MB OBJ 64 MB 457 MB Visual GLB 14 MB 421 MB OBJ 41 MB 431 MB

2953. flightcontroller

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	2.0	7.4	0.6 ms	8.7	0.4	1.1	0.3	20.6
Simulation, STEP	0.9	2.1	7.1	0.6 ms	8.2	6.6	1.0	0.3	26.2
Simulation, STL	0.8	2.1	6.8	0.9 ms	9.0	0.8	1.1	0.2	20.9
Simulation, OBJ	0.8	2.1	7.2	0.6 ms	8.5	12.0	1.1	0.3	32.0
Visual, GLB	0.8	2.0	7.2	0.6 ms	16.3	0.2	2.0	0.3	28.8
Visual, OBJ	0.8	2.1	7.3	0.7 ms	15.8	8.1	2.3	0.2	36.7

Board Repo: ukinori/flightcontroller Board: flightcontroller.kicad_pcb Complexity 348 / 1000 (size 263, features 85) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 10 (20260206) Parts, tracks, vias 129, 3,528, 249 Triangles, simulation 2,284,130 in 154 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 78 MB 807 MB STEP 366 MB 1.0 GB STL 114 MB 811 MB OBJ 238 MB 1.5 GB Visual GLB 52 MB 963 MB OBJ 162 MB 1.1 GB

2954. uECG_v4_5

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.8	2.8	0.6 ms	3.8	0.1	0.4	0.3	8.4
Simulation, STEP	0.3	0.6	2.7	0.5 ms	3.8	2.5	0.4	0.2	10.6
Simulation, STL	0.3	0.6	2.6	0.4 ms	3.9	0.2	0.4	0.2	8.2
Simulation, OBJ	0.2	0.7	2.6	0.4 ms	3.9	3.5	0.4	0.3	11.5
Visual, GLB	0.2	0.7	2.7	0.4 ms	7.2	0.1	0.9	0.3	12.1
Visual, OBJ	0.2	0.7	2.6	0.6 ms	7.2	3.1	0.9	0.2	14.9

Board Repo: ultimaterobotics/uECG_pcb Board: uECG_v4_5.kicad_pcb Folder uECG_v4_5 Complexity 273 / 1000 (size 218, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 67, 730, 138 Triangles, simulation 725,870 in 100 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 25 MB 389 MB STEP 126 MB 492 MB STL 36 MB 388 MB OBJ 73 MB 541 MB Visual GLB 23 MB 568 MB OBJ 68 MB 571 MB

2955. uECG_v4_52_lsm_tlv

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.7	2.5	0.4 ms	3.2	0.1	0.4	0.2	7.4
Simulation, STEP	0.3	0.7	2.4	0.3 ms	3.3	2.4	0.4	0.2	9.7
Simulation, STL	0.3	0.7	2.4	0.3 ms	3.0	0.2	0.4	0.2	7.1
Simulation, OBJ	0.3	0.7	2.4	0.3 ms	3.3	3.6	0.4	0.2	11.0
Visual, GLB	0.3	0.7	2.7	0.3 ms	5.9	95 ms	0.5	0.2	10.4
Visual, OBJ	0.3	0.7	2.5	0.5 ms	5.9	3.2	0.5	0.2	13.2

Board Repo: ultimaterobotics/uECG_pcb Board: uECG_v4_52_lsm_tlv.kicad_pcb Folder uECG_v4_52_lsm_tlv Complexity 310 / 1000 (size 220, features 90) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 6 (20211014) Parts, tracks, vias 71, 814, 147 Triangles, simulation 754,512 in 97 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 26 MB 390 MB STEP 140 MB 483 MB STL 38 MB 394 MB OBJ 77 MB 525 MB Visual GLB 23 MB 570 MB OBJ 69 MB 528 MB

2956. NanoS3_Carrier

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.5	2.4	0.4 ms	2.0	0.1	0.3	0.3	5.7
Simulation, STEP	0.2	0.5	2.3	0.2 ms	1.9	1.7	0.3	0.2	7.2
Simulation, STL	0.2	0.5	2.3	0.3 ms	2.0	0.2	0.3	0.2	5.6
Simulation, OBJ	0.2	0.5	2.4	0.3 ms	2.1	2.9	0.4	0.2	8.6
Visual, GLB	0.2	0.5	2.4	0.3 ms	4.8	69 ms	0.6	0.3	8.8
Visual, OBJ	0.2	0.5	2.4	0.3 ms	4.5	2.1	0.6	0.2	10.6

Board Repo: UnexpectedMaker/esp32s3 Board: NanoS3_Carrier.kicad_pcb Folder kicad / NanoS3 Carrier Complexity 267 / 1000 (size 152, features 115) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 20, 255, 83 Triangles, simulation 547,766 in 55 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 19 MB 306 MB STEP 102 MB 347 MB STL 27 MB 319 MB OBJ 56 MB 427 MB Visual GLB 14 MB 364 MB OBJ 43 MB 382 MB

2957. OMGS3_Carrier_R1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	1.6	0.3 ms	1.3	63 ms	0.2	0.2	3.8
Simulation, STEP	0.2	0.3	1.4	0.2 ms	1.3	1.3	0.2	0.2	4.9
Simulation, STL	0.2	0.3	1.4	0.3 ms	1.2	87 ms	0.2	0.2	3.5
Simulation, OBJ	0.2	0.4	1.5	0.2 ms	1.2	1.6	0.3	0.2	5.2
Visual, GLB	0.2	0.4	1.6	0.2 ms	3.1	42 ms	0.4	0.2	5.9
Visual, OBJ	0.2	0.3	1.5	0.5 ms	2.9	1.3	0.3	0.2	6.8

Board Repo: UnexpectedMaker/esp32s3 Board: OMGS3_Carrier_R1.kicad_pcb Folder kicad / OMGS3 Carrier Complexity 269 / 1000 (size 144, features 125) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 15, 134, 80 Triangles, simulation 353,816 in 40 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 12 MB 259 MB STEP 52 MB 290 MB STL 18 MB 252 MB OBJ 36 MB 292 MB Visual GLB 8.9 MB 278 MB OBJ 26 MB 279 MB

2958. EdgeS3D_Carrier_P1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.7	3.3	0.3 ms	3.2	0.1	0.4	0.2	8.3
Simulation, STEP	0.2	0.7	3.2	0.3 ms	3.0	2.3	0.5	0.2	10.1
Simulation, STL	0.2	0.6	3.3	0.3 ms	3.0	0.2	0.4	0.2	8.0
Simulation, OBJ	0.2	0.7	3.3	0.8 ms	3.3	4.1	0.5	0.2	12.4
Visual, GLB	0.2	0.7	3.4	0.3 ms	6.7	95 ms	0.7	0.2	12.1
Visual, OBJ	0.2	0.7	3.5	0.5 ms	6.8	3.1	0.7	0.2	15.2

Board Repo: UnexpectedMaker/esp32s3 Board: EdgeS3D_Carrier_P1.kicad_pcb Folder series_d / KiCAD / EdgeS3D_Carrier_P1 Complexity 257 / 1000 (size 157, features 100) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 15, 338, 160 Triangles, simulation 769,534 in 70 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 27 MB 378 MB STEP 126 MB 465 MB STL 38 MB 398 MB OBJ 79 MB 556 MB Visual GLB 21 MB 527 MB OBJ 64 MB 529 MB

2959. armory

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	3.9	14.4	0.5 ms	14.2	0.7	2.0	0.3	36.2
Simulation, STEP	0.6	4.0	14.9	1 ms	14.4	8.9	2.0	0.3	45.0
Simulation, STL	0.7	4.1	14.8	1 ms	14.6	1.4	2.2	0.3	38.1
Simulation, OBJ	0.7	4.1	14.3	0.5 ms	14.7	21.4	2.4	0.4	57.9
Visual, GLB	0.6	4.4	15.1	0.7 ms	28.6	0.4	4.2	0.3	53.6
Visual, OBJ	0.7	4.3	14.7	0.5 ms	27.7	11.7	4.7	0.3	64.1

Board Repo: usbarmory/usbarmory Board: armory.kicad_pcb Folder hardware / mark-one Complexity 339 / 1000 (size 294, features 45) KESE features through vias, filled zones, curved board outline Tested 9th November 2026 Copper layers 8 File format KiCad 3 (3) Parts, tracks, vias 174, 2,408, 337 Triangles, simulation 4,039,766 in 144 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 140 MB 1.2 GB STEP 558 MB 1.4 GB STL 202 MB 1.1 GB OBJ 443 MB 2.7 GB Visual GLB 75 MB 1.4 GB OBJ 240 MB 1.6 GB

2960. armory

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.5	4.7	15.4	0.9 ms	18.5	0.9	2.5	0.4	44.0
Simulation, STEP	1.6	4.8	15.0	2 ms	19.0	11.9	2.8	0.4	55.6
Simulation, STL	1.6	4.8	15.4	0.9 ms	19.3	2.2	2.6	0.3	46.2
Simulation, OBJ	1.7	4.7	14.7	2 ms	18.9	27.5	2.7	0.4	70.6
Visual, GLB	2.1	5.6	15.4	2 ms	40.4	0.4	5.4	0.3	69.6
Visual, OBJ	1.7	5.1	15.4	1 ms	39.7	14.2	5.8	0.3	82.2

Board Repo: usbarmory/usbarmory Board: armory.kicad_pcb Folder hardware / mark-two-beta Complexity 400 / 1000 (size 320, features 80) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 6 File format KiCad 5 (20171130) Parts, tracks, vias 180, 18,286, 423 Triangles, simulation 5,129,354 in 434 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 178 MB 1.5 GB STEP 738 MB 1.8 GB STL 257 MB 1.5 GB OBJ 553 MB 3.3 GB Visual GLB 94 MB 1.6 GB OBJ 302 MB 2.0 GB

2961. accessory

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.7	2.9	0.3 ms	2.9	0.1	0.4	0.2	7.4
Simulation, STEP	0.2	0.7	2.8	0.3 ms	2.6	2.2	0.4	0.2	9.2
Simulation, STL	0.3	0.7	2.9	0.3 ms	2.7	0.2	0.4	0.2	7.4
Simulation, OBJ	0.2	0.8	2.9	0.7 ms	2.9	3.8	0.4	0.2	11.3
Visual, GLB	0.2	0.9	2.8	0.5 ms	6.2	88 ms	0.8	0.2	11.1
Visual, OBJ	0.2	0.7	3.0	0.4 ms	6.5	3.0	0.8	0.3	14.5

Board Repo: usbarmory/usbarmory Board: accessory.kicad_pcb Folder hardware / mark-two-debug-accessory Complexity 278 / 1000 (size 213, features 65) KESE features through vias, slotted holes, filled zones, copper text, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 37, 609, 80 Triangles, simulation 714,356 in 80 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 25 MB 388 MB STEP 122 MB 480 MB STL 36 MB 397 MB OBJ 73 MB 517 MB Visual GLB 20 MB 493 MB OBJ 61 MB 496 MB

2962. armory

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.5	3.7	9.9	1 ms	13.3	0.7	2.1	0.4	31.7
Simulation, STEP	1.5	4.1	10.7	1 ms	13.4	9.6	2.0	0.3	41.6
Simulation, STL	1.5	3.9	9.7	1 ms	13.1	1.2	1.9	0.3	31.7
Simulation, OBJ	1.4	3.9	10.4	1 ms	13.9	23.3	2.3	0.3	55.5
Visual, GLB	1.6	4.0	10.0	1 ms	32.2	0.4	3.8	0.3	52.3
Visual, OBJ	1.5	4.0	10.6	1 ms	31.7	13.3	3.7	0.3	65.1

Board Repo: usbarmory/usbarmory Board: armory.kicad_pcb Folder hardware / mark-two-lan Complexity 445 / 1000 (size 320, features 125) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 6 File format KiCad 7 (20221018) Parts, tracks, vias 194, 17,001, 371 Triangles, simulation 3,979,384 in 422 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 136 MB 1.1 GB STEP 616 MB 1.4 GB STL 199 MB 1.1 GB OBJ 426 MB 2.6 GB Visual GLB 75 MB 1.4 GB OBJ 242 MB 1.7 GB

2963. armory

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.3	4.0	13.6	0.8 ms	16.6	1.0	2.4	0.3	39.2
Simulation, STEP	1.3	4.0	13.5	1 ms	16.8	10.7	2.4	0.3	49.0
Simulation, STL	1.4	4.1	13.4	1 ms	16.5	1.9	2.6	0.3	40.2
Simulation, OBJ	1.3	3.8	12.9	1.0 ms	16.5	22.5	2.7	0.4	60.2
Visual, GLB	1.4	4.0	13.0	2 ms	34.5	0.5	5.0	0.3	58.7
Visual, OBJ	1.3	3.9	13.4	1 ms	33.8	12.2	5.2	0.3	70.0

Board Repo: usbarmory/usbarmory Board: armory.kicad_pcb Folder hardware / mark-two Complexity 400 / 1000 (size 320, features 80) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 6 File format KiCad 5 (20171130) Parts, tracks, vias 180, 17,717, 431 Triangles, simulation 5,187,220 in 436 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 179 MB 1.4 GB STEP 751 MB 1.7 GB STL 259 MB 1.7 GB OBJ 559 MB 3.3 GB Visual GLB 94 MB 1.8 GB OBJ 304 MB 2.0 GB

2964. milight-hub-base

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.7	0.2 ms	0.8	35 ms	0.1	0.2	2.3
Simulation, STEP	0.1	0.2	0.7	0.3 ms	0.8	1.0	0.1	0.2	3.1
Simulation, STL	0.1	0.2	0.7	0.2 ms	0.7	47 ms	95 ms	0.2	2.0
Simulation, OBJ	0.1	0.2	0.7	0.2 ms	0.7	0.9	0.1	0.2	2.9
Visual, GLB	0.1	0.2	0.6	0.2 ms	1.7	27 ms	0.2	0.2	3.1
Visual, OBJ	0.1	0.2	0.6	0.2 ms	1.7	0.7	0.2	0.2	3.7

Board Repo: usimd/milight-hub Board: milight-hub-base.kicad_pcb Complexity 248 / 1000 (size 143, features 105) KESE features through vias, rounded, trapezoid or chamfered pads, drill offsets, filled zones, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 10 (20260206) Parts, tracks, vias 23, 110, 55 Triangles, simulation 233,428 in 36 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 8.1 MB 230 MB STEP 39 MB 249 MB STL 12 MB 239 MB OBJ 24 MB 240 MB Visual GLB 6.2 MB 208 MB OBJ 18 MB 208 MB

2965. uCM4

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.7	2.3	0.8 ms	2.6	0.1	0.5	0.2	6.7
Simulation, STEP	0.3	0.6	2.3	0.6 ms	2.5	2.2	0.5	0.2	8.6
Simulation, STL	0.3	0.6	2.3	0.5 ms	2.5	0.2	0.4	0.2	6.5
Simulation, OBJ	0.4	0.6	2.2	0.6 ms	2.8	3.5	0.5	0.2	10.2
Visual, GLB	0.3	0.6	2.3	0.5 ms	6.4	92 ms	0.7	0.2	10.6
Visual, OBJ	0.3	0.6	2.3	0.5 ms	6.2	3.1	0.7	0.2	13.5

Board Repo: v3l0c1r4pt0r/ucm4 Board: uCM4.kicad_pcb Complexity 285 / 1000 (size 175, features 110) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, drill offsets, filled zones, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 6 (20210228) Parts, tracks, vias 30, 1,280, 109 Triangles, simulation 649,970 in 177 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 23 MB 382 MB STEP 117 MB 417 MB STL 33 MB 384 MB OBJ 66 MB 473 MB Visual GLB 20 MB 533 MB OBJ 59 MB 525 MB

2966. bus_breakout

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	93 ms	0.3	1.2	0.3 ms	0.9	41 ms	0.1	0.2	2.9
Simulation, STEP	90 ms	0.3	1.2	0.2 ms	1.0	1.0	0.1	0.2	3.8
Simulation, STL	89 ms	0.3	1.2	0.2 ms	1.0	59 ms	0.1	0.2	2.9
Simulation, OBJ	96 ms	0.3	1.1	0.2 ms	0.9	1.1	0.2	0.2	3.9
Visual, GLB	97 ms	0.2	1.2	0.2 ms	2.0	21 ms	0.2	0.2	3.9
Visual, OBJ	96 ms	0.2	1.2	0.2 ms	1.9	0.6	0.2	0.2	4.4

Board Repo: vascofazza/8bit-cpu Board: bus_breakout.kicad_pcb Folder bus_breakout Complexity 124 / 1000 (size 104, features 20) KESE features copper text, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 4, 72, 0 Triangles, simulation 248,268 in 30 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 8.6 MB 227 MB STEP 43 MB 235 MB STL 12 MB 226 MB OBJ 25 MB 227 MB Visual GLB 5.1 MB 203 MB OBJ 15 MB 202 MB

2967. arduino_eeprom_programmer

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	1.1	4.4	0.3 ms	3.2	0.1	0.5	0.2	10.0
Simulation, STEP	0.6	1.0	4.4	0.2 ms	3.3	2.8	0.5	0.2	12.8
Simulation, STL	0.6	1.1	4.6	0.5 ms	3.2	0.3	0.5	0.2	10.4
Simulation, OBJ	0.6	1.0	4.4	0.3 ms	3.2	5.5	0.5	0.3	15.4
Visual, GLB	0.6	1.0	4.5	0.4 ms	7.7	0.1	1.0	0.2	15.1
Visual, OBJ	0.6	1.0	4.5	0.4 ms	7.9	3.9	1.0	0.3	19.2

Board Repo: vascofazza/8bit-cpu Board: arduino_eeprom_programmer.kicad_pcb Folder eeprom_programmer / arduino_eeprom_programmer Complexity 191 / 1000 (size 136, features 55) KESE features through vias, filled zones, copper drawings, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 8, 317, 4 Triangles, simulation 926,940 in 45 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 32 MB 418 MB STEP 177 MB 482 MB STL 46 MB 409 MB OBJ 95 MB 669 MB Visual GLB 22 MB 526 MB OBJ 64 MB 533 MB

2968. display_interface

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.0	4.2	0.6 ms	3.0	0.1	0.5	0.2	9.5
Simulation, STEP	0.4	1.0	4.0	0.3 ms	3.0	2.5	0.4	0.2	11.6
Simulation, STL	0.5	0.9	3.9	0.3 ms	3.1	0.2	0.5	0.3	9.4
Simulation, OBJ	0.6	1.1	4.2	0.3 ms	3.0	4.1	0.5	0.3	13.7
Visual, GLB	0.4	1.0	4.1	0.4 ms	7.3	94 ms	1.0	0.2	14.0
Visual, OBJ	0.5	1.0	4.5	0.3 ms	7.1	3.0	1.2	0.3	17.6

Board Repo: vascofazza/8bit-cpu Board: display_interface.kicad_pcb Folder helix_display_interface / display_interface Complexity 227 / 1000 (size 147, features 80) KESE features through vias, custom pads, filled zones, copper drawings, copper text, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 10, 554, 5 Triangles, simulation 871,560 in 43 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 31 MB 384 MB STEP 172 MB 461 MB STL 44 MB 389 MB OBJ 90 MB 636 MB Visual GLB 21 MB 483 MB OBJ 63 MB 529 MB

2969. 8bit-computer

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.6	15.3	109.1	4 ms	83.3	3.4	12.6	0.6	226.7
Simulation, STEP	2.8	15.7	112.8	3 ms	84.7	50.1	12.8	0.6	279.4
Simulation, STL	2.8	15.8	112.0	3 ms	84.4	7.6	13.0	0.6	236.3
Simulation, OBJ	3.0	16.3	114.0	2 ms	84.3	110.7	12.8	0.5	341.7
Visual, GLB	2.8	16.0	113.4	3 ms	192.7	1.7	17.2	0.4	344.2
Visual, OBJ	2.8	16.1	113.3	3 ms	195.3	60.9	17.3	0.5	406.1

Board Repo: vascofazza/8bit-cpu Board: 8bit-computer.kicad_pcb Folder MK1_CPU / 8bit-computer Complexity 387 / 1000 (size 287, features 100) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 328, 11,197, 441 Triangles, simulation 15,245,230 in 586 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 527 MB 3.5 GB STEP 2.9 GB 4.9 GB STL 762 MB 3.3 GB OBJ 1.7 GB 9.8 GB Visual GLB 328 MB 5.1 GB OBJ 1.0 GB 6.5 GB

2970. programming_interface

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	0.9	4.7	0.5 ms	3.2	0.1	0.5	0.2	10.0
Simulation, STEP	0.4	0.9	4.9	0.3 ms	3.4	2.7	0.4	0.2	13.0
Simulation, STL	0.4	1.0	4.7	0.4 ms	3.3	0.3	0.5	0.3	10.5
Simulation, OBJ	0.4	0.9	4.9	0.5 ms	3.4	4.2	0.4	0.2	14.4
Visual, GLB	0.4	1.0	5.3	0.5 ms	7.3	0.1	1.1	0.2	15.4
Visual, OBJ	0.4	1.0	5.1	0.5 ms	6.8	2.7	0.8	0.2	16.9

Board Repo: vascofazza/8bit-cpu Board: programming_interface.kicad_pcb Folder start9_programming_interface / programming_interface Complexity 247 / 1000 (size 192, features 55) KESE features through vias, filled zones, copper text, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 13, 631, 11 Triangles, simulation 1,047,248 in 48 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 36 MB 431 MB STEP 199 MB 520 MB STL 52 MB 452 MB OBJ 108 MB 749 MB Visual GLB 23 MB 578 MB OBJ 69 MB 578 MB

2971. omower

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.2	7.9	32.9	1 ms	24.3	1.3	2.9	0.4	70.9
Simulation, STEP	1.2	8.0	32.7	1 ms	24.0	15.2	2.8	0.4	84.3
Simulation, STL	1.2	7.7	34.4	1 ms	24.7	2.4	3.1	0.3	74.0
Simulation, OBJ	1.2	8.6	33.7	1 ms	25.0	34.9	3.0	0.3	106.7
Visual, GLB	1.2	7.9	33.7	1 ms	60.0	0.6	6.2	0.3	109.9
Visual, OBJ	1.3	8.1	33.2	1 ms	57.9	19.6	6.3	0.3	126.7

Board Repo: vasimv/omower Board: omower.kicad_pcb Folder hardware / OMower Complexity 337 / 1000 (size 282, features 55) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 4 File format KiCad 4 (4) Parts, tracks, vias 402, 4,619, 537 Triangles, simulation 5,924,968 in 351 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 207 MB 1.4 GB STEP 824 MB 1.9 GB STL 296 MB 1.5 GB OBJ 642 MB 3.9 GB Visual GLB 114 MB 1.8 GB OBJ 362 MB 2.5 GB

2972. BLDC_4

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.4	4.7	0.7 ms	5.2	0.3	0.8	0.3	13.1
Simulation, STEP	0.4	1.5	4.8	0.5 ms	5.1	3.5	0.8	0.3	16.4
Simulation, STL	0.5	1.4	4.6	0.7 ms	5.3	0.5	0.8	0.2	13.3
Simulation, OBJ	0.4	1.5	4.7	0.5 ms	5.2	7.5	0.7	0.2	20.3
Visual, GLB	0.4	1.3	4.6	0.6 ms	15.4	0.2	1.5	0.3	23.8
Visual, OBJ	0.4	1.5	4.9	0.8 ms	15.5	5.4	1.8	0.3	29.8

Board Repo: vedderb/bldc-hardware Board: BLDC_4.kicad_pcb Folder design Complexity 303 / 1000 (size 258, features 45) KESE features through vias, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 4 (4) Parts, tracks, vias 117, 1,671, 187 Triangles, simulation 1,473,188 in 129 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 51 MB 623 MB STEP 222 MB 636 MB STL 74 MB 620 MB OBJ 153 MB 1.0 GB Visual GLB 36 MB 702 MB OBJ 108 MB 786 MB

2973. VB-IoT1_v1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.1	4.9	13.3	0.7 ms	15.8	0.9	2.1	0.3	38.4
Simulation, STEP	1.0	4.9	13.5	1 ms	16.0	10.4	2.2	0.3	48.3
Simulation, STL	1.1	4.9	13.5	0.8 ms	16.7	1.5	2.2	0.3	40.1
Simulation, OBJ	1.0	5.1	13.7	0.7 ms	15.9	23.2	2.5	0.3	61.7
Visual, GLB	1.0	4.9	13.6	0.7 ms	41.8	0.5	5.2	0.3	67.4
Visual, OBJ	1.0	5.0	13.3	0.7 ms	39.4	17.0	5.9	0.3	81.9

Board Repo: venseytech/VB-IoT1 Board: VB-IoT1_v1.kicad_pcb Folder VB-IoT1_v1 Complexity 336 / 1000 (size 281, features 55) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 4 File format KiCad 4 (4) Parts, tracks, vias 175, 5,166, 533 Triangles, simulation 4,269,758 in 267 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 148 MB 1.3 GB STEP 710 MB 1.7 GB STL 214 MB 1.3 GB OBJ 457 MB 2.7 GB Visual GLB 111 MB 1.8 GB OBJ 350 MB 2.3 GB

2974. MicroZed_carrier_board_v4

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	3.3	9.5	1.0 ms	9.6	0.5	1.4	0.3	25.0
Simulation, STEP	0.4	3.1	9.2	1 ms	9.7	6.1	1.3	0.2	30.2
Simulation, STL	0.4	2.9	9.3	1 ms	10.1	1.1	1.4	0.2	25.5
Simulation, OBJ	0.4	3.0	8.8	1 ms	10.0	15.4	1.3	0.2	39.3
Visual, GLB	0.4	3.3	9.0	1 ms	19.6	0.3	2.7	0.2	35.5
Visual, OBJ	0.5	3.1	9.1	1 ms	19.4	7.9	3.2	0.2	43.3

Board Repo: viktor-nikolov/microzed-carrier-board Board: MicroZed_carrier_board_v4.kicad_pcb Folder KiCad_and_production_files Complexity 312 / 1000 (size 222, features 90) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 6 File format KiCad 7 (20221018) Parts, tracks, vias 91, 1,904, 296 Triangles, simulation 3,634,492 in 225 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 120 MB 995 MB STEP 370 MB 1.3 GB STL 182 MB 1.0 GB OBJ 379 MB 2.3 GB Visual GLB 63 MB 1.3 GB OBJ 197 MB 1.4 GB

2975. vimdrones_esc_development_board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.6	5.4	0.6 ms	5.5	0.3	0.7	0.3	14.3
Simulation, STEP	0.8	1.6	5.7	0.5 ms	5.7	3.8	0.6	0.2	18.4
Simulation, STL	0.4	1.4	5.0	0.4 ms	5.6	0.6	0.7	0.3	13.9
Simulation, OBJ	0.4	1.5	5.2	0.4 ms	5.3	7.7	0.6	0.2	20.9
Visual, GLB	0.4	1.5	5.4	0.4 ms	11.3	0.1	1.2	0.2	20.1
Visual, OBJ	0.5	1.5	5.5	0.4 ms	10.1	4.7	1.6	0.3	24.1

Board Repo: VimDrones/AM32_esc_development_board Board: vimdrones_esc_development_board.kicad_pcb Complexity 366 / 1000 (size 241, features 125) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 82, 650, 292 Triangles, simulation 1,569,380 in 81 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 53 MB 564 MB STEP 211 MB 712 MB STL 78 MB 564 MB OBJ 161 MB 1.0 GB Visual GLB 32 MB 682 MB OBJ 96 MB 740 MB

2976. Tangenta

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.2	8.9	35.3	5 ms	63.1	1.8	4.9	0.3	116.6
Simulation, STEP	2.1	8.7	35.1	3 ms	62.5	26.2	4.9	0.4	139.7
Simulation, STL	2.2	8.7	33.4	3 ms	63.8	3.7	5.3	0.4	117.6
Simulation, OBJ	2.2	8.9	34.8	3 ms	62.4	62.7	5.3	0.4	176.8
Visual, GLB	2.3	8.9	35.0	3 ms	89.0	1.1	10.2	0.3	146.9
Visual, OBJ	2.2	9.1	35.3	3 ms	93.0	36.1	12.0	0.3	188.0

Board Repo: vmetodiev/tangenta Board: Tangenta.kicad_pcb Folder Tangenta Complexity 395 / 1000 (size 295, features 100) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 559, 7,736, 1,128 Triangles, simulation 10,448,246 in 1043 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 345 MB 2.8 GB STEP 1.3 GB 3.6 GB STL 522 MB 2.8 GB OBJ 1.1 GB 6.5 GB Visual GLB 219 MB 3.5 GB OBJ 719 MB 4.3 GB

2977. CM4_MATX

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	2.2	12.2	1 ms	11.0	0.4	1.1	0.3	27.7
Simulation, STEP	0.3	2.2	12.1	2 ms	11.4	7.4	1.2	0.3	34.9
Simulation, STL	0.4	2.2	11.9	2 ms	11.7	0.9	1.1	0.3	28.4
Simulation, OBJ	0.3	2.2	11.6	2 ms	11.2	13.9	1.1	0.3	40.7
Visual, GLB	0.3	2.1	11.8	2 ms	19.7	0.2	1.8	0.2	36.1
Visual, OBJ	0.4	2.3	12.0	2 ms	20.1	7.6	2.1	0.2	44.8

Board Repo: volkertb/CM4_MATX Board: CM4_MATX.kicad_pcb Folder KiCad Complexity 111 / 1000 (size 101, features 10) KESE features curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 31, 0, 0 Triangles, simulation 2,451,152 in 596 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 80 MB 747 MB STEP 273 MB 987 MB STL 123 MB 741 MB OBJ 259 MB 1.6 GB Visual GLB 46 MB 996 MB OBJ 142 MB 1.1 GB

2978. altair-8800b-cpu-card

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	3.2	14.4	2 ms	12.5	0.7	1.7	0.3	33.4
Simulation, STEP	0.6	2.9	14.4	1 ms	12.2	8.7	1.7	0.3	40.7
Simulation, STL	0.6	2.9	13.6	1 ms	12.5	1.1	1.6	0.3	32.6
Simulation, OBJ	0.6	2.9	14.3	1 ms	12.5	20.2	1.8	0.3	52.5
Visual, GLB	0.6	3.0	14.4	1 ms	24.5	0.3	2.8	0.2	45.8
Visual, OBJ	0.6	2.9	14.1	1 ms	24.4	11.9	3.3	0.2	57.4

Board Repo: warmech/altair-8800b-cpu-card Board: altair-8800b-cpu-card.kicad_pcb Folder cad Complexity 261 / 1000 (size 201, features 60) KESE features through vias, filled zones, curved board outline, TrueType text Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 136, 2,087, 314 Triangles, simulation 3,660,442 in 245 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 123 MB 1.2 GB STEP 486 MB 1.5 GB STL 183 MB 1.2 GB OBJ 382 MB 3.0 GB Visual GLB 75 MB 1.4 GB OBJ 236 MB 2.0 GB

2979. altair-8800b-display-control-pcb

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	5.4	26.3	2 ms	23.1	0.9	4.1	0.3	60.8
Simulation, STEP	0.7	5.5	27.4	2 ms	23.2	15.3	4.2	0.3	76.6
Simulation, STL	0.8	5.3	26.5	2 ms	23.2	2.1	4.7	0.4	62.9
Simulation, OBJ	0.8	5.6	26.7	2 ms	23.7	31.5	3.9	0.4	92.5
Visual, GLB	0.8	5.2	27.1	3 ms	51.7	0.5	7.0	0.3	92.5
Visual, OBJ	0.8	5.1	26.6	2 ms	49.0	17.2	7.5	0.3	106.7

Board Repo: warmech/altair-8800b-display-control-pcb Board: altair-8800b-display-control-pcb.kicad_pcb Folder cad Complexity 250 / 1000 (size 215, features 35) KESE features through vias, slotted holes, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 231, 3,782, 372 Triangles, simulation 5,441,458 in 443 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 182 MB 1.5 GB STEP 841 MB 2.1 GB STL 272 MB 1.5 GB OBJ 572 MB 4.5 GB Visual GLB 112 MB 1.9 GB OBJ 358 MB 2.2 GB

2980. lisa-2mb-ram-card

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.9	5.9	19.6	1.0 ms	20.1	1.1	3.5	0.4	51.5
Simulation, STEP	1.0	5.9	20.2	1 ms	21.2	13.1	3.9	0.4	65.6
Simulation, STL	1.0	6.2	21.1	1 ms	20.6	2.4	3.7	0.4	55.4
Simulation, OBJ	0.9	6.0	20.9	2 ms	21.8	34.5	3.4	0.4	87.8
Visual, GLB	0.9	5.9	20.0	2 ms	40.0	0.5	5.6	0.3	73.1
Visual, OBJ	0.9	6.1	21.1	2 ms	38.4	13.5	5.2	0.3	85.5

Board Repo: warmech/lisa-2mb-ram-card Board: lisa-2mb-ram-card.kicad_pcb Folder cad Complexity 288 / 1000 (size 213, features 75) KESE features through vias, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 74, 2,945, 150 Triangles, simulation 5,930,502 in 242 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 200 MB 1.5 GB STEP 693 MB 1.9 GB STL 297 MB 1.4 GB OBJ 632 MB 3.7 GB Visual GLB 88 MB 1.6 GB OBJ 281 MB 2.0 GB

2981. cpu-card

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	3.8	12.9	51.9	2 ms	53.2	3.1	8.0	0.5	133.4
Simulation, STEP	3.9	12.5	50.7	2 ms	53.4	37.3	7.6	0.6	166.0
Simulation, STL	3.9	12.5	51.5	2 ms	53.9	5.9	7.7	0.6	136.0
Simulation, OBJ	3.8	13.0	52.7	3 ms	54.3	99.6	7.9	0.6	231.9
Visual, GLB	4.0	12.4	51.0	2 ms	116.6	1.3	10.5	0.5	196.3
Visual, OBJ	4.6	13.8	54.2	3 ms	124.5	46.8	11.2	0.5	255.5

Board Repo: warmech/lisa-cpu-card Board: cpu-card.kicad_pcb Folder cad Complexity 397 / 1000 (size 242, features 155) KESE features through vias, custom pads, arc tracks, filled zones, copper drawings, copper text, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 140, 9,460, 1,038 Triangles, simulation 14,992,174 in 395 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 515 MB 3.6 GB STEP 2.1 GB 4.3 GB STL 750 MB 3.5 GB OBJ 1.6 GB 9.5 GB Visual GLB 252 MB 4.2 GB OBJ 830 MB 5.4 GB

2982. altimeter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	1.5	5.7	0.5 ms	6.6	0.3	0.9	0.2	15.9
Simulation, STEP	0.6	1.6	5.7	0.6 ms	6.6	5.5	0.9	0.2	21.0
Simulation, STL	0.6	1.5	5.6	0.5 ms	6.4	0.5	0.8	0.2	15.7
Simulation, OBJ	0.6	1.6	5.7	0.4 ms	6.7	10.6	0.9	0.2	26.3
Visual, GLB	0.6	1.8	5.7	0.5 ms	15.3	0.2	1.9	0.2	25.7
Visual, OBJ	0.6	1.7	5.9	0.5 ms	14.7	7.6	1.8	0.3	32.6

Board Repo: waterloo-rocketry/canhw Board: altimeter.kicad_pcb Folder altimeter Complexity 374 / 1000 (size 249, features 125) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 137, 1,234, 161 Triangles, simulation 1,893,396 in 162 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 64 MB 731 MB STEP 283 MB 849 MB STL 95 MB 705 MB OBJ 196 MB 1.3 GB Visual GLB 46 MB 868 MB OBJ 140 MB 979 MB

2983. camera

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.9	2.7	0.8 ms	4.0	0.2	0.7	0.3	9.0
Simulation, STEP	0.4	1.0	2.5	0.5 ms	3.9	3.1	0.6	0.2	11.7
Simulation, STL	0.4	0.9	2.5	0.5 ms	3.9	0.3	0.6	0.2	8.8
Simulation, OBJ	0.3	0.9	2.6	0.5 ms	3.9	5.9	0.6	0.2	14.5
Visual, GLB	0.4	0.9	2.7	0.5 ms	8.5	0.1	1.0	0.3	13.8
Visual, OBJ	0.4	0.9	2.7	0.5 ms	8.7	4.4	1.0	0.2	18.3

Board Repo: waterloo-rocketry/canhw Board: camera.kicad_pcb Folder camera Complexity 334 / 1000 (size 234, features 100) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 58, 754, 165 Triangles, simulation 1,060,698 in 133 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 36 MB 457 MB STEP 147 MB 576 MB STL 53 MB 457 MB OBJ 107 MB 729 MB Visual GLB 26 MB 694 MB OBJ 77 MB 653 MB

2984. camera_interface_CAN_board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.6	1.8	0.4 ms	2.1	97 ms	0.3	0.2	5.3
Simulation, STEP	0.3	0.5	1.7	0.3 ms	2.1	2.1	0.3	0.2	7.2
Simulation, STL	0.3	0.5	1.8	0.2 ms	2.2	0.2	0.4	0.3	5.5
Simulation, OBJ	0.3	0.5	1.8	0.3 ms	2.1	3.1	0.3	0.2	8.3
Visual, GLB	0.3	0.5	1.7	0.3 ms	5.3	71 ms	0.6	0.2	8.7
Visual, OBJ	0.3	0.6	1.7	0.5 ms	5.3	2.1	0.7	0.2	10.8

Board Repo: waterloo-rocketry/canhw Board: camera_interface_CAN_board.kicad_pcb Folder camera_interface_CAN_board Complexity 275 / 1000 (size 175, features 100) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 10 (20260206) Parts, tracks, vias 44, 248, 67 Triangles, simulation 646,922 in 67 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 22 MB 359 MB STEP 101 MB 413 MB STL 32 MB 375 MB OBJ 65 MB 481 MB Visual GLB 16 MB 417 MB OBJ 47 MB 413 MB

2985. CAN_relay

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.6	2.1	0.4 ms	2.9	0.1	0.4	0.3	6.8
Simulation, STEP	0.2	0.6	2.1	0.4 ms	2.8	2.5	0.4	0.2	8.9
Simulation, STL	0.3	0.6	2.3	0.4 ms	2.8	0.3	0.4	0.2	6.9
Simulation, OBJ	0.2	0.6	2.1	0.4 ms	3.0	3.9	0.4	0.2	10.4
Visual, GLB	0.3	0.6	2.2	0.5 ms	6.4	93 ms	0.9	0.2	10.8
Visual, OBJ	0.3	0.6	2.3	0.3 ms	6.5	2.6	0.9	0.2	13.4

Board Repo: waterloo-rocketry/canhw Board: CAN_relay.kicad_pcb Folder CAN_relay Complexity 318 / 1000 (size 218, features 100) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 10 (20260206) Parts, tracks, vias 46, 314, 79 Triangles, simulation 820,192 in 132 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 28 MB 389 MB STEP 122 MB 479 MB STL 41 MB 393 MB OBJ 82 MB 612 MB Visual GLB 20 MB 520 MB OBJ 60 MB 526 MB

2986. AD_Breakout

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.4	1.2	0.2 ms	1.6	77 ms	0.3	0.3	4.0
Simulation, STEP	0.2	0.4	1.2	0.2 ms	1.6	1.6	0.2	0.2	5.5
Simulation, STL	0.2	0.4	1.2	0.3 ms	1.6	0.1	0.3	0.3	4.1
Simulation, OBJ	0.2	0.4	1.2	0.3 ms	1.6	2.1	0.2	0.3	6.1
Visual, GLB	0.2	0.4	1.2	0.2 ms	3.1	48 ms	0.3	0.3	5.5
Visual, OBJ	0.2	0.4	1.1	0.2 ms	3.3	1.5	0.3	0.3	7.1

Board Repo: waterloo-rocketry/canhw Board: AD_Breakout.kicad_pcb Folder CanardBoard / AD_Breakout_Board Complexity 259 / 1000 (size 174, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 10th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 39, 268, 61 Triangles, simulation 352,802 in 48 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 12 MB 257 MB STEP 47 MB 293 MB STL 18 MB 255 MB OBJ 35 MB 267 MB Visual GLB 8.6 MB 275 MB OBJ 25 MB 274 MB

2987. CanardBoard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.7	6.7	18.4	0.9 ms	20.6	1.1	3.0	0.3	51.9
Simulation, STEP	1.6	6.6	17.8	0.9 ms	20.0	11.7	2.8	0.3	60.9
Simulation, STL	1.6	6.3	17.5	1 ms	20.7	2.1	3.0	0.3	51.6
Simulation, OBJ	1.6	6.0	17.8	1 ms	20.3	36.2	2.9	0.4	85.3
Visual, GLB	1.5	6.1	17.7	2 ms	57.4	0.4	3.9	0.3	87.4
Visual, OBJ	1.5	6.0	17.9	0.9 ms	60.8	16.6	3.7	0.3	106.7

Board Repo: waterloo-rocketry/canhw Board: CanardBoard.kicad_pcb Folder CanardBoard Complexity 417 / 1000 (size 282, features 135) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 253, 2,085, 863 Triangles, simulation 6,007,234 in 258 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 200 MB 1.4 GB STEP 567 MB 1.9 GB STL 300 MB 1.4 GB OBJ 645 MB 3.8 GB Visual GLB 95 MB 1.9 GB OBJ 309 MB 2.1 GB

2988. DAQ CAN support

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.4	2.1	0.3 ms	2.0	81 ms	0.3	0.2	5.3
Simulation, STEP	0.2	0.4	2.1	0.2 ms	2.0	1.7	0.3	0.2	6.8
Simulation, STL	0.2	0.3	2.1	0.3 ms	1.9	0.1	0.3	0.2	5.1
Simulation, OBJ	0.2	0.4	1.9	0.4 ms	1.9	2.4	0.3	0.2	7.3
Visual, GLB	0.2	0.3	1.8	0.3 ms	3.4	59 ms	0.4	0.2	6.4
Visual, OBJ	0.2	0.3	1.9	0.3 ms	3.6	1.5	0.4	0.2	8.1

Board Repo: waterloo-rocketry/canhw Board: DAQ CAN support.kicad_pcb Folder DAQ CAN support Complexity 219 / 1000 (size 149, features 70) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 33, 247, 20 Triangles, simulation 506,750 in 46 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 17 MB 305 MB STEP 82 MB 367 MB STL 25 MB 305 MB OBJ 51 MB 396 MB Visual GLB 12 MB 388 MB OBJ 37 MB 353 MB

2989. gps_2

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.6	2.2	0.3 ms	2.3	91 ms	0.3	0.3	6.1
Simulation, STEP	0.2	0.6	2.2	0.4 ms	2.3	2.0	0.3	0.2	7.9
Simulation, STL	0.2	0.6	2.2	0.4 ms	2.3	0.1	0.4	0.2	6.0
Simulation, OBJ	0.2	0.7	2.2	0.3 ms	2.4	3.4	0.3	0.3	9.6
Visual, GLB	0.3	0.6	2.2	0.4 ms	5.3	76 ms	0.6	0.3	9.3
Visual, OBJ	0.2	0.6	2.2	0.4 ms	5.2	2.7	0.6	0.2	11.8

Board Repo: waterloo-rocketry/canhw Board: gps_2.kicad_pcb Folder gps Complexity 254 / 1000 (size 164, features 90) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 37, 264, 151 Triangles, simulation 566,746 in 57 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 20 MB 354 MB STEP 93 MB 410 MB STL 28 MB 337 MB OBJ 58 MB 429 MB Visual GLB 16 MB 415 MB OBJ 49 MB 429 MB

2990. injector_sensor_hub

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.5	2.2	0.3 ms	2.3	0.1	0.4	0.2	6.0
Simulation, STEP	0.3	0.6	2.3	0.3 ms	2.2	2.2	0.4	0.2	8.2
Simulation, STL	0.3	0.7	2.3	0.3 ms	2.4	0.3	0.4	0.3	6.6
Simulation, OBJ	0.3	0.6	2.2	0.3 ms	2.4	3.3	0.4	0.3	9.4
Visual, GLB	0.3	0.6	2.5	0.4 ms	5.5	75 ms	0.5	0.3	9.7
Visual, OBJ	0.3	0.5	2.6	0.5 ms	5.0	2.8	0.7	0.2	12.3

Board Repo: waterloo-rocketry/canhw Board: injector_sensor_hub.kicad_pcb Folder injector_sensor_hub Complexity 215 / 1000 (size 160, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 48, 278, 68 Triangles, simulation 650,724 in 58 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 22 MB 337 MB STEP 113 MB 401 MB STL 33 MB 330 MB OBJ 66 MB 472 MB Visual GLB 17 MB 425 MB OBJ 51 MB 468 MB

2991. telemetry_transmitter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	0.8	4.4	0.5 ms	2.9	0.2	0.4	0.3	9.5
Simulation, STEP	0.3	0.7	4.3	0.5 ms	3.1	2.8	0.4	0.3	11.9
Simulation, STL	0.4	0.7	4.5	0.6 ms	2.9	0.2	0.4	0.2	9.3
Simulation, OBJ	0.3	0.7	4.2	0.6 ms	3.0	4.9	0.5	0.3	13.9
Visual, GLB	0.3	0.7	4.5	0.7 ms	7.2	0.1	0.7	0.3	13.8
Visual, OBJ	0.3	0.7	4.5	0.5 ms	6.9	3.2	0.7	0.3	16.6

Board Repo: waterloo-rocketry/canhw Board: telemetry_transmitter.kicad_pcb Folder live_telemetry / ARCHIVE / old_telemetry_transmitter Complexity 232 / 1000 (size 162, features 70) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline Tested 10th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 46, 305, 88 Triangles, simulation 758,176 in 67 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 26 MB 369 MB STEP 139 MB 431 MB STL 38 MB 381 MB OBJ 78 MB 542 MB Visual GLB 18 MB 438 MB OBJ 54 MB 450 MB

2992. LTT

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	3.5	9.0	0.4 ms	10.6	0.5	1.2	0.3	25.7
Simulation, STEP	0.7	3.4	8.7	0.3 ms	10.8	5.4	1.1	0.4	30.5
Simulation, STL	0.7	3.8	9.3	1.0 ms	11.1	1.0	1.2	0.4	27.4
Simulation, OBJ	0.6	3.3	8.6	0.5 ms	10.6	15.4	1.2	0.4	40.1
Visual, GLB	0.7	3.4	9.4	0.4 ms	21.0	0.3	2.2	0.3	37.3
Visual, OBJ	0.6	3.2	8.6	0.9 ms	20.9	8.5	2.2	0.3	44.2

Board Repo: waterloo-rocketry/canhw Board: LTT.kicad_pcb Folder live_telemetry / LTT Complexity 353 / 1000 (size 253, features 100) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 10th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 100, 545, 705 Triangles, simulation 2,420,870 in 95 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 82 MB 946 MB STEP 221 MB 1.2 GB STL 121 MB 1.1 GB OBJ 252 MB 1.6 GB Visual GLB 47 MB 889 MB OBJ 145 MB 1.0 GB

2993. power-splitter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.3	1.2	0.1 ms	0.9	32 ms	89 ms	0.2	2.9
Simulation, STEP	0.1	0.3	1.2	0.1 ms	0.9	0.9	90 ms	0.2	3.7
Simulation, STL	0.1	0.3	1.2	0.1 ms	0.8	46 ms	86 ms	0.2	2.8
Simulation, OBJ	0.1	0.3	1.1	0.1 ms	0.9	1.1	94 ms	0.2	3.9
Visual, GLB	0.1	0.3	1.2	0.2 ms	1.7	23 ms	0.2	0.2	3.8
Visual, OBJ	0.1	0.3	1.1	0.2 ms	1.8	0.7	0.1	0.2	4.4

Board Repo: waterloo-rocketry/canhw Board: power-splitter.kicad_pcb Folder live_telemetry / power-splitter Complexity 234 / 1000 (size 139, features 95) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 7, 9, 140 Triangles, simulation 198,584 in 14 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 6.8 MB 223 MB STEP 15 MB 238 MB STL 9.9 MB 226 MB OBJ 20 MB 223 MB Visual GLB 4.7 MB 201 MB OBJ 14 MB 205 MB

2994. novatel_gps_breakout

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.2	1.3	0.2 ms	1.1	54 ms	0.2	0.2	3.3
Simulation, STEP	0.1	0.2	1.3	0.2 ms	1.2	1.2	0.2	0.2	4.5
Simulation, STL	0.2	0.3	1.3	0.3 ms	1.1	80 ms	0.2	0.3	3.4
Simulation, OBJ	0.2	0.3	1.3	0.2 ms	1.1	1.7	0.2	0.2	5.0
Visual, GLB	0.2	0.2	1.3	0.2 ms	2.6	35 ms	0.3	0.3	4.8
Visual, OBJ	0.2	0.3	1.4	0.2 ms	2.7	1.2	0.2	0.2	6.1

Board Repo: waterloo-rocketry/canhw Board: novatel_gps_breakout.kicad_pcb Folder novatel_gps_breakout Complexity 188 / 1000 (size 118, features 70) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones Tested 10th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 7, 119, 2 Triangles, simulation 317,818 in 35 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 11 MB 239 MB STEP 48 MB 268 MB STL 16 MB 251 MB OBJ 31 MB 260 MB Visual GLB 7.0 MB 238 MB OBJ 20 MB 235 MB

2995. picdev

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.6	4.3	0.3 ms	3.1	0.1	0.4	0.2	8.9
Simulation, STEP	0.2	0.6	4.0	0.4 ms	3.2	2.4	0.4	0.2	11.0
Simulation, STL	0.2	0.6	4.2	0.3 ms	3.1	0.2	0.4	0.2	9.0
Simulation, OBJ	0.2	0.6	4.1	0.4 ms	3.1	4.2	0.4	0.3	12.8
Visual, GLB	0.2	0.6	4.1	0.5 ms	6.8	88 ms	0.9	0.2	12.9
Visual, OBJ	0.2	0.6	4.0	0.4 ms	6.8	2.8	0.8	0.2	15.3

Board Repo: waterloo-rocketry/canhw Board: picdev.kicad_pcb Folder picdev / picdev Complexity 185 / 1000 (size 150, features 35) KESE features through vias, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 45, 239, 12 Triangles, simulation 994,038 in 72 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 34 MB 449 MB STEP 182 MB 505 MB STL 50 MB 446 MB OBJ 102 MB 704 MB Visual GLB 22 MB 548 MB OBJ 64 MB 558 MB

2996. processor

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.0	3.0	0.4 ms	3.6	0.2	0.5	0.2	8.9
Simulation, STEP	0.3	0.9	2.9	0.4 ms	3.6	3.0	0.4	0.2	11.5
Simulation, STL	0.3	0.9	3.1	0.3 ms	3.7	0.5	0.5	0.2	9.3
Simulation, OBJ	0.4	0.9	3.0	0.4 ms	3.6	5.2	0.5	0.3	13.9
Visual, GLB	0.4	1.0	3.0	0.7 ms	8.9	0.1	1.2	0.2	14.8
Visual, OBJ	0.4	1.0	3.4	0.4 ms	8.8	3.9	1.4	0.2	19.0

Board Repo: waterloo-rocketry/canhw Board: processor.kicad_pcb Folder processor Complexity 352 / 1000 (size 237, features 115) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 63, 1,009, 121 Triangles, simulation 1,275,614 in 130 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 44 MB 489 MB STEP 183 MB 593 MB STL 64 MB 521 MB OBJ 131 MB 902 MB Visual GLB 31 MB 680 MB OBJ 94 MB 722 MB

2997. PropulsionBoard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.0	4.4	0.4 ms	4.0	0.2	0.5	0.3	10.7
Simulation, STEP	0.4	1.0	4.3	0.3 ms	4.3	3.7	0.5	0.2	14.4
Simulation, STL	0.4	1.0	4.4	0.3 ms	4.0	0.4	0.5	0.3	11.0
Simulation, OBJ	0.4	1.0	4.4	0.4 ms	4.1	6.0	0.5	0.3	16.6
Visual, GLB	0.5	1.0	4.4	0.3 ms	9.3	0.1	1.0	0.3	16.7
Visual, OBJ	0.4	1.1	4.5	0.3 ms	9.4	5.0	1.3	0.2	21.8

Board Repo: waterloo-rocketry/canhw Board: PropulsionBoard.kicad_pcb Folder PropulsionBoard Complexity 237 / 1000 (size 182, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 10th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 86, 851, 138 Triangles, simulation 1,003,706 in 76 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 35 MB 480 MB STEP 178 MB 591 MB STL 50 MB 496 MB OBJ 102 MB 693 MB Visual GLB 29 MB 696 MB OBJ 86 MB 758 MB

2998. remote_arming

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.9	2.6	0.4 ms	2.8	0.1	0.4	0.2	7.4
Simulation, STEP	0.3	0.8	2.5	0.4 ms	2.8	2.5	0.4	0.2	9.5
Simulation, STL	0.3	0.8	2.6	0.4 ms	3.0	0.3	0.4	0.2	7.7
Simulation, OBJ	0.3	0.8	2.6	0.4 ms	2.9	4.6	0.5	0.2	11.9
Visual, GLB	0.3	0.9	2.7	0.5 ms	6.8	0.1	0.7	0.2	11.7
Visual, OBJ	0.3	0.8	2.8	0.5 ms	7.2	2.8	0.7	0.2	14.8

Board Repo: waterloo-rocketry/canhw Board: remote_arming.kicad_pcb Folder remote_arming Complexity 300 / 1000 (size 190, features 110) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 65, 441, 140 Triangles, simulation 1,057,408 in 71 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 36 MB 461 MB STEP 138 MB 531 MB STL 53 MB 468 MB OBJ 107 MB 719 MB Visual GLB 23 MB 519 MB OBJ 69 MB 576 MB

2999. rocket_power_board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.8	2.9	0.4 ms	3.3	0.2	0.5	0.2	8.2
Simulation, STEP	0.3	0.8	3.0	0.4 ms	3.3	2.7	0.5	0.2	10.7
Simulation, STL	0.3	0.8	2.9	0.5 ms	3.3	0.2	0.5	0.2	8.3
Simulation, OBJ	0.3	0.9	3.0	0.3 ms	3.3	5.2	0.4	0.2	13.4
Visual, GLB	0.3	0.8	2.9	0.4 ms	6.7	0.1	0.6	0.2	11.7
Visual, OBJ	0.4	0.9	2.9	0.5 ms	6.6	3.6	0.6	0.2	15.2

Board Repo: waterloo-rocketry/canhw Board: rocket_power_board.kicad_pcb Folder rocket_power_board Complexity 294 / 1000 (size 194, features 100) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 83, 553, 136 Triangles, simulation 1,134,474 in 71 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 39 MB 472 MB STEP 167 MB 577 MB STL 57 MB 487 MB OBJ 115 MB 805 MB Visual GLB 26 MB 616 MB OBJ 79 MB 637 MB

3000. usbdbg

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.4	1.6	0.2 ms	1.8	66 ms	0.3	0.3	4.7
Simulation, STEP	0.2	0.4	1.6	0.3 ms	1.8	1.8	0.2	0.2	6.3
Simulation, STL	0.2	0.4	1.6	0.5 ms	1.9	0.1	0.2	0.2	4.6
Simulation, OBJ	0.2	0.4	1.7	0.4 ms	1.9	2.4	0.2	0.2	7.0
Visual, GLB	0.2	0.4	1.6	0.4 ms	4.2	73 ms	0.4	0.2	7.1
Visual, OBJ	0.2	0.4	1.6	0.2 ms	4.0	1.9	0.5	0.2	8.8

Board Repo: waterloo-rocketry/canhw Board: usbdbg.kicad_pcb Folder usbdbg Complexity 247 / 1000 (size 152, features 95) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 10 (20260206) Parts, tracks, vias 31, 252, 42 Triangles, simulation 440,540 in 54 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 15 MB 281 MB STEP 74 MB 327 MB STL 22 MB 282 MB OBJ 44 MB 322 MB Visual GLB 12 MB 340 MB OBJ 35 MB 340 MB

3001. Driverino-Shield

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.7	3.2	0.4 ms	2.8	0.1	0.4	0.4	7.8
Simulation, STEP	0.2	0.6	3.1	0.4 ms	2.6	2.2	0.4	0.2	9.4
Simulation, STL	0.3	0.5	2.8	0.4 ms	2.6	0.2	0.4	0.2	7.1
Simulation, OBJ	0.3	0.5	3.0	0.4 ms	2.8	3.5	0.4	0.2	10.8
Visual, GLB	0.3	0.6	2.9	0.4 ms	5.5	0.1	0.7	0.2	10.2
Visual, OBJ	0.3	0.6	3.0	0.5 ms	5.7	2.7	0.7	0.2	13.2

Board Repo: weirdgyn/Driverino-Shield Board: Driverino-Shield.kicad_pcb Folder PCB Complexity 241 / 1000 (size 196, features 45) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 52, 229, 45 Triangles, simulation 743,350 in 58 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 25 MB 372 MB STEP 120 MB 455 MB STL 37 MB 360 MB OBJ 75 MB 551 MB Visual GLB 18 MB 458 MB OBJ 53 MB 442 MB

3002. FourThirdsEye

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	3.1	10.9	0.7 ms	9.3	0.4	1.0	0.2	25.8
Simulation, STEP	0.6	3.2	10.9	0.3 ms	9.6	4.9	1.0	0.3	30.6
Simulation, STL	0.7	3.1	11.3	0.8 ms	9.8	0.7	0.9	0.3	26.8
Simulation, OBJ	0.6	2.9	10.8	0.3 ms	9.9	14.9	0.9	0.3	40.3
Visual, GLB	0.6	3.1	10.7	0.4 ms	24.5	0.2	2.1	0.3	41.4
Visual, OBJ	0.7	3.2	10.5	0.4 ms	23.8	8.9	2.6	0.3	49.9

Board Repo: will127534/FourThirdsEye Board: FourThirdsEye.kicad_pcb Complexity 341 / 1000 (size 216, features 125) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 107, 634, 836 Triangles, simulation 2,604,862 in 89 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 85 MB 1.0 GB STEP 244 MB 1.2 GB STL 130 MB 961 MB OBJ 269 MB 1.7 GB Visual GLB 54 MB 1.0 GB OBJ 166 MB 1.2 GB

3003. IMUArray_BreakoutBoard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.3	0.9	0.3 ms	1.0	47 ms	0.1	0.2	2.8
Simulation, STEP	0.2	0.4	0.9	0.2 ms	0.9	1.0	0.1	0.2	3.8
Simulation, STL	0.1	0.4	1.0	0.2 ms	0.9	68 ms	0.2	0.2	2.8
Simulation, OBJ	0.1	0.3	0.9	0.2 ms	1.0	1.5	0.2	0.2	4.1
Visual, GLB	0.1	0.3	1.0	0.2 ms	2.1	29 ms	0.3	0.2	4.0
Visual, OBJ	0.1	0.3	1.0	0.2 ms	2.1	1.0	0.2	0.2	4.9

Board Repo: will127534/IMU_Array Board: IMUArray_BreakoutBoard.kicad_pcb Folder IMUArray_BreakoutBoard Complexity 240 / 1000 (size 145, features 95) KESE features through vias, rounded, trapezoid or chamfered pads, drill offsets, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 6 (20211014) Parts, tracks, vias 6, 54, 65 Triangles, simulation 316,704 in 48 parts Note panel Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 11 MB 269 MB STEP 39 MB 278 MB STL 16 MB 262 MB OBJ 32 MB 266 MB Visual GLB 7.0 MB 235 MB OBJ 20 MB 234 MB

3004. IMUArray_ProcessingBoard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	2.7	7.1	0.4 ms	9.3	0.3	0.8	0.3	21.0
Simulation, STEP	0.5	2.7	6.9	0.5 ms	9.2	3.7	0.8	0.2	24.0
Simulation, STL	0.4	2.7	6.7	0.3 ms	8.3	0.6	0.8	0.3	19.9
Simulation, OBJ	0.4	2.6	6.9	0.3 ms	8.5	11.2	0.7	0.3	30.6
Visual, GLB	0.5	2.6	6.6	0.5 ms	12.5	0.2	1.5	0.2	24.0
Visual, OBJ	0.4	2.5	6.5	0.8 ms	12.8	6.7	1.6	0.2	30.7

Board Repo: will127534/IMU_Array Board: IMUArray_ProcessingBoard.kicad_pcb Folder IMUArray_ProcessingBoard / IMUArray_ProcessingBoard Complexity 338 / 1000 (size 253, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 85, 390, 880 Triangles, simulation 2,049,144 in 124 parts Note panel Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 65 MB 868 MB STEP 147 MB 988 MB STL 102 MB 887 MB OBJ 208 MB 1.4 GB Visual GLB 44 MB 827 MB OBJ 134 MB 942 MB

3005. IMUArray_SensorBoard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.2	3.4	10.9	2 ms	13.3	0.9	1.7	0.3	31.7
Simulation, STEP	1.2	3.5	10.6	0.5 ms	13.5	8.0	1.4	0.3	38.5
Simulation, STL	1.0	3.1	10.8	0.5 ms	13.5	1.0	1.5	0.3	31.1
Simulation, OBJ	1.0	3.2	10.6	0.9 ms	14.1	19.4	1.5	0.3	50.2
Visual, GLB	1.0	3.0	11.1	1 ms	34.0	0.2	2.8	0.3	52.4
Visual, OBJ	1.1	3.2	11.4	0.5 ms	35.0	8.4	3.5	0.3	62.8

Board Repo: will127534/IMU_Array Board: IMUArray_SensorBoard.kicad_pcb Folder IMUArray_SensorBoard Complexity 353 / 1000 (size 268, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 6 File format KiCad 6 (20211014) Parts, tracks, vias 148, 1,177, 558 Triangles, simulation 3,916,240 in 97 parts Note panel Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 132 MB 1.1 GB STEP 509 MB 1.3 GB STL 196 MB 1.0 GB OBJ 429 MB 2.6 GB Visual GLB 62 MB 1.3 GB OBJ 200 MB 1.5 GB

3006. CM4ClusterHat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.1	4.4	13.6	2 ms	19.5	0.7	2.0	0.3	41.5
Simulation, STEP	1.2	4.4	13.4	2 ms	19.6	9.7	1.9	0.3	50.6
Simulation, STL	1.2	4.5	13.2	2 ms	19.1	1.3	1.9	0.3	41.6
Simulation, OBJ	1.1	4.5	13.4	1 ms	19.2	17.6	1.8	0.3	57.8
Visual, GLB	1.2	4.5	12.9	0.9 ms	34.7	0.5	4.6	0.2	58.5
Visual, OBJ	1.2	4.1	13.3	0.9 ms	35.2	12.7	5.0	0.3	71.6

Board Repo: will127534/Miniature-CM4-Cluster Board: CM4ClusterHat.kicad_pcb Folder ClusterHat Complexity 377 / 1000 (size 277, features 100) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 6 (20210925) Parts, tracks, vias 236, 2,332, 758 Triangles, simulation 3,694,372 in 401 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 125 MB 1.2 GB STEP 514 MB 1.6 GB STL 185 MB 1.1 GB OBJ 393 MB 2.4 GB Visual GLB 88 MB 1.4 GB OBJ 278 MB 1.8 GB

3007. CM4Card

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.2	4.5	0.8 ms	5.0	0.2	0.8	0.2	12.4
Simulation, STEP	0.5	1.4	4.5	0.8 ms	4.6	3.3	0.6	0.2	15.0
Simulation, STL	0.4	1.2	4.4	0.7 ms	4.5	0.3	0.6	0.2	11.8
Simulation, OBJ	0.5	1.2	4.4	0.8 ms	4.4	5.4	0.6	0.2	16.7
Visual, GLB	0.4	1.1	4.4	0.7 ms	10.5	0.1	1.3	0.2	18.0
Visual, OBJ	0.4	1.2	4.7	0.8 ms	10.7	4.2	1.4	0.3	22.9

Board Repo: will127534/Miniature-CM4-Cluster Board: CM4Card.kicad_pcb Folder CM4Card Complexity 288 / 1000 (size 198, features 90) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 6 (20210925) Parts, tracks, vias 54, 822, 252 Triangles, simulation 1,208,432 in 246 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 41 MB 516 MB STEP 190 MB 629 MB STL 60 MB 504 MB OBJ 124 MB 831 MB Visual GLB 30 MB 643 MB OBJ 91 MB 733 MB

3008. OneInchEye

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.8	5.8	0.8 ms	5.3	0.3	0.6	0.2	14.5
Simulation, STEP	0.4	1.8	6.1	0.3 ms	5.9	3.5	0.6	0.2	18.4
Simulation, STL	0.4	2.0	5.7	0.7 ms	5.6	0.5	0.7	0.3	14.9
Simulation, OBJ	0.4	1.9	5.9	0.3 ms	5.6	8.3	0.6	0.2	23.0
Visual, GLB	0.4	1.8	6.0	0.7 ms	15.5	0.2	1.3	0.3	25.5
Visual, OBJ	0.4	1.8	6.2	0.5 ms	15.1	4.7	1.5	0.2	30.1

Board Repo: will127534/OneInchEye Board: OneInchEye.kicad_pcb Complexity 307 / 1000 (size 207, features 100) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 80, 624, 531 Triangles, simulation 1,868,154 in 74 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 62 MB 762 MB STEP 191 MB 835 MB STL 93 MB 730 MB OBJ 192 MB 1.2 GB Visual GLB 37 MB 750 MB OBJ 113 MB 840 MB

3009. NixieAtomicClock

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.2	7.5	33.8	1 ms	23.8	1.0	2.8	0.4	70.4
Simulation, STEP	1.1	7.5	34.4	0.9 ms	24.0	11.6	2.8	0.3	81.8
Simulation, STL	1.2	7.6	33.8	1 ms	24.5	2.3	2.9	0.4	72.6
Simulation, OBJ	1.2	7.6	33.3	2 ms	25.0	30.8	2.7	0.3	100.8
Visual, GLB	1.1	7.6	33.1	1 ms	69.3	0.5	5.7	0.3	117.5
Visual, OBJ	1.2	8.1	35.4	3 ms	68.5	17.7	6.0	0.3	137.1

Board Repo: will127534/RaspberryPiAtomicNixieClock Board: NixieAtomicClock.kicad_pcb Folder PCB Complexity 397 / 1000 (size 282, features 115) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 6 (20201002) Parts, tracks, vias 256, 2,400, 2,132 Triangles, simulation 6,889,714 in 363 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 225 MB 2.5 GB STEP 718 MB 2.6 GB STL 345 MB 2.3 GB OBJ 728 MB 4.3 GB Visual GLB 135 MB 2.3 GB OBJ 436 MB 2.8 GB

3010. StarlightEye

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.8	7.0	0.6 ms	5.9	0.2	0.5	0.2	16.1
Simulation, STEP	0.4	1.7	6.7	0.8 ms	5.7	3.4	0.6	0.2	18.7
Simulation, STL	0.4	1.7	6.9	0.6 ms	5.9	0.7	0.6	0.3	16.4
Simulation, OBJ	0.4	1.8	7.0	0.8 ms	6.0	8.5	0.5	0.2	24.5
Visual, GLB	0.4	1.7	6.9	0.8 ms	17.1	0.2	1.6	0.2	28.2
Visual, OBJ	0.4	1.7	6.7	1.0 ms	16.7	5.1	1.3	0.2	32.0

Board Repo: will127534/StarlightEye Board: StarlightEye.kicad_pcb Complexity 335 / 1000 (size 210, features 125) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 111, 601, 524 Triangles, simulation 2,043,226 in 113 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 69 MB 806 MB STEP 223 MB 899 MB STL 102 MB 808 MB OBJ 211 MB 1.4 GB Visual GLB 43 MB 820 MB OBJ 131 MB 933 MB

3011. macpro62_am5

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.7	10.9	0.1 ms	13.5	0.4	0.7	0.2	28.0
Simulation, STEP	0.5	1.7	11.0	0.1 ms	14.1	7.2	0.7	0.2	35.3
Simulation, STL	0.4	1.9	10.5	0.2 ms	13.4	0.8	0.6	0.2	27.9
Simulation, OBJ	0.5	1.9	10.6	0.1 ms	13.7	11.8	0.7	0.3	39.4
Visual, GLB	0.5	1.7	10.9	0.2 ms	24.7	0.3	3.4	0.3	41.7
Visual, OBJ	0.5	2.0	10.6	0.1 ms	26.1	10.3	4.2	0.2	53.9

Board Repo: winkleplex10-bit/the-mac-pro-project Board: macpro62_am5.kicad_pcb Folder kicad / macpro62-am5-v3 Complexity 209 / 1000 (size 154, features 55) KESE features curved board outline, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 10 File format KiCad 9 (20241229) Parts, tracks, vias 26, 0, 0 Triangles, simulation 2,490,472 in 26 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 88 MB 1.1 GB STEP 374 MB 1.4 GB STL 125 MB 1.1 GB OBJ 272 MB 1.7 GB Visual GLB 77 MB 1.6 GB OBJ 241 MB 1.6 GB

3012. macpro62_am5

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	2.1	12.6	0.2 ms	15.8	0.4	0.9	0.3	32.8
Simulation, STEP	0.6	2.2	12.8	0.1 ms	14.8	8.4	0.8	0.2	39.8
Simulation, STL	0.6	2.1	12.5	0.1 ms	15.3	0.8	0.8	0.3	32.4
Simulation, OBJ	0.6	2.1	12.1	0.1 ms	14.5	15.3	0.9	0.3	45.9
Visual, GLB	0.6	2.2	13.0	0.1 ms	26.4	0.4	3.2	0.2	46.0
Visual, OBJ	0.6	2.2	13.0	0.2 ms	26.2	13.9	3.3	0.3	59.5

Board Repo: winkleplex10-bit/the-mac-pro-project Board: macpro62_am5.kicad_pcb Folder kicad / macpro62-am5 Complexity 209 / 1000 (size 154, features 55) KESE features curved board outline, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 10 File format KiCad 9 (20241229) Parts, tracks, vias 26, 0, 0 Triangles, simulation 2,490,472 in 26 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 88 MB 1.1 GB STEP 374 MB 1.4 GB STL 125 MB 1.1 GB OBJ 272 MB 1.8 GB Visual GLB 77 MB 1.5 GB OBJ 241 MB 1.7 GB

3013. backplane

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.2	7.0	17.0	2 ms	30.8	0.9	2.8	0.3	60.0
Simulation, STEP	1.3	6.7	16.9	0.9 ms	30.8	15.9	3.1	0.4	75.0
Simulation, STL	1.2	6.8	17.0	0.9 ms	31.6	2.2	3.1	0.3	62.1
Simulation, OBJ	1.3	6.9	17.5	0.8 ms	32.1	35.3	2.9	0.4	96.4
Visual, GLB	1.3	6.9	17.0	1.0 ms	47.4	0.5	6.1	0.3	79.5
Visual, OBJ	1.4	7.2	18.2	2 ms	47.8	20.8	6.3	0.3	102.0

Board Repo: winkleplex10-bit/the-mac-pro-project Board: backplane.kicad_pcb Folder kicad / macpro62-backplane-v2 Complexity 370 / 1000 (size 280, features 90) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 149, 6,925, 1,336 Triangles, simulation 5,498,640 in 349 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 186 MB 1.6 GB STEP 690 MB 2.3 GB STL 275 MB 1.5 GB OBJ 582 MB 3.4 GB Visual GLB 108 MB 1.8 GB OBJ 348 MB 2.3 GB

3014. backplane

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.5	6.8	15.5	0.9 ms	28.7	1.2	3.6	0.3	57.6
Simulation, STEP	1.4	7.2	15.8	1 ms	29.1	16.6	3.8	0.4	74.3
Simulation, STL	1.6	7.5	16.7	0.9 ms	28.8	3.0	3.5	0.3	61.4
Simulation, OBJ	1.3	7.0	16.1	0.9 ms	29.4	41.0	3.8	0.4	99.0
Visual, GLB	1.4	7.1	16.2	1 ms	51.9	0.5	7.2	0.4	84.7
Visual, OBJ	1.5	7.1	16.4	2 ms	50.2	18.8	6.8	0.3	101.2

Board Repo: winkleplex10-bit/the-mac-pro-project Board: backplane.kicad_pcb Folder kicad / macpro62-backplane-v3 Complexity 427 / 1000 (size 292, features 135) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 152, 8,103, 1,423 Triangles, simulation 7,763,616 in 333 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 258 MB 2.0 GB STEP 837 MB 2.9 GB STL 388 MB 2.1 GB OBJ 834 MB 4.8 GB Visual GLB 124 MB 2.1 GB OBJ 410 MB 2.7 GB

3015. backplane

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.3	7.1	17.3	0.9 ms	32.3	1.0	3.1	0.3	62.6
Simulation, STEP	1.3	7.3	17.0	2 ms	30.7	16.5	3.0	0.4	76.2
Simulation, STL	1.4	6.9	16.8	2 ms	32.1	2.4	3.1	0.3	63.0
Simulation, OBJ	1.3	7.0	17.5	0.9 ms	31.1	32.7	3.1	0.4	93.1
Visual, GLB	1.3	7.0	17.1	0.9 ms	47.0	0.5	5.6	0.3	78.8
Visual, OBJ	1.3	6.9	17.0	2 ms	46.4	20.1	5.7	0.3	97.7

Board Repo: winkleplex10-bit/the-mac-pro-project Board: backplane.kicad_pcb Folder kicad / macpro62-backplane Complexity 370 / 1000 (size 280, features 90) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 149, 6,925, 1,336 Triangles, simulation 5,498,650 in 349 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 186 MB 1.5 GB STEP 690 MB 2.3 GB STL 275 MB 1.6 GB OBJ 582 MB 3.4 GB Visual GLB 108 MB 1.8 GB OBJ 348 MB 2.2 GB

3016. backplane_direct

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	1.0	0.2 ms	1.1	44 ms	86 ms	0.2	2.7
Simulation, STEP	0.1	0.2	0.9	0.1 ms	1.1	1.2	85 ms	0.2	3.7
Simulation, STL	0.1	0.2	0.9	0.1 ms	1.1	71 ms	93 ms	0.2	2.7
Simulation, OBJ	0.1	0.2	1.0	0.1 ms	1.2	1.2	0.1	0.2	3.9
Visual, GLB	0.1	0.2	0.9	0.1 ms	2.1	32 ms	0.2	0.2	3.7
Visual, OBJ	0.1	0.2	0.9	0.1 ms	2.1	1.0	0.2	0.2	4.7

Board Repo: winkleplex10-bit/the-mac-pro-project Board: backplane_direct.kicad_pcb Folder kicad / macpro62-backplane Complexity 171 / 1000 (size 106, features 65) KESE features rounded, trapezoid or chamfered pads, curved board outline, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 19, 0, 0 Triangles, simulation 280,020 in 13 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 10.0 MB 255 MB STEP 42 MB 293 MB STL 14 MB 257 MB OBJ 29 MB 258 MB Visual GLB 8.1 MB 268 MB OBJ 24 MB 276 MB

3017. hub_fitcheck

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	1.8	0.2 ms	1.2	39 ms	0.2	0.2	4.0
Simulation, STEP	0.1	0.3	1.6	0.2 ms	1.2	1.3	0.2	0.2	4.9
Simulation, STL	0.1	0.3	1.8	0.2 ms	1.2	91 ms	0.2	0.2	4.0
Simulation, OBJ	0.1	0.3	1.7	0.2 ms	1.2	1.6	0.2	0.2	5.4
Visual, GLB	0.1	0.3	1.7	0.2 ms	3.3	39 ms	0.4	0.2	6.0
Visual, OBJ	0.1	0.3	1.8	0.2 ms	3.0	1.3	0.3	0.3	7.2

Board Repo: winkleplex10-bit/the-mac-pro-project Board: hub_fitcheck.kicad_pcb Folder kicad / macpro62-backplane / variants / fitcheck_hub_allMCIO_cable_variant Complexity 126 / 1000 (size 96, features 30) KESE features slotted holes, rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 7, 0, 0 Triangles, simulation 298,708 in 13 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 11 MB 266 MB STEP 45 MB 296 MB STL 15 MB 269 MB OBJ 31 MB 267 MB Visual GLB 8.8 MB 285 MB OBJ 26 MB 291 MB

3018. backplane_fp6

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	1.8	0.2 ms	1.9	64 ms	0.2	0.2	4.7
Simulation, STEP	0.2	0.4	1.7	0.2 ms	1.8	1.6	0.2	0.2	6.0
Simulation, STL	0.2	0.3	1.7	0.1 ms	1.6	0.1	0.2	0.2	4.4
Simulation, OBJ	0.2	0.4	1.8	0.1 ms	1.7	1.7	0.2	0.2	6.1
Visual, GLB	0.2	0.3	1.8	0.2 ms	3.4	48 ms	0.3	0.2	6.2
Visual, OBJ	0.2	0.3	1.8	0.2 ms	3.5	1.4	0.4	0.2	7.7

Board Repo: winkleplex10-bit/the-mac-pro-project Board: backplane_fp6.kicad_pcb Folder kicad / macpro62-backplane / variants / fp6_floorplan_6L Complexity 191 / 1000 (size 116, features 75) KESE features slotted holes, rounded, trapezoid or chamfered pads, curved board outline, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 20, 0, 0 Triangles, simulation 418,448 in 15 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 15 MB 307 MB STEP 61 MB 355 MB STL 21 MB 306 MB OBJ 44 MB 357 MB Visual GLB 12 MB 363 MB OBJ 36 MB 411 MB

3019. backplane_hub_fp2

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.4	2.4	0.1 ms	2.1	76 ms	0.3	0.2	5.8
Simulation, STEP	0.2	0.4	2.6	0.2 ms	2.1	2.0	0.3	0.2	7.9
Simulation, STL	0.2	0.5	2.6	0.2 ms	2.2	0.1	0.2	0.2	6.0
Simulation, OBJ	0.2	0.5	2.5	0.2 ms	2.2	2.8	0.2	0.2	8.8
Visual, GLB	0.2	0.4	2.4	0.2 ms	4.2	54 ms	0.3	0.2	7.9
Visual, OBJ	0.3	0.5	2.4	0.2 ms	3.8	1.9	0.4	0.3	9.7

Board Repo: winkleplex10-bit/the-mac-pro-project Board: backplane_hub_fp2.kicad_pcb Folder kicad / macpro62-backplane / variants / hub_fp2_d30_assumed Complexity 192 / 1000 (size 117, features 75) KESE features slotted holes, rounded, trapezoid or chamfered pads, curved board outline, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 21, 0, 0 Triangles, simulation 429,260 in 15 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 15 MB 315 MB STEP 62 MB 352 MB STL 21 MB 311 MB OBJ 46 MB 358 MB Visual GLB 12 MB 418 MB OBJ 37 MB 413 MB

3020. macpro62-io-board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.2	7.1	0.2 ms	7.5	0.3	0.5	0.3	17.4
Simulation, STEP	0.5	1.1	7.4	0.3 ms	7.8	5.0	0.5	0.2	22.5
Simulation, STL	0.5	1.3	7.5	0.2 ms	7.7	0.6	0.5	0.2	18.2
Simulation, OBJ	0.5	1.2	7.6	0.3 ms	8.1	7.0	0.5	0.2	25.1
Visual, GLB	0.5	1.2	7.5	0.1 ms	16.2	0.2	1.5	0.2	27.3
Visual, OBJ	0.5	1.2	7.4	0.4 ms	15.8	6.0	2.2	0.2	33.4

Board Repo: winkleplex10-bit/the-mac-pro-project Board: macpro62-io-board.kicad_pcb Folder kicad / macpro62-io-board Complexity 237 / 1000 (size 162, features 75) KESE features slotted holes, rounded, trapezoid or chamfered pads, curved board outline, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 143, 0, 0 Triangles, simulation 1,595,010 in 16 parts Note mostly unrouted Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 59 MB 735 MB STEP 284 MB 919 MB STL 80 MB 752 MB OBJ 180 MB 1.2 GB Visual GLB 47 MB 1.1 GB OBJ 147 MB 1.1 GB

3021. mod_hdmi

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	56 ms	0.1	0.5	0.1 ms	1.1	30 ms	0.1	0.2	2.2
Simulation, STEP	56 ms	0.2	0.5	0.1 ms	1.2	0.9	0.1	0.2	3.1
Simulation, STL	55 ms	0.1	0.5	0.1 ms	1.1	46 ms	0.1	0.2	2.2
Simulation, OBJ	84 ms	0.1	0.5	0.2 ms	1.1	0.8	0.1	0.2	2.9
Visual, GLB	60 ms	0.1	0.5	2 ms	1.7	21 ms	0.2	0.2	2.8
Visual, OBJ	74 ms	0.2	0.5	0.1 ms	1.8	0.6	0.2	0.2	3.4

Board Repo: winkleplex10-bit/the-mac-pro-project Board: mod_hdmi.kicad_pcb Folder kicad / macpro62-io-modules / mod_hdmi Complexity 196 / 1000 (size 131, features 65) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 4, 291, 24 Triangles, simulation 168,642 in 27 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 6.3 MB 211 MB STEP 36 MB 223 MB STL 8.4 MB 205 MB OBJ 18 MB 207 MB Visual GLB 5.0 MB 175 MB OBJ 14 MB 175 MB

3022. mod_usba

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	99 ms	0.3	1.6	0.3 ms	2.2	48 ms	0.3	0.2	4.8
Simulation, STEP	98 ms	0.3	1.6	0.2 ms	2.4	1.5	0.3	0.2	6.5
Simulation, STL	0.1	0.4	1.6	0.2 ms	2.2	69 ms	0.3	0.3	4.9
Simulation, OBJ	94 ms	0.3	1.6	0.2 ms	2.2	1.3	0.3	0.3	6.1
Visual, GLB	0.1	0.4	1.5	0.1 ms	2.8	36 ms	0.3	0.2	5.2
Visual, OBJ	96 ms	0.3	1.5	0.2 ms	2.7	1.0	0.2	0.2	6.0

Board Repo: winkleplex10-bit/the-mac-pro-project Board: mod_usba.kicad_pcb Folder kicad / macpro62-io-modules / mod_usba Complexity 190 / 1000 (size 125, features 65) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 4, 198, 19 Triangles, simulation 264,738 in 22 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 10 MB 263 MB STEP 57 MB 273 MB STL 13 MB 262 MB OBJ 29 MB 257 MB Visual GLB 7.1 MB 236 MB OBJ 20 MB 237 MB

3023. mod_usbc

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	92 ms	0.2	0.5	0.1 ms	1.4	39 ms	0.2	0.2	2.7
Simulation, STEP	91 ms	0.2	0.6	0.2 ms	1.3	1.1	0.2	0.2	3.7
Simulation, STL	76 ms	0.2	0.5	0.2 ms	1.2	45 ms	0.2	0.2	2.5
Simulation, OBJ	77 ms	0.2	0.6	0.1 ms	1.2	1.0	0.2	0.2	3.4
Visual, GLB	76 ms	0.2	0.5	0.2 ms	2.0	26 ms	0.2	0.2	3.3
Visual, OBJ	73 ms	0.2	0.5	0.1 ms	1.9	0.9	0.2	0.2	4.0

Board Repo: winkleplex10-bit/the-mac-pro-project Board: mod_usbc.kicad_pcb Folder kicad / macpro62-io-modules / mod_usbc Complexity 209 / 1000 (size 134, features 75) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 4, 361, 29 Triangles, simulation 184,304 in 30 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 6.9 MB 208 MB STEP 39 MB 232 MB STL 9.2 MB 206 MB OBJ 19 MB 209 MB Visual GLB 5.5 MB 192 MB OBJ 15 MB 188 MB

3024. panel_a25

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	2.8	18.7	0.6 ms	51.1	0.3	2.5	0.3	76.4
Simulation, STEP	0.7	2.6	18.5	0.4 ms	50.3	8.7	2.5	0.3	83.8
Simulation, STL	0.8	2.7	18.2	0.4 ms	50.9	0.5	2.4	0.3	75.9
Simulation, OBJ	0.8	2.7	19.2	0.3 ms	50.9	10.9	2.7	0.3	87.5
Visual, GLB	0.8	2.8	19.1	0.5 ms	25.2	0.2	1.7	0.3	50.1
Visual, OBJ	0.8	2.9	19.9	0.4 ms	25.4	8.1	2.1	0.3	59.5

Board Repo: winkleplex10-bit/the-mac-pro-project Board: panel_a25.kicad_pcb Folder kicad / macpro62-io-modules / panel / panel_a25 Complexity 220 / 1000 (size 165, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper drawings Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 22, 825, 88 Triangles, simulation 1,738,244 in 61 parts Note panel Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 68 MB 969 MB STEP 418 MB 1.0 GB STL 87 MB 945 MB OBJ 202 MB 1.4 GB Visual GLB 48 MB 1.2 GB OBJ 142 MB 1.1 GB

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