Corpus Testing 04

Corpus Page 4

Part 4 of 30 of Corpus Testing: boards 325 to 432, six runs each, one file format a run, as Corpus Testing describes.

325. Caravel_breakout_v2

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.5	2.5	0.4 ms	2.6	91 ms	0.4	0.3	6.6
Simulation, STEP	0.3	0.5	2.5	0.4 ms	2.5	2.1	0.4	0.2	8.4
Simulation, STL	0.2	0.4	2.5	0.5 ms	2.5	0.1	0.5	0.3	6.5
Simulation, OBJ	0.2	0.4	2.5	0.4 ms	3.0	3.3	0.4	0.2	10.1
Visual, GLB	0.3	0.5	2.6	0.3 ms	4.9	90 ms	0.4	0.3	9.1
Visual, OBJ	0.3	0.4	2.5	0.4 ms	4.6	2.4	0.4	0.2	10.9

Board Repo: antmicro/caravel_board Board: Caravel_breakout_v2.kicad_pcb Folder hardware / caravel_breakout_v2 Complexity 275 / 1000 (size 200, features 75) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 6 (20211014) Parts, tracks, vias 12, 469, 28 Triangles, simulation 522,928 in 69 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 18 MB 300 MB STEP 97 MB 365 MB STL 26 MB 302 MB OBJ 54 MB 383 MB Visual GLB 13 MB 364 MB OBJ 38 MB 369 MB

326. Caravel_daughter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.9	1.9	0.5 ms	1.7	74 ms	0.2	0.2	5.1
Simulation, STEP	0.2	0.9	1.7	0.5 ms	1.6	1.6	0.2	0.2	6.4
Simulation, STL	0.2	0.9	1.7	0.3 ms	1.6	0.1	0.2	0.3	5.0
Simulation, OBJ	0.2	0.8	1.7	0.6 ms	1.5	2.0	0.2	0.3	6.7
Visual, GLB	0.2	0.8	1.8	0.3 ms	3.4	41 ms	0.3	0.2	6.7
Visual, OBJ	0.2	0.9	1.8	0.4 ms	3.6	1.1	0.3	0.3	8.1

Board Repo: antmicro/caravel_board Board: Caravel_daughter.kicad_pcb Folder hardware / caravel_daughter Complexity 138 / 1000 (size 108, features 30) KESE features rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 36, 0, 0 Triangles, simulation 390,448 in 66 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 14 MB 269 MB STEP 76 MB 318 MB STL 20 MB 265 MB OBJ 41 MB 322 MB Visual GLB 7.5 MB 267 MB OBJ 22 MB 266 MB

327. caravel_FTDI_QFN_test_socket

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.2	6.3	1 ms	5.7	0.2	0.6	0.3	14.7
Simulation, STEP	0.3	1.1	6.4	1 ms	5.5	4.5	0.6	0.2	18.7
Simulation, STL	0.3	1.3	6.7	1 ms	6.4	0.5	0.7	0.2	16.1
Simulation, OBJ	0.4	1.3	6.5	0.9 ms	5.3	6.6	0.6	0.2	20.9
Visual, GLB	0.3	1.2	6.7	0.8 ms	12.4	0.2	1.7	0.2	22.8
Visual, OBJ	0.3	1.1	6.3	0.9 ms	12.7	5.0	1.4	0.2	27.1

Board Repo: antmicro/caravel_board Board: caravel_FTDI_QFN_test_socket.kicad_pcb Folder hardware / caravel_FTDI_QFN_test_socket Complexity 315 / 1000 (size 230, features 85) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 6 (20211014) Parts, tracks, vias 72, 1,076, 164 Triangles, simulation 1,635,312 in 99 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 56 MB 606 MB STEP 277 MB 809 MB STL 82 MB 588 MB OBJ 169 MB 1.1 GB Visual GLB 41 MB 784 MB OBJ 126 MB 936 MB

328. caravel_Nucleo

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.9	9.9	1 ms	8.7	0.4	1.1	0.3	22.7
Simulation, STEP	0.5	1.7	9.8	2 ms	8.9	6.4	1.2	0.3	28.7
Simulation, STL	0.5	1.8	9.9	1 ms	8.4	0.8	1.1	0.3	22.8
Simulation, OBJ	0.5	1.9	9.5	0.9 ms	8.4	10.5	1.1	0.3	32.3
Visual, GLB	0.5	1.9	9.8	1 ms	20.4	0.3	2.8	0.3	35.9
Visual, OBJ	0.5	2.2	10.1	1 ms	20.5	7.6	2.8	0.2	43.9

Board Repo: antmicro/caravel_board Board: caravel_Nucleo.kicad_pcb Folder hardware / caravel_Nucleo Complexity 333 / 1000 (size 228, features 105) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, drill offsets, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 6 (20211014) Parts, tracks, vias 89, 1,284, 162 Triangles, simulation 2,223,932 in 208 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 75 MB 745 MB STEP 364 MB 998 MB STL 111 MB 756 MB OBJ 232 MB 1.5 GB Visual GLB 55 MB 1.1 GB OBJ 169 MB 1.2 GB

329. Caravel_pcb

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	2.2	8.0	0.6 ms	6.5	0.2	0.7	0.3	18.7
Simulation, STEP	0.4	1.7	7.5	0.5 ms	6.2	4.1	0.7	0.2	20.9
Simulation, STL	0.4	1.7	7.8	0.4 ms	6.0	0.5	0.7	0.3	17.3
Simulation, OBJ	0.4	1.6	7.4	0.5 ms	6.2	7.4	0.7	0.3	24.0
Visual, GLB	0.4	1.7	7.6	0.4 ms	11.7	0.2	1.4	0.2	23.3
Visual, OBJ	0.4	1.6	8.1	0.5 ms	12.2	5.8	1.4	0.2	29.8

Board Repo: antmicro/caravel_board Board: Caravel_pcb.kicad_pcb Folder hardware / caravel_pcb_v1 Complexity 290 / 1000 (size 235, features 55) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 72, 1,749, 98 Triangles, simulation 1,242,816 in 99 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 44 MB 520 MB STEP 248 MB 654 MB STL 62 MB 526 MB OBJ 131 MB 885 MB Visual GLB 32 MB 628 MB OBJ 95 MB 747 MB

330. caravel_pcb_v3_FTDI_flexy

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.4	7.8	0.6 ms	5.6	0.2	0.7	0.2	16.5
Simulation, STEP	0.5	1.5	7.5	0.7 ms	5.3	4.8	0.7	0.2	20.5
Simulation, STL	0.4	1.4	7.6	0.6 ms	5.4	0.4	0.8	0.2	16.3
Simulation, OBJ	0.5	1.4	7.7	0.4 ms	5.6	9.1	0.8	0.2	25.4
Visual, GLB	0.5	1.6	7.8	1.0 ms	13.7	0.2	1.3	0.3	25.3
Visual, OBJ	0.5	1.5	7.8	0.6 ms	13.5	6.5	1.4	0.3	31.5

Board Repo: antmicro/caravel_board Board: caravel_pcb_v3_FTDI_flexy.kicad_pcb Folder hardware / caravel_pcb_v3_FTDI Complexity 314 / 1000 (size 219, features 95) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, drill offsets, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 6 (20211014) Parts, tracks, vias 63, 935, 122 Triangles, simulation 1,524,006 in 98 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 52 MB 585 MB STEP 270 MB 782 MB STL 76 MB 605 MB OBJ 157 MB 1.0 GB Visual GLB 39 MB 715 MB OBJ 118 MB 875 MB

331. caravel_pcb_v3_FTDI_SMD

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.1	4.8	0.5 ms	5.0	0.2	0.6	0.3	12.4
Simulation, STEP	0.4	1.1	4.8	0.6 ms	4.5	3.8	0.5	0.2	15.4
Simulation, STL	0.3	1.0	4.7	0.8 ms	4.5	0.5	0.5	0.2	11.8
Simulation, OBJ	0.4	1.2	5.2	0.7 ms	4.7	5.9	0.5	0.3	18.1
Visual, GLB	0.4	1.1	4.8	0.7 ms	9.8	0.2	1.5	0.3	18.0
Visual, OBJ	0.4	1.1	4.8	0.7 ms	10.3	5.1	1.6	0.2	23.5

Board Repo: antmicro/caravel_board Board: caravel_pcb_v3_FTDI_SMD.kicad_pcb Folder hardware / caravel_pcb_v3_FTDI Complexity 305 / 1000 (size 220, features 85) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 6 (20211014) Parts, tracks, vias 63, 932, 131 Triangles, simulation 1,286,120 in 97 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 44 MB 556 MB STEP 229 MB 681 MB STL 64 MB 545 MB OBJ 131 MB 861 MB Visual GLB 35 MB 663 MB OBJ 104 MB 792 MB

332. caravel_pcb_v3_MCP

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.4	2.1	0.7 ms	1.8	86 ms	0.3	0.3	5.1
Simulation, STEP	0.1	0.5	2.3	0.4 ms	1.7	1.6	0.3	0.2	6.7
Simulation, STL	0.1	0.4	2.2	0.4 ms	1.6	0.1	0.3	0.2	5.0
Simulation, OBJ	0.2	0.4	2.2	0.5 ms	1.7	2.6	0.3	0.2	7.5
Visual, GLB	0.2	0.5	2.1	0.5 ms	3.9	47 ms	0.4	0.3	7.5
Visual, OBJ	0.2	0.4	2.2	0.7 ms	3.9	1.5	0.5	0.3	8.9

Board Repo: antmicro/caravel_board Board: caravel_pcb_v3_MCP.kicad_pcb Folder hardware / caravel_pcb_v3_MCP Complexity 76 / 1000 (size 56, features 20) KESE features slotted holes, rounded, trapezoid or chamfered pads Tested 9th November 2026 Copper layers 2 File format KiCad 6 (20211014) Parts, tracks, vias 38, 0, 0 Triangles, simulation 494,144 in 78 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 16 MB 287 MB STEP 61 MB 325 MB STL 25 MB 281 MB OBJ 50 MB 377 MB Visual GLB 11 MB 336 MB OBJ 32 MB 339 MB

333. caravel_pcb_v4_FTDI_flexy

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.2	7.0	0.4 ms	4.8	0.2	0.7	0.2	14.5
Simulation, STEP	0.4	1.1	6.6	0.4 ms	4.9	4.4	0.6	0.2	18.3
Simulation, STL	0.4	1.4	6.6	0.8 ms	4.6	0.5	0.7	0.2	14.4
Simulation, OBJ	0.4	1.2	6.4	0.6 ms	5.0	7.2	0.6	0.2	20.9
Visual, GLB	0.4	1.2	6.9	0.8 ms	11.5	0.1	1.2	0.2	21.6
Visual, OBJ	0.4	1.2	6.9	0.5 ms	11.7	5.7	1.6	0.2	27.7

Board Repo: antmicro/caravel_board Board: caravel_pcb_v4_FTDI_flexy.kicad_pcb Folder hardware / caravel_pcb_v4_FTDI Complexity 312 / 1000 (size 217, features 95) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, drill offsets, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 6 (20211014) Parts, tracks, vias 61, 884, 104 Triangles, simulation 1,428,776 in 104 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 49 MB 601 MB STEP 248 MB 741 MB STL 71 MB 583 MB OBJ 147 MB 990 MB Visual GLB 36 MB 805 MB OBJ 108 MB 858 MB

334. caravel_pcb_v4_FTDI_SMD

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.1	5.1	0.7 ms	4.9	0.2	0.6	0.3	12.6
Simulation, STEP	0.4	1.1	5.1	0.6 ms	4.7	4.0	0.6	0.2	16.1
Simulation, STL	0.3	1.0	5.0	0.6 ms	4.9	0.4	0.7	0.3	12.5
Simulation, OBJ	0.4	1.2	5.3	0.9 ms	4.8	6.3	0.5	0.2	18.7
Visual, GLB	0.4	1.1	4.8	0.5 ms	9.4	0.2	1.0	0.2	17.0
Visual, OBJ	0.4	1.1	4.9	0.3 ms	9.2	5.1	1.0	0.2	22.0

Board Repo: antmicro/caravel_board Board: caravel_pcb_v4_FTDI_SMD.kicad_pcb Folder hardware / caravel_pcb_v4_FTDI Complexity 303 / 1000 (size 218, features 85) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 6 (20211014) Parts, tracks, vias 61, 854, 123 Triangles, simulation 1,217,782 in 103 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 42 MB 509 MB STEP 212 MB 671 MB STL 61 MB 529 MB OBJ 124 MB 815 MB Visual GLB 33 MB 724 MB OBJ 98 MB 772 MB

335. cm4-baseboard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	12.0	10.4	30.5	1 ms	39.2	1.9	6.8	0.6	101.4
Simulation, STEP	11.8	10.9	30.1	2 ms	38.8	23.4	6.0	0.5	121.5
Simulation, STL	10.7	10.4	29.3	2 ms	37.0	4.0	6.0	0.5	98.0
Simulation, OBJ	10.8	10.0	29.6	1 ms	36.3	62.5	5.5	0.6	155.2
Visual, GLB	11.4	10.1	29.3	2 ms	95.0	0.9	9.6	0.4	156.7
Visual, OBJ	11.7	10.7	29.9	1 ms	92.1	35.7	9.0	0.4	189.5

Board Repo: antmicro/cm4-baseboard Board: cm4-baseboard.kicad_pcb Complexity 472 / 1000 (size 307, features 165) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 442, 6,879, 1,129 Triangles, simulation 9,169,160 in 522 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 312 MB 2.8 GB STEP 1.3 GB 3.5 GB STL 459 MB 2.8 GB OBJ 986 MB 6.0 GB Visual GLB 193 MB 3.3 GB OBJ 622 MB 4.2 GB

336. cm4-lvds-adapter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.7	2.1	5.2	0.6 ms	7.1	0.3	1.1	0.3	18.8
Simulation, STEP	2.9	2.0	5.0	0.8 ms	7.1	5.0	1.0	0.3	23.3
Simulation, STL	2.9	2.0	4.9	0.5 ms	7.3	0.7	1.0	0.3	19.1
Simulation, OBJ	3.0	2.1	5.1	0.7 ms	7.5	11.2	1.0	0.3	30.3
Visual, GLB	2.9	1.9	4.9	0.8 ms	16.6	0.2	1.8	0.3	28.7
Visual, OBJ	3.1	2.0	5.3	0.9 ms	16.3	7.1	1.7	0.3	35.8

Board Repo: antmicro/cm4-baseboard-lvds-adapter Board: cm4-lvds-adapter.kicad_pcb Complexity 408 / 1000 (size 263, features 145) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 130, 1,596, 254 Triangles, simulation 2,092,774 in 158 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 71 MB 737 MB STEP 278 MB 973 MB STL 105 MB 738 MB OBJ 218 MB 1.4 GB Visual GLB 45 MB 889 MB OBJ 140 MB 1.1 GB

337. com-express-7-baseboard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	17.4	17.8	54.6	3 ms	79.1	4.6	12.4	1.0	186.9
Simulation, STEP	19.1	17.8	55.2	3 ms	77.6	42.2	12.4	0.8	225.1
Simulation, STL	18.8	17.4	55.7	3 ms	79.1	10.2	11.6	0.8	193.6
Simulation, OBJ	18.4	18.4	58.9	5 ms	84.5	143.3	13.6	1.1	338.2
Visual, GLB	19.8	17.8	56.5	3 ms	249.6	2.5	22.4	0.7	369.4
Visual, OBJ	17.6	18.0	55.6	3 ms	231.8	66.0	22.6	0.8	412.4

Board Repo: antmicro/com-express-7-baseboard Board: com-express-7-baseboard.kicad_pcb Complexity 525 / 1000 (size 345, features 180) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 to 10th November 2026 Copper layers 8 File format KiCad 9 (20241229) Parts, tracks, vias 693, 10,459, 2,865 Triangles, simulation 21,291,582 in 1018 parts Verifier PASS in all six runs Run again Simulation, OBJ: failed in the corpus run, run again with the memory cap raised from 11 GB to 14.5 GB, and passed

File type File size Peak memory used Simulation GLB 684 MB 6.3 GB STEP 2.3 GB 7.1 GB STL 1.1 GB 6.2 GB OBJ 2.3 GB 13 GB Visual GLB 388 MB 6.7 GB OBJ 1.3 GB 8.2 GB

338. cvbs-mipi-bridge

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.8	1.1	3.7	0.6 ms	4.1	0.2	0.4	0.2	11.6
Simulation, STEP	1.8	1.1	3.8	0.5 ms	3.9	2.8	0.5	0.2	14.0
Simulation, STL	1.9	1.2	3.8	0.5 ms	3.8	0.4	0.4	0.3	11.8
Simulation, OBJ	1.8	1.2	3.6	0.8 ms	3.8	5.6	0.4	0.2	16.8
Visual, GLB	1.9	1.2	3.7	0.4 ms	8.8	0.1	1.3	0.3	17.2
Visual, OBJ	1.9	1.2	3.9	0.5 ms	9.1	3.9	1.3	0.3	21.5

Board Repo: antmicro/cvbs-mipi-bridge Board: cvbs-mipi-bridge.kicad_pcb Complexity 375 / 1000 (size 255, features 120) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 98, 578, 295 Triangles, simulation 1,334,870 in 113 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 45 MB 595 MB STEP 149 MB 735 MB STL 67 MB 620 MB OBJ 136 MB 988 MB Visual GLB 30 MB 796 MB OBJ 92 MB 760 MB

339. d1600e-psu-breakout-board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	3.5	4.0	13.6	0.9 ms	13.0	0.6	1.6	0.3	36.7
Simulation, STEP	3.8	4.1	13.3	1 ms	13.9	9.2	1.5	0.4	46.2
Simulation, STL	3.9	4.3	13.7	0.5 ms	13.1	1.3	1.6	0.3	38.2
Simulation, OBJ	3.6	4.0	13.7	0.5 ms	13.2	19.7	1.6	0.3	56.1
Visual, GLB	3.8	4.3	14.8	1 ms	33.5	0.5	3.7	0.3	61.0
Visual, OBJ	3.8	4.1	14.9	0.6 ms	34.3	13.3	3.8	0.4	74.4

Board Repo: antmicro/d1600e-psu-breakout Board: d1600e-psu-breakout-board.kicad_pcb Complexity 405 / 1000 (size 265, features 140) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 to 10th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 185, 985, 903 Triangles, simulation 4,123,478 in 180 parts Verifier PASS in all six runs Run again Visual, GLB; Visual, OBJ: failed in the corpus run, run again with fixes to KESE made after the corpus run, and passed

File type File size Peak memory used Simulation GLB 137 MB 1.4 GB STEP 477 MB 1.8 GB STL 206 MB 1.4 GB OBJ 433 MB 2.7 GB Visual GLB 86 MB 1.6 GB OBJ 271 MB 1.9 GB

340. data-center-rdimm-ddr4-tester

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	22.7	30.8	44.0	2 ms	85.8	4.8	12.4	1.1	201.5
Simulation, STEP	22.8	29.9	44.3	2 ms	89.9	47.7	12.6	0.9	248.2
Simulation, STL	22.5	30.1	44.6	3 ms	86.8	9.7	12.8	1.0	207.5
Simulation, OBJ									exceeded 11 GB on a 15 GB machine (stopped there, not a KESE failure); it will be run again on a machine with more memory
Visual, GLB	22.9	30.0	45.8	2 ms	186.0	1.9	15.6	0.6	302.7
Visual, OBJ	20.8	27.7	44.3	3 ms	177.7	68.1	16.4	0.7	355.7

Board Repo: antmicro/data-center-dram-tester Board: data-center-rdimm-ddr4-tester.kicad_pcb Complexity 559 / 1000 (size 359, features 200) KESE features through vias, blind and buried vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, TrueType text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 12 File format KiCad 7 (20221018) Parts, tracks, vias 648, 21,939, 2,467 Triangles, simulation 25,480,794 in 941 parts Verifier Simulation, OBJ: exceeded 11 GB on a 15 GB machine (stopped there, not a KESE failure); it will be run again on a machine with more memory

File type File size Peak memory used Simulation GLB 858 MB 6.1 GB STEP 2.4 GB 7.6 GB STL 1.3 GB 6.0 GB OBJ – 11 GB Visual GLB 353 MB 6.3 GB OBJ 1.2 GB 7.9 GB

341. dc-sci-debug-interposer

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	3.6	6.3	12.2	1.0 ms	19.7	1.1	2.7	0.4	46.1
Simulation, STEP	3.4	5.9	12.4	1 ms	20.1	11.8	3.0	0.4	57.1
Simulation, STL	3.8	6.0	12.2	1 ms	20.1	2.0	2.9	0.3	47.3
Simulation, OBJ	3.6	6.1	12.3	2 ms	20.3	35.3	2.7	0.3	80.7
Visual, GLB	3.7	6.2	12.8	1.0 ms	46.9	0.6	5.6	0.4	76.2
Visual, OBJ	3.6	6.0	12.5	1.0 ms	45.2	19.8	5.6	0.4	93.1

Board Repo: antmicro/dc-sci-debug-interposer Board: dc-sci-debug-interposer.kicad_pcb Complexity 439 / 1000 (size 294, features 145) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 8 File format KiCad 10 (20260206) Parts, tracks, vias 266, 4,217, 679 Triangles, simulation 5,925,818 in 368 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 199 MB 1.8 GB STEP 706 MB 2.1 GB STL 296 MB 1.6 GB OBJ 632 MB 3.8 GB Visual GLB 114 MB 2.0 GB OBJ 371 MB 2.6 GB

342. dc-scm-breakout-board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	6.6	9.3	15.9	1 ms	24.5	0.9	2.7	0.4	60.4
Simulation, STEP	7.1	9.5	15.9	2 ms	24.7	13.6	2.6	0.4	73.8
Simulation, STL	6.8	9.4	15.8	1 ms	23.9	1.7	2.3	0.4	60.3
Simulation, OBJ	6.3	9.2	15.9	2 ms	24.3	29.6	2.5	0.4	88.2
Visual, GLB	6.7	9.3	15.9	1 ms	44.9	0.5	5.3	0.4	83.0
Visual, OBJ	6.4	9.3	16.0	2 ms	44.7	19.3	5.6	0.4	101.8

Board Repo: antmicro/dc-scm-breakout-board Board: dc-scm-breakout-board.kicad_pcb Complexity 449 / 1000 (size 284, features 165) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 6 File format KiCad 10 (20260206) Parts, tracks, vias 282, 3,405, 582 Triangles, simulation 4,927,224 in 410 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 167 MB 1.5 GB STEP 655 MB 2.1 GB STL 246 MB 1.5 GB OBJ 525 MB 3.3 GB Visual GLB 105 MB 1.9 GB OBJ 336 MB 2.3 GB

343. bmc-reference-carrier-board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	9.2	12.0	28.2	2 ms	44.9	2.9	6.4	0.5	104.1
Simulation, STEP	9.4	11.4	27.2	2 ms	45.5	24.6	6.1	0.5	124.7
Simulation, STL	9.5	11.2	26.7	2 ms	44.7	6.5	6.7	0.7	106.1
Simulation, OBJ	9.7	12.1	27.8	2 ms	46.2	83.2	6.3	0.6	185.9
Visual, GLB	9.8	11.7	26.8	2 ms	105.3	1.0	13.2	0.5	168.3
Visual, OBJ	9.9	12.3	28.5	2 ms	104.6	33.9	13.0	0.4	202.6

Board Repo: antmicro/dc-scm-osm-l-carrier-card Board: bmc-reference-carrier-board.kicad_pcb Complexity 527 / 1000 (size 332, features 195) KESE features through vias, padstacks, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 10 File format KiCad 9 (20241229) Parts, tracks, vias 529, 8,646, 1,355 Triangles, simulation 14,795,830 in 1092 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 488 MB 3.5 GB STEP 1.5 GB 4.8 GB STL 740 MB 3.5 GB OBJ 1.6 GB 9.4 GB Visual GLB 231 MB 4.1 GB OBJ 765 MB 5.1 GB

344. dc-scm-rot-jumper-card

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.4	2.0	0.4 ms	2.1	65 ms	0.3	0.2	5.3
Simulation, STEP	0.2	0.4	2.1	0.8 ms	2.1	2.1	0.2	0.2	7.3
Simulation, STL	0.3	0.3	2.2	0.3 ms	2.2	0.2	0.2	0.2	5.6
Simulation, OBJ	0.2	0.4	2.3	0.2 ms	2.2	3.0	0.3	0.2	8.6
Visual, GLB	0.3	0.4	2.2	0.3 ms	5.1	57 ms	0.4	0.3	8.8
Visual, OBJ	0.2	0.4	2.3	0.3 ms	6.0	2.1	0.5	0.2	11.8

Board Repo: antmicro/dc-scm-rot-jumper-card Board: dc-scm-rot-jumper-card.kicad_pcb Complexity 188 / 1000 (size 153, features 35) KESE features through vias, rounded, trapezoid or chamfered pads, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 23, 348, 48 Triangles, simulation 407,326 in 58 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 15 MB 292 MB STEP 90 MB 353 MB STL 20 MB 314 MB OBJ 43 MB 353 MB Visual GLB 10 MB 326 MB OBJ 31 MB 331 MB

345. ddr4-spd-breakout

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	2.8	9.8	0.7 ms	11.1	0.4	0.9	0.3	25.9
Simulation, STEP	0.5	2.7	9.6	0.2 ms	11.4	7.1	0.9	0.3	32.5
Simulation, STL	0.6	2.8	10.0	0.4 ms	11.7	1.0	0.9	0.3	27.4
Simulation, OBJ	0.7	2.7	9.2	0.4 ms	10.4	13.2	0.8	0.3	37.2
Visual, GLB	0.5	2.4	9.2	0.7 ms	21.4	0.3	2.1	0.3	36.2
Visual, OBJ	0.5	2.7	9.3	0.4 ms	21.7	8.2	2.0	0.3	44.6

Board Repo: antmicro/ddr4-spd-breakout-board Board: ddr4-spd-breakout.kicad_pcb Complexity 306 / 1000 (size 241, features 65) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 57, 505, 450 Triangles, simulation 2,164,064 in 47 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 74 MB 807 MB STEP 270 MB 1.1 GB STL 108 MB 799 MB OBJ 226 MB 1.4 GB Visual GLB 47 MB 926 MB OBJ 144 MB 1.0 GB

346. ddr5-testbed

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.6	1.6	5.5	0.6 ms	5.9	0.3	0.8	0.2	16.0
Simulation, STEP	1.6	1.7	5.8	0.8 ms	5.9	4.1	0.9	0.2	20.3
Simulation, STL	1.7	1.7	5.4	0.6 ms	5.8	0.5	0.8	0.2	16.2
Simulation, OBJ	1.8	1.6	5.3	0.7 ms	6.0	9.2	0.8	0.3	25.0
Visual, GLB	1.8	1.6	5.5	0.7 ms	12.2	0.2	1.0	0.2	22.4
Visual, OBJ	1.6	1.6	5.6	0.8 ms	12.0	5.2	1.1	0.3	27.3

Board Repo: antmicro/ddr5-testbed Board: ddr5-testbed.kicad_pcb Complexity 379 / 1000 (size 284, features 95) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 59, 5,140, 180 Triangles, simulation 1,652,750 in 238 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 57 MB 655 MB STEP 245 MB 736 MB STL 83 MB 618 MB OBJ 175 MB 1.2 GB Visual GLB 31 MB 750 MB OBJ 97 MB 809 MB

347. data-center-rdimm-ddr5-tester

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	34.9	27.7	60.3	5 ms	98.7	5.8	15.7	1.0	244.2
Simulation, STEP	34.6	23.9	55.8	2 ms	93.1	58.3	13.8	1.3	280.9
Simulation, STL	34.0	25.2	57.9	2 ms	106.4	14.7	16.3	1.6	256.0
Simulation, OBJ	20.1	16.2	39.6	2 ms	65.3	98.1	8.5	0.8	248.7
Visual, GLB	36.2	26.9	57.6	3 ms	228.3	2.3	23.4	0.9	375.5
Visual, OBJ	33.2	24.7	58.6	5 ms	232.4	115.4	23.1	1.0	488.4

Board Repo: antmicro/ddr5-tester Board: data-center-rdimm-ddr5-tester.kicad_pcb Complexity 560 / 1000 (size 365, features 195) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 to 10th November 2026 Copper layers 12 File format KiCad 9 (20241229) Parts, tracks, vias 761, 19,710, 2,625 Triangles, simulation 22,023,050 in 849 parts Verifier PASS in all six runs Run again Simulation, OBJ: failed in the corpus run, run again with the memory cap raised from 11 GB to 14.5 GB, and passed

File type File size Peak memory used Simulation GLB 698 MB 6.0 GB STEP 2.2 GB 6.9 GB STL 1.1 GB 5.9 GB OBJ 2.4 GB 14 GB Visual GLB 361 MB 6.7 GB OBJ 1.2 GB 8.2 GB

348. dual-camera-to-gmsl-serializer-csi-adapter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.4	1.9	6.7	0.6 ms	6.7	0.3	0.8	0.3	19.1
Simulation, STEP	2.6	2.3	7.5	0.9 ms	9.5	5.7	0.8	0.3	28.8
Simulation, STL	2.4	2.0	6.5	1.0 ms	7.0	0.6	0.8	0.3	19.7
Simulation, OBJ	2.8	2.0	6.6	0.5 ms	6.7	12.0	0.8	0.4	31.2
Visual, GLB	2.3	1.9	6.2	0.6 ms	17.1	0.3	2.4	0.3	30.6
Visual, OBJ	2.6	1.9	6.7	1 ms	17.6	9.3	2.6	0.3	40.9

Board Repo: antmicro/dual-gmsl-serializer-adapter Board: dual-camera-to-gmsl-serializer-csi-adapter.kicad_pcb Complexity 357 / 1000 (size 212, features 145) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 95, 1,730, 289 Triangles, simulation 1,904,014 in 141 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 66 MB 850 MB STEP 246 MB 891 MB STL 95 MB 836 MB OBJ 202 MB 1.4 GB Visual GLB 48 MB 911 MB OBJ 150 MB 1.1 GB

349. dual-ipex-csi-interposer

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.7	2.2	0.4 ms	2.5	0.1	0.4	0.3	6.3
Simulation, STEP	0.3	0.6	2.1	0.4 ms	2.5	2.3	0.3	0.2	8.3
Simulation, STL	0.2	0.6	2.0	0.4 ms	2.4	0.2	0.4	0.2	5.9
Simulation, OBJ	0.2	0.6	1.9	0.3 ms	2.6	3.3	0.4	0.2	9.2
Visual, GLB	0.2	0.6	1.9	0.4 ms	5.1	67 ms	0.4	0.2	8.6
Visual, OBJ	0.2	0.6	2.0	0.3 ms	5.2	2.5	0.5	0.2	11.2

Board Repo: antmicro/dual-ipex-csi-interposer Board: dual-ipex-csi-interposer.kicad_pcb Complexity 267 / 1000 (size 172, features 95) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 6 (20211014) Parts, tracks, vias 13, 511, 107 Triangles, simulation 645,608 in 69 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 22 MB 348 MB STEP 103 MB 417 MB STL 32 MB 350 MB OBJ 65 MB 479 MB Visual GLB 15 MB 457 MB OBJ 45 MB 455 MB

350. ecp5-dc-scm

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	16.6	18.0	61.9	5 ms	63.3	3.7	9.1	0.8	173.4
Simulation, STEP	16.2	16.0	63.4	2 ms	61.9	33.5	8.7	0.8	200.4
Simulation, STL	14.5	15.6	61.0	2 ms	64.6	7.6	9.2	0.8	173.4
Simulation, OBJ	15.7	15.8	61.9	2 ms	63.8	100.0	9.4	0.9	267.5
Visual, GLB	16.0	16.3	60.4	2 ms	139.2	1.4	14.8	0.7	248.8
Visual, OBJ	15.8	15.7	60.2	3 ms	140.8	42.4	14.3	0.7	289.8

Board Repo: antmicro/ecp5-dc-scm Board: ecp5-dc-scm.kicad_pcb Complexity 508 / 1000 (size 343, features 165) KESE features through vias, blind and buried vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 8 File format KiCad 7 (20221018) Parts, tracks, vias 488, 12,884, 1,545 Triangles, simulation 13,991,872 in 803 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 480 MB 3.1 GB STEP 1.8 GB 4.6 GB STL 700 MB 3.4 GB OBJ 1.5 GB 9.2 GB Visual GLB 231 MB 4.2 GB OBJ 763 MB 5.5 GB

351. environment-sensor

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.8	1.0	3.2	0.6 ms	5.0	0.2	0.6	0.3	12.0
Simulation, STEP	1.8	0.9	3.4	0.5 ms	5.1	3.4	0.6	0.3	15.5
Simulation, STL	1.8	1.0	3.4	0.5 ms	5.1	0.4	0.5	0.3	12.5
Simulation, OBJ	1.9	1.0	3.4	0.5 ms	4.9	5.5	0.5	0.2	17.4
Visual, GLB	1.9	1.1	3.4	0.5 ms	9.9	0.1	1.2	0.3	17.8
Visual, OBJ	1.9	1.0	3.2	0.5 ms	9.9	4.4	1.1	0.2	21.8

Board Repo: antmicro/environment-sensor Board: environment-sensor.kicad_pcb Complexity 341 / 1000 (size 246, features 95) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 92, 863, 144 Triangles, simulation 1,221,012 in 105 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 42 MB 559 MB STEP 208 MB 681 MB STL 61 MB 555 MB OBJ 126 MB 890 MB Visual GLB 30 MB 803 MB OBJ 91 MB 793 MB

352. environment-sensor-sip-baseboard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	0.8	3.3	0.4 ms	3.8	0.1	0.5	0.3	9.6
Simulation, STEP	0.8	0.9	3.5	0.4 ms	3.8	3.0	0.5	0.2	12.6
Simulation, STL	0.9	0.9	3.5	0.4 ms	3.8	0.2	0.6	0.3	10.3
Simulation, OBJ	0.8	0.8	3.4	0.3 ms	3.9	4.9	0.7	0.3	14.9
Visual, GLB	0.8	0.9	3.6	0.4 ms	7.7	0.1	0.8	0.2	14.1
Visual, OBJ	0.8	0.8	3.3	0.5 ms	8.2	3.2	0.7	0.2	17.3

Board Repo: antmicro/environment-sensor-myra-baseboard Board: environment-sensor-sip-baseboard.kicad_pcb Complexity 372 / 1000 (size 232, features 140) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 33, 434, 106 Triangles, simulation 824,680 in 64 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 28 MB 410 MB STEP 133 MB 482 MB STL 41 MB 407 MB OBJ 84 MB 636 MB Visual GLB 19 MB 545 MB OBJ 58 MB 550 MB

353. lz1-led-driver

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.1	0.5	2.6	0.2 ms	2.4	97 ms	0.4	0.2	7.2
Simulation, STEP	1.1	0.5	2.7	0.2 ms	2.5	2.1	0.4	0.3	9.6
Simulation, STL	1.0	0.5	2.5	0.2 ms	2.3	0.2	0.4	0.2	7.1
Simulation, OBJ	1.0	0.5	2.6	0.2 ms	2.3	3.7	0.4	0.2	10.7
Visual, GLB	0.9	0.5	2.6	0.2 ms	5.6	74 ms	0.4	0.2	10.3
Visual, OBJ	0.9	0.5	2.6	0.2 ms	5.8	2.7	0.5	0.2	13.3

Board Repo: antmicro/flickerless-led-driver Board: lz1-led-driver.kicad_pcb Complexity 253 / 1000 (size 158, features 95) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 41, 161, 101 Triangles, simulation 675,574 in 39 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 23 MB 391 MB STEP 135 MB 447 MB STL 34 MB 391 MB OBJ 69 MB 512 MB Visual GLB 16 MB 460 MB OBJ 49 MB 490 MB

354. fmc2sata

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	2.2	8.1	0.7 ms	6.5	0.3	0.7	0.3	18.9
Simulation, STEP	0.8	2.2	8.1	0.8 ms	6.9	5.3	0.7	0.3	24.2
Simulation, STL	0.7	2.2	8.3	1.0 ms	6.9	0.7	0.7	0.3	19.8
Simulation, OBJ	0.7	2.3	8.1	0.7 ms	6.8	11.2	0.8	0.3	30.0
Visual, GLB	0.7	2.3	8.2	0.7 ms	15.0	0.2	1.5	0.3	28.3
Visual, OBJ	0.8	2.2	8.2	0.7 ms	14.4	6.6	1.6	0.3	34.1

Board Repo: antmicro/fmc-sata-adapter Board: fmc2sata.kicad_pcb Complexity 253 / 1000 (size 198, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 59, 769, 258 Triangles, simulation 1,824,356 in 179 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 63 MB 888 MB STEP 287 MB 891 MB STL 91 MB 821 MB OBJ 193 MB 1.3 GB Visual GLB 39 MB 865 MB OBJ 119 MB 887 MB

355. framos-csi-adapter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.4	0.6	2.1	0.6 ms	2.9	0.1	0.4	0.2	7.7
Simulation, STEP	1.5	0.6	2.1	0.3 ms	2.8	2.5	0.5	0.2	10.3
Simulation, STL	1.4	0.7	2.1	0.3 ms	3.0	0.2	0.4	0.2	8.0
Simulation, OBJ	1.4	0.6	2.2	0.3 ms	3.0	4.1	0.5	0.2	12.0
Visual, GLB	1.4	0.7	2.3	0.6 ms	6.8	87 ms	0.6	0.3	12.1
Visual, OBJ	1.4	0.7	2.3	0.3 ms	6.5	3.1	0.6	0.2	14.8

Board Repo: antmicro/framos-csi-adapter Board: framos-csi-adapter.kicad_pcb Complexity 297 / 1000 (size 187, features 110) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper text, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 41, 705, 87 Triangles, simulation 762,210 in 81 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 26 MB 418 MB STEP 131 MB 457 MB STL 38 MB 415 MB OBJ 77 MB 589 MB Visual GLB 19 MB 554 MB OBJ 58 MB 541 MB

356. gem-demo-board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	5.4	15.6	1 ms	14.2	0.8	1.8	0.3	39.0
Simulation, STEP	0.7	5.1	14.7	1 ms	14.0	8.2	2.2	0.3	45.2
Simulation, STL	0.8	5.3	15.6	2 ms	14.5	1.2	1.7	0.3	39.4
Simulation, OBJ	0.8	5.1	14.5	1 ms	14.1	20.8	1.7	0.3	57.3
Visual, GLB	0.8	5.1	14.3	1.0 ms	25.7	0.3	2.9	0.3	49.5
Visual, OBJ	0.8	5.1	14.8	1 ms	27.6	11.1	3.0	0.3	62.7

Board Repo: antmicro/gem-baseboard Board: gem-demo-board.kicad_pcb Complexity 290 / 1000 (size 235, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text Tested 9th November 2026 Copper layers 6 File format KiCad 5 (20171130) Parts, tracks, vias 122, 3,756, 417 Triangles, simulation 3,761,442 in 229 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 130 MB 988 MB STEP 482 MB 1.2 GB STL 188 MB 954 MB OBJ 403 MB 2.5 GB Visual GLB 64 MB 1.3 GB OBJ 206 MB 1.5 GB

357. zglue-gem1-adapter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	2.1	4.6	0.7 ms	4.9	0.3	0.8	0.3	13.4
Simulation, STEP	0.3	2.1	5.0	0.6 ms	5.1	3.5	0.8	0.2	17.0
Simulation, STL	0.4	2.1	4.9	0.6 ms	5.2	0.4	0.8	0.2	14.1
Simulation, OBJ	0.4	2.1	4.6	0.6 ms	5.0	9.2	0.8	0.2	22.4
Visual, GLB	0.4	2.1	4.8	0.6 ms	10.8	0.1	1.1	0.2	19.6
Visual, OBJ	0.4	2.1	4.9	0.6 ms	11.4	5.3	1.3	0.2	25.6

Board Repo: antmicro/gem1-adapter Board: zglue-gem1-adapter.kicad_pcb Complexity 315 / 1000 (size 270, features 45) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 6 File format KiCad 5 (20171130) Parts, tracks, vias 44, 2,794, 221 Triangles, simulation 1,631,130 in 133 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 54 MB 571 MB STEP 188 MB 658 MB STL 82 MB 574 MB OBJ 170 MB 1.1 GB Visual GLB 29 MB 717 MB OBJ 91 MB 714 MB

358. gem2-adapter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	2.0	4.5	0.6 ms	5.0	0.2	0.8	0.3	13.1
Simulation, STEP	0.3	2.2	4.4	0.6 ms	5.2	2.9	0.8	0.3	16.0
Simulation, STL	0.3	1.8	4.3	0.8 ms	5.1	0.4	0.7	0.2	12.9
Simulation, OBJ	0.3	1.8	4.3	0.6 ms	5.1	7.0	0.8	0.2	19.4
Visual, GLB	0.3	1.7	4.2	0.5 ms	11.3	0.1	1.0	0.2	18.8
Visual, OBJ	0.3	1.9	4.5	0.7 ms	11.4	3.9	1.2	0.3	23.5

Board Repo: antmicro/gem2-adapter Board: gem2-adapter.kicad_pcb Complexity 313 / 1000 (size 268, features 45) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 6 File format KiCad 5 (20171130) Parts, tracks, vias 46, 2,404, 212 Triangles, simulation 1,644,764 in 133 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 55 MB 576 MB STEP 198 MB 633 MB STL 82 MB 541 MB OBJ 172 MB 1.1 GB Visual GLB 30 MB 747 MB OBJ 94 MB 769 MB

359. gmsl-deserializer

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	3.8	2.5	8.1	1 ms	13.4	0.5	1.1	0.3	29.7
Simulation, STEP	3.7	2.4	8.3	0.4 ms	13.7	7.5	1.0	0.3	37.0
Simulation, STL	3.7	2.3	8.4	0.7 ms	13.7	1.0	1.0	0.3	30.5
Simulation, OBJ	3.9	2.2	8.0	0.9 ms	14.0	13.4	1.0	0.3	42.8
Visual, GLB	3.8	2.4	8.0	0.8 ms	22.8	0.3	3.2	0.3	40.9
Visual, OBJ	3.7	2.5	8.5	0.8 ms	23.0	10.0	3.4	0.3	51.4

Board Repo: antmicro/gmsl-deserializer Board: gmsl-deserializer.kicad_pcb Complexity 420 / 1000 (size 265, features 155) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 206, 2,413, 362 Triangles, simulation 2,685,502 in 163 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 91 MB 1.0 GB STEP 412 MB 1.3 GB STL 134 MB 1.0 GB OBJ 281 MB 1.8 GB Visual GLB 69 MB 1.2 GB OBJ 215 MB 1.5 GB

360. gmsl-serializer

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.9	1.3	4.1	0.4 ms	5.8	0.3	0.6	0.3	14.2
Simulation, STEP	2.4	1.3	4.3	0.5 ms	6.2	3.8	0.6	0.2	18.9
Simulation, STL	2.2	1.2	4.3	0.6 ms	5.5	0.5	0.5	0.3	14.5
Simulation, OBJ	2.2	1.3	4.3	0.5 ms	5.8	6.4	0.6	0.3	20.9
Visual, GLB	2.3	1.3	4.0	0.6 ms	10.2	0.1	1.4	0.3	19.5
Visual, OBJ	2.2	1.5	4.4	0.6 ms	10.9	4.6	1.7	0.2	25.5

Board Repo: antmicro/gmsl-serializer Board: gmsl-serializer.kicad_pcb Complexity 374 / 1000 (size 244, features 130) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 104, 878, 206 Triangles, simulation 1,204,088 in 110 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 42 MB 561 MB STEP 154 MB 643 MB STL 60 MB 558 MB OBJ 125 MB 876 MB Visual GLB 30 MB 709 MB OBJ 90 MB 792 MB

361. gpu-cluster-backplane

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	10.8	17.0	48.5	1 ms	57.8	2.3	5.8	0.6	143.0
Simulation, STEP	10.8	18.0	50.4	1 ms	60.0	30.1	6.2	0.6	176.2
Simulation, STL	11.6	18.3	52.8	1 ms	60.1	6.3	6.6	0.6	156.2
Simulation, OBJ	11.2	18.9	51.9	2 ms	60.7	100.6	6.9	0.6	250.7
Visual, GLB	11.5	18.5	51.9	1 ms	148.1	1.4	15.8	0.7	248.0
Visual, OBJ	12.1	21.0	52.6	1 ms	152.4	56.9	14.6	0.5	310.2

Board Repo: antmicro/gpu-cluster-backplane Board: gpu-cluster-backplane.kicad_pcb Complexity 457 / 1000 (size 307, features 150) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 541, 4,646, 3,885 Triangles, simulation 13,710,074 in 399 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 448 MB 3.3 GB STEP 1.3 GB 4.9 GB STL 686 MB 3.5 GB OBJ 1.5 GB 8.7 GB Visual GLB 294 MB 5.0 GB OBJ 956 MB 6.3 GB

362. hdmi-edid-debug-board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.1	1.3	5.0	0.6 ms	4.5	0.2	0.5	0.2	13.8
Simulation, STEP	1.9	1.3	5.1	0.4 ms	4.8	3.6	0.5	0.2	17.4
Simulation, STL	2.0	1.3	5.1	0.5 ms	5.0	0.4	0.5	0.2	14.4
Simulation, OBJ	1.9	1.2	5.0	0.4 ms	4.8	7.2	0.6	0.2	21.0
Visual, GLB	2.0	1.3	5.0	0.5 ms	10.8	0.1	0.9	0.2	20.3
Visual, OBJ	2.0	1.3	4.9	0.4 ms	10.3	5.3	1.1	0.3	25.1

Board Repo: antmicro/hdmi-edid-debug-board Board: hdmi-edid-debug-board.kicad_pcb Complexity 396 / 1000 (size 246, features 150) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 98, 1,266, 175 Triangles, simulation 1,401,090 in 109 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 49 MB 634 MB STEP 193 MB 732 MB STL 70 MB 613 MB OBJ 146 MB 1.0 GB Visual GLB 36 MB 882 MB OBJ 109 MB 882 MB

363. antmicro-hdmi-mipi-bridge-hw

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.8	1.8	6.3	0.4 ms	9.4	0.4	0.9	0.3	21.8
Simulation, STEP	2.8	1.7	6.1	0.4 ms	9.6	5.9	0.8	0.3	27.2
Simulation, STL	3.0	1.7	5.6	0.4 ms	8.8	0.7	0.8	0.3	21.0
Simulation, OBJ	2.9	1.8	5.9	0.4 ms	9.0	9.2	0.8	0.3	29.8
Visual, GLB	2.8	1.6	5.8	0.5 ms	14.9	0.2	1.8	0.3	27.4
Visual, OBJ	2.8	1.7	6.0	0.5 ms	15.3	7.0	2.1	0.3	35.2

Board Repo: antmicro/hdmi-mipi-bridge Board: antmicro-hdmi-mipi-bridge-hw.kicad_pcb Complexity 404 / 1000 (size 274, features 130) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 111, 1,960, 312 Triangles, simulation 2,009,788 in 160 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 67 MB 813 MB STEP 298 MB 974 MB STL 101 MB 807 MB OBJ 209 MB 1.4 GB Visual GLB 49 MB 1.1 GB OBJ 152 MB 1.1 GB

364. icicle-hdmi-breakout

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.0	4.2	0.5 ms	3.6	0.1	0.4	0.2	9.8
Simulation, STEP	0.3	1.0	4.0	0.5 ms	3.4	2.9	0.4	0.2	12.3
Simulation, STL	0.3	1.0	4.1	0.5 ms	3.6	0.3	0.5	0.2	10.0
Simulation, OBJ	0.3	1.0	3.9	0.3 ms	3.5	5.2	0.5	0.2	14.7
Visual, GLB	0.3	1.1	4.1	0.4 ms	8.0	87 ms	0.6	0.2	14.4
Visual, OBJ	0.5	1.0	3.8	0.4 ms	7.7	3.0	0.7	0.3	17.1

Board Repo: antmicro/icicle-hdmi-breakout Board: icicle-hdmi-breakout.kicad_pcb Complexity 254 / 1000 (size 189, features 65) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 34, 1,178, 41 Triangles, simulation 851,176 in 64 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 29 MB 401 MB STEP 166 MB 464 MB STL 43 MB 404 MB OBJ 88 MB 637 MB Visual GLB 17 MB 457 MB OBJ 50 MB 468 MB

365. ict-baseboard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	4.6	2.7	10.7	0.6 ms	16.0	0.4	1.2	0.3	36.0
Simulation, STEP	4.4	2.6	10.6	1.0 ms	16.2	8.7	1.2	0.3	44.2
Simulation, STL	4.4	2.8	10.5	0.9 ms	16.1	1.0	1.3	0.3	36.4
Simulation, OBJ	4.9	2.8	11.0	0.6 ms	17.1	17.2	1.4	0.3	54.7
Visual, GLB	4.5	2.8	11.1	1 ms	24.7	0.3	3.1	0.3	46.9
Visual, OBJ	4.6	2.8	10.7	0.9 ms	26.4	10.9	3.4	0.3	59.3

Board Repo: antmicro/ict-baseboard Board: ict-baseboard.kicad_pcb Complexity 413 / 1000 (size 258, features 155) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text, knockout text, TrueType text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 206, 1,672, 214 Triangles, simulation 2,622,894 in 218 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 89 MB 1.0 GB STEP 384 MB 1.2 GB STL 131 MB 1.0 GB OBJ 276 MB 1.8 GB Visual GLB 60 MB 1.3 GB OBJ 185 MB 1.3 GB

366. ir-irradiance-probe

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.1	1.1	4.1	1 ms	3.5	0.2	0.5	0.4	11.9
Simulation, STEP	1.5	0.9	3.8	0.4 ms	3.5	2.9	0.5	0.3	13.4
Simulation, STL	1.8	1.0	4.7	0.4 ms	3.7	0.2	0.5	0.3	12.1
Simulation, OBJ	1.3	0.9	4.1	0.4 ms	3.7	5.0	0.5	0.3	15.8
Visual, GLB	1.6	1.0	4.3	0.3 ms	7.9	0.1	0.8	0.3	16.0
Visual, OBJ	1.3	0.9	3.6	0.4 ms	8.0	3.9	0.8	0.3	18.8

Board Repo: antmicro/infrared-irradiance-probe Board: ir-irradiance-probe.kicad_pcb Complexity 282 / 1000 (size 172, features 110) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 52, 330, 196 Triangles, simulation 735,330 in 43 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 26 MB 490 MB STEP 124 MB 484 MB STL 37 MB 482 MB OBJ 77 MB 563 MB Visual GLB 20 MB 532 MB OBJ 61 MB 578 MB

367. jetson-agx-csi-adapter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.5	2.2	7.7	0.7 ms	14.4	0.4	1.4	0.4	29.0
Simulation, STEP	2.6	2.2	7.5	0.8 ms	14.8	11.0	1.3	0.3	39.7
Simulation, STL	3.1	2.1	8.0	0.7 ms	14.5	1.0	1.3	0.4	30.4
Simulation, OBJ	2.8	2.4	8.6	0.9 ms	15.5	15.5	1.3	0.4	46.6
Visual, GLB	2.5	2.0	9.6	0.9 ms	30.8	0.4	3.4	0.3	49.0
Visual, OBJ	2.6	2.3	8.3	1 ms	27.3	13.6	4.2	0.4	58.6

Board Repo: antmicro/jetson-agx-csi-adapter Board: jetson-agx-csi-adapter.kicad_pcb Complexity 345 / 1000 (size 215, features 130) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 80, 2,929, 225 Triangles, simulation 2,205,664 in 193 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 74 MB 935 MB STEP 344 MB 1.1 GB STL 110 MB 935 MB OBJ 230 MB 1.5 GB Visual GLB 63 MB 1.2 GB OBJ 196 MB 1.4 GB

368. jetson-agx-thor-baseboard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	26.6	32.6	75.6	3 ms	106.5	5.8	16.9	1.1	265.1
Simulation, STEP	26.9	33.0	79.2	3 ms	106.7	60.6	17.0	1.1	324.4
Simulation, STL	27.1	33.4	78.6	3 ms	116.7	13.6	19.5	1.0	289.9
Simulation, OBJ									exceeded 11 GB on a 15 GB machine (stopped there, not a KESE failure); it will be run again on a machine with more memory
Visual, GLB	29.1	37.1	83.3	3 ms	333.1	2.5	26.7	0.8	512.8
Visual, OBJ	23.1	31.4	69.2	3 ms	284.4	67.0	21.0	0.7	496.9

Board Repo: antmicro/jetson-agx-thor-baseboard Board: jetson-agx-thor-baseboard.kicad_pcb Complexity 526 / 1000 (size 351, features 175) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, knockout text, TrueType text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 to 10th November 2026 Copper layers 10 File format KiCad 9 (20241229) Parts, tracks, vias 1,025, 22,645, 3,223 Triangles, simulation 32,687,176 in 1419 parts Verifier Simulation, OBJ: exceeded 11 GB on a 15 GB machine (stopped there, not a KESE failure); it will be run again on a machine with more memory Run again Visual, OBJ: failed in the corpus run, run again with the memory cap raised from 11 GB to 14.5 GB, and passed

File type File size Peak memory used Simulation GLB 1.1 GB 7.5 GB STEP 3.3 GB 9.2 GB STL 1.6 GB 7.3 GB OBJ – 11 GB Visual GLB 485 MB 8.6 GB OBJ 1.6 GB 11 GB

369. jetson-nano-baseboard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	6.9	6.5	15.4	1 ms	23.4	1.1	3.0	0.4	56.8
Simulation, STEP	7.1	6.2	15.8	1 ms	23.1	13.0	3.2	0.4	68.8
Simulation, STL	6.9	5.8	15.9	1 ms	24.8	2.2	3.1	0.4	59.3
Simulation, OBJ	7.5	7.2	16.7	1 ms	24.0	36.6	3.2	0.5	95.6
Visual, GLB	7.2	6.5	16.2	1 ms	53.8	0.5	4.9	0.3	89.4
Visual, OBJ	7.2	6.1	16.3	2 ms	52.3	17.1	5.0	0.3	104.3

Board Repo: antmicro/jetson-nano-baseboard Board: jetson-nano-baseboard.kicad_pcb Complexity 448 / 1000 (size 313, features 135) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 8 File format KiCad 9 (20241229) Parts, tracks, vias 326, 15,624, 794 Triangles, simulation 7,900,080 in 506 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 263 MB 2.0 GB STEP 948 MB 2.7 GB STL 395 MB 2.2 GB OBJ 871 MB 5.2 GB Visual GLB 130 MB 2.4 GB OBJ 440 MB 3.0 GB

370. jetson-orin-baseboard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	11.9	13.2	30.7	2 ms	53.6	2.4	7.0	0.6	119.4
Simulation, STEP	12.0	13.6	31.4	3 ms	54.3	28.5	7.8	0.6	148.2
Simulation, STL	11.9	13.6	31.1	3 ms	54.9	5.1	7.3	0.6	124.4
Simulation, OBJ	11.6	13.6	30.9	2 ms	53.8	86.9	7.4	0.7	205.0
Visual, GLB	12.4	13.5	33.0	3 ms	122.5	1.1	11.1	0.5	194.1
Visual, OBJ	11.8	13.2	31.7	2 ms	122.7	45.0	12.6	0.5	237.4

Board Repo: antmicro/jetson-orin-baseboard Board: jetson-orin-baseboard.kicad_pcb Complexity 522 / 1000 (size 327, features 195) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 8 File format KiCad 8 (20240108) Parts, tracks, vias 618, 14,181, 1,345 Triangles, simulation 13,533,484 in 817 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 455 MB 2.9 GB STEP 1.7 GB 4.4 GB STL 677 MB 2.9 GB OBJ 1.5 GB 8.6 GB Visual GLB 249 MB 4.2 GB OBJ 822 MB 5.5 GB

371. job-ict-bottom-board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.5	1.8	7.8	0.6 ms	6.8	0.3	0.9	0.3	20.3
Simulation, STEP	2.8	2.0	9.0	0.7 ms	7.2	5.7	0.9	0.3	27.8
Simulation, STL	2.8	2.1	8.2	0.7 ms	7.0	0.5	0.9	0.3	21.9
Simulation, OBJ	2.6	2.0	8.5	3 ms	7.1	9.1	1.0	0.3	30.6
Visual, GLB	2.5	2.0	8.0	0.8 ms	12.6	0.2	1.4	0.2	26.9
Visual, OBJ	2.6	1.8	8.0	0.7 ms	13.6	7.1	1.6	0.3	34.9

Board Repo: antmicro/job-ict-bottom-board Board: job-ict-bottom-board.kicad_pcb Complexity 323 / 1000 (size 173, features 150) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, knockout text, TrueType text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 93, 492, 64 Triangles, simulation 1,493,234 in 119 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 51 MB 653 MB STEP 219 MB 798 MB STL 75 MB 670 MB OBJ 155 MB 1.1 GB Visual GLB 37 MB 744 MB OBJ 111 MB 851 MB

372. job-ict-support-board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.4	1.5	0.4 ms	1.5	67 ms	0.2	0.2	4.1
Simulation, STEP	0.2	0.5	1.4	0.2 ms	1.5	1.5	0.2	0.3	5.5
Simulation, STL	0.3	0.4	1.3	0.2 ms	1.3	0.1	0.2	0.2	3.8
Simulation, OBJ	0.2	0.4	1.4	0.5 ms	1.5	1.9	0.2	0.2	5.8
Visual, GLB	0.2	0.4	1.4	0.8 ms	3.1	46 ms	0.4	0.2	5.8
Visual, OBJ	0.3	0.5	1.5	0.3 ms	3.0	1.2	0.4	0.2	7.0

Board Repo: antmicro/job-ict-support-board Board: job-ict-support-board.kicad_pcb Complexity 112 / 1000 (size 17, features 95) KESE features rounded, trapezoid or chamfered pads, filled zones, knockout text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 0, 0, 0 Triangles, simulation 434,326 in 38 parts Note no components Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 15 MB 331 MB STEP 66 MB 337 MB STL 22 MB 315 MB OBJ 44 MB 354 MB Visual GLB 10 MB 317 MB OBJ 30 MB 312 MB

373. jetson-orin-baseboard-oculink-expansion

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.0	1.2	4.5	0.7 ms	6.9	0.3	0.6	0.3	15.7
Simulation, STEP	2.3	1.2	4.1	0.5 ms	6.4	4.4	0.6	0.3	19.3
Simulation, STL	2.0	1.2	4.0	0.5 ms	6.1	0.5	0.6	0.3	14.7
Simulation, OBJ	1.9	1.1	4.3	0.5 ms	6.6	7.7	0.6	0.3	22.4
Visual, GLB	2.1	1.3	4.4	0.7 ms	15.5	0.2	1.9	0.3	25.6
Visual, OBJ	1.9	1.2	4.3	0.8 ms	15.6	5.8	2.0	0.3	31.2

Board Repo: antmicro/job-oculink-expansion Board: jetson-orin-baseboard-oculink-expansion.kicad_pcb Complexity 374 / 1000 (size 254, features 120) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper text, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 97, 1,265, 219 Triangles, simulation 1,861,222 in 153 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 64 MB 787 MB STEP 312 MB 930 MB STL 93 MB 801 MB OBJ 194 MB 1.3 GB Visual GLB 46 MB 984 MB OBJ 142 MB 1.1 GB

374. jetson-orin-baseboard-pcie-switch-expansion

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	8.9	6.4	15.3	1 ms	23.0	1.2	2.6	0.5	58.0
Simulation, STEP	8.3	6.3	15.9	1 ms	22.5	14.5	2.7	0.5	70.6
Simulation, STL	8.2	6.2	15.5	1 ms	22.4	2.5	2.6	0.5	57.8
Simulation, OBJ	8.3	6.2	15.7	1 ms	22.7	37.7	2.9	0.5	94.0
Visual, GLB	8.3	6.3	16.0	1 ms	53.4	0.6	6.4	0.4	91.4
Visual, OBJ	8.6	6.4	15.6	2 ms	54.1	22.8	6.6	0.4	114.5

Board Repo: antmicro/job-pcie-switch-expansion Board: jetson-orin-baseboard-pcie-switch-expansion.kicad_pcb Complexity 489 / 1000 (size 304, features 185) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 6 File format KiCad 10 (20260206) Parts, tracks, vias 297, 4,689, 779 Triangles, simulation 5,931,152 in 404 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 202 MB 1.9 GB STEP 759 MB 2.2 GB STL 297 MB 1.9 GB OBJ 632 MB 3.9 GB Visual GLB 122 MB 2.2 GB OBJ 396 MB 2.9 GB

375. jetson-orin-baseboard-storage-expansion

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.1	1.7	5.3	0.8 ms	7.1	0.3	0.8	0.3	17.6
Simulation, STEP	2.3	1.7	5.0	0.7 ms	6.9	4.8	0.7	0.3	21.8
Simulation, STL	2.3	1.6	5.1	0.9 ms	6.7	0.7	0.7	0.3	17.4
Simulation, OBJ	2.2	1.8	5.0	0.7 ms	6.8	8.9	0.7	0.3	25.8
Visual, GLB	2.4	1.7	5.2	0.7 ms	16.4	0.2	1.9	0.3	28.1
Visual, OBJ	2.3	1.6	5.1	0.8 ms	17.0	7.0	2.0	0.3	35.3

Board Repo: antmicro/job-storage-expansion Board: jetson-orin-baseboard-storage-expansion.kicad_pcb Complexity 411 / 1000 (size 251, features 160) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 88, 1,551, 378 Triangles, simulation 1,932,092 in 167 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 64 MB 850 MB STEP 274 MB 1.0 GB STL 97 MB 810 MB OBJ 200 MB 1.4 GB Visual GLB 48 MB 934 MB OBJ 149 MB 1.1 GB

376. k410t-devboard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	25.1	31.1	68.8	3 ms	92.3	6.0	16.1	1.2	240.7
Simulation, STEP	24.5	29.8	69.7	3 ms	92.5	49.7	16.0	1.1	283.2
Simulation, STL	23.7	29.2	68.6	3 ms	93.4	11.7	20.5	1.3	248.4
Simulation, OBJ									exceeded 11 GB on a 15 GB machine (stopped there, not a KESE failure); it will be run again on a machine with more memory
Visual, GLB	24.4	30.5	70.9	3 ms	256.2	2.1	18.5	0.7	403.3
Visual, OBJ	24.8	29.6	66.0	3 ms	265.3	62.1	19.9	0.8	468.5

Board Repo: antmicro/kintex-410t-devboard Board: k410t-devboard.kicad_pcb Complexity 497 / 1000 (size 367, features 130) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 10 File format KiCad 9 (20241229) Parts, tracks, vias 962, 19,907, 2,762 Triangles, simulation 29,401,472 in 1433 parts Verifier Simulation, OBJ: exceeded 11 GB on a 15 GB machine (stopped there, not a KESE failure); it will be run again on a machine with more memory

File type File size Peak memory used Simulation GLB 978 MB 6.3 GB STEP 2.9 GB 8.2 GB STL 1.5 GB 6.2 GB OBJ – 11 GB Visual GLB 430 MB 7.8 GB OBJ 1.5 GB 9.9 GB

377. kria-k26-devboard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	20.2	18.3	40.0	2 ms	55.9	3.6	7.6	0.7	146.4
Simulation, STEP	18.7	16.7	36.4	2 ms	54.0	31.5	7.5	0.7	165.6
Simulation, STL	18.7	17.3	38.3	2 ms	54.4	7.5	7.2	0.8	144.1
Simulation, OBJ	18.7	16.8	38.0	2 ms	54.6	101.3	7.9	0.8	238.1
Visual, GLB	19.1	17.9	42.9	2 ms	124.4	1.8	13.1	0.7	219.9
Visual, OBJ	18.7	18.1	39.4	2 ms	120.3	47.8	13.1	0.7	257.9

Board Repo: antmicro/kria-k26-devboard Board: kria-k26-devboard.kicad_pcb Complexity 491 / 1000 (size 336, features 155) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 8 File format KiCad 7 (20221018) Parts, tracks, vias 577, 20,506, 1,901 Triangles, simulation 15,836,218 in 822 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 527 MB 4.3 GB STEP 1.6 GB 5.2 GB STL 792 MB 4.0 GB OBJ 1.7 GB 10 GB Visual GLB 256 MB 4.6 GB OBJ 853 MB 5.8 GB

378. lpddr4-test-board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	12.7	9.9	20.3	1 ms	34.8	1.5	3.1	0.6	82.9
Simulation, STEP	12.9	10.4	20.3	1 ms	33.7	17.2	3.1	0.5	98.2
Simulation, STL	12.9	10.2	20.1	1 ms	33.7	3.6	3.1	0.6	84.1
Simulation, OBJ	13.0	9.9	19.3	1 ms	33.7	43.7	2.9	0.8	123.3
Visual, GLB	13.2	10.1	20.3	1 ms	65.6	0.8	7.1	0.5	117.6
Visual, OBJ	12.8	10.4	19.6	1 ms	64.9	23.1	6.8	0.5	138.0

Board Repo: antmicro/lpddr4-test-board Board: lpddr4-test-board.kicad_pcb Complexity 514 / 1000 (size 324, features 190) KESE features through vias, blind and buried vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 8 File format KiCad 9 (20241229) Parts, tracks, vias 445, 5,712, 1,214 Triangles, simulation 9,482,776 in 688 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 314 MB 2.6 GB STEP 1.0 GB 3.6 GB STL 474 MB 2.6 GB OBJ 1.0 GB 6.3 GB Visual GLB 171 MB 3.1 GB OBJ 569 MB 3.9 GB

379. lpddr4-testbed

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.9	1.8	7.4	0.9 ms	7.4	0.3	0.9	0.3	20.0
Simulation, STEP	1.9	1.9	7.5	0.8 ms	7.5	4.9	0.9	0.3	24.7
Simulation, STL	1.9	1.8	7.1	0.8 ms	7.4	0.6	0.8	0.3	20.0
Simulation, OBJ	1.8	1.8	7.3	0.8 ms	7.3	11.3	0.9	0.3	30.6
Visual, GLB	1.8	1.8	7.3	0.9 ms	15.5	0.2	1.4	0.3	28.2
Visual, OBJ	1.8	1.9	7.3	0.9 ms	15.0	6.5	1.4	0.2	34.1

Board Repo: antmicro/lpddr4-testbed Board: lpddr4-testbed.kicad_pcb Complexity 377 / 1000 (size 267, features 110) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper text, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 63, 1,498, 248 Triangles, simulation 2,042,424 in 275 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 69 MB 747 MB STEP 283 MB 897 MB STL 102 MB 840 MB OBJ 216 MB 1.4 GB Visual GLB 39 MB 844 MB OBJ 121 MB 932 MB

380. lpddr5-testbed

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	3.5	5.1	19.1	0.8 ms	21.5	0.9	2.8	0.4	53.2
Simulation, STEP	3.4	5.2	20.4	0.8 ms	21.8	12.4	2.8	0.4	66.4
Simulation, STL	3.6	5.2	19.7	0.8 ms	22.2	2.0	2.9	0.4	56.0
Simulation, OBJ	3.4	5.0	19.6	0.8 ms	22.5	28.8	2.8	0.4	82.5
Visual, GLB	3.5	5.1	19.5	0.8 ms	49.8	0.5	6.3	0.4	85.0
Visual, OBJ	3.5	5.0	19.9	0.9 ms	48.8	16.3	6.2	0.3	100.1

Board Repo: antmicro/lpddr5-testbed Board: lpddr5-testbed.kicad_pcb Complexity 417 / 1000 (size 302, features 115) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper text, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 152, 5,078, 590 Triangles, simulation 5,169,826 in 244 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 176 MB 1.5 GB STEP 766 MB 1.9 GB STL 259 MB 1.5 GB OBJ 555 MB 3.4 GB Visual GLB 100 MB 1.8 GB OBJ 323 MB 2.3 GB

381. antmicro-m2-oculink-adapter-hw

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	0.7	2.6	0.3 ms	3.8	0.1	0.4	0.3	8.5
Simulation, STEP	0.5	0.7	2.5	0.6 ms	4.1	2.9	0.4	0.2	11.3
Simulation, STL	0.5	0.7	2.4	0.3 ms	3.9	0.4	0.4	0.2	8.7
Simulation, OBJ	0.5	0.8	2.7	0.4 ms	3.8	4.5	0.4	0.3	13.0
Visual, GLB	0.5	0.7	2.6	0.4 ms	8.2	0.1	0.9	0.2	13.3
Visual, OBJ	0.5	0.7	2.6	0.3 ms	8.2	3.4	1.2	0.3	16.9

Board Repo: antmicro/m2-oculink-adapter Board: antmicro-m2-oculink-adapter-hw.kicad_pcb Complexity 296 / 1000 (size 181, features 115) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper text, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 19, 577, 183 Triangles, simulation 873,538 in 72 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 30 MB 440 MB STEP 132 MB 533 MB STL 44 MB 429 MB OBJ 89 MB 638 MB Visual GLB 22 MB 590 MB OBJ 67 MB 584 MB

382. m2-pcie-adapter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	0.5	2.2	0.4 ms	3.0	0.1	0.4	0.2	7.2
Simulation, STEP	0.6	0.5	2.1	0.3 ms	3.1	2.6	0.4	0.2	9.6
Simulation, STL	0.6	0.5	2.2	0.4 ms	3.0	0.2	0.4	0.2	7.1
Simulation, OBJ	0.6	0.6	2.2	0.4 ms	3.2	4.1	0.4	0.2	11.2
Visual, GLB	0.6	0.5	2.3	0.5 ms	7.3	91 ms	0.6	0.2	11.7
Visual, OBJ	0.6	0.5	2.2	0.3 ms	7.7	3.1	0.5	0.2	15.0

Board Repo: antmicro/m2-pcie-adapter Board: m2-pcie-adapter.kicad_pcb Complexity 288 / 1000 (size 178, features 110) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper text, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 16, 787, 92 Triangles, simulation 808,562 in 81 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 28 MB 497 MB STEP 142 MB 498 MB STL 40 MB 453 MB OBJ 83 MB 586 MB Visual GLB 21 MB 538 MB OBJ 63 MB 600 MB

383. m2-smart-iot-module

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.9	3.0	9.3	0.9 ms	11.7	0.5	1.4	0.3	27.1
Simulation, STEP	1.2	2.9	9.4	1 ms	12.1	9.5	1.4	0.3	36.9
Simulation, STL	1.3	3.2	9.9	1 ms	12.0	0.9	1.4	0.3	29.1
Simulation, OBJ	1.1	3.0	10.1	1 ms	12.6	19.5	1.5	0.4	48.2
Visual, GLB	1.2	2.9	9.7	0.9 ms	29.4	0.3	3.3	0.3	47.2
Visual, OBJ	0.9	2.8	10.0	1.0 ms	30.3	12.3	3.4	0.2	59.8

Board Repo: antmicro/m2-smart-iot-module Board: m2-smart-iot-module.kicad_pcb Complexity 393 / 1000 (size 268, features 125) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 10 (20260206) Parts, tracks, vias 195, 1,615, 435 Triangles, simulation 2,528,042 in 263 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 87 MB 817 MB STEP 423 MB 1.1 GB STL 126 MB 876 MB OBJ 271 MB 1.7 GB Visual GLB 61 MB 1.1 GB OBJ 190 MB 1.3 GB

384. machxo5-espi-debugger

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	6.3	4.0	12.4	1 ms	15.9	0.6	1.7	0.4	41.3
Simulation, STEP	6.3	4.0	12.7	1 ms	15.2	10.2	1.6	0.4	50.4
Simulation, STL	6.4	4.2	12.8	1 ms	17.5	1.3	1.9	0.4	44.5
Simulation, OBJ	7.0	5.0	13.5	2 ms	15.2	22.4	1.8	0.4	65.3
Visual, GLB	6.6	4.1	13.5	1 ms	36.2	0.4	3.3	0.4	64.5
Visual, OBJ	6.4	4.1	12.2	2 ms	34.6	14.4	3.4	0.3	75.5

Board Repo: antmicro/machx05-espi-debugger Board: machxo5-espi-debugger.kicad_pcb Complexity 461 / 1000 (size 291, features 170) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, knockout text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 6 File format KiCad 10 (20260206) Parts, tracks, vias 227, 2,121, 491 Triangles, simulation 3,681,402 in 482 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 122 MB 1.3 GB STEP 478 MB 1.5 GB STL 184 MB 1.3 GB OBJ 382 MB 2.4 GB Visual GLB 81 MB 1.5 GB OBJ 259 MB 1.9 GB

385. mec1723-espi-debugger

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	4.8	6.1	12.2	2 ms	19.0	1.0	3.1	0.4	46.6
Simulation, STEP	5.2	6.4	12.9	2 ms	19.5	12.8	2.8	0.5	60.1
Simulation, STL	4.7	6.1	12.2	1 ms	18.5	2.3	2.6	0.4	46.8
Simulation, OBJ	4.9	5.9	12.0	2 ms	19.3	33.2	2.6	0.4	78.3
Visual, GLB	4.9	5.9	12.8	1 ms	40.5	0.6	5.3	0.4	70.5
Visual, OBJ	5.0	6.5	12.9	2 ms	40.7	17.8	6.1	0.4	89.4

Board Repo: antmicro/mec1723-espi-debugger Board: mec1723-espi-debugger.kicad_pcb Complexity 471 / 1000 (size 301, features 170) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, knockout text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 8 File format KiCad 10 (20260206) Parts, tracks, vias 212, 3,327, 470 Triangles, simulation 4,657,560 in 302 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 158 MB 1.3 GB STEP 528 MB 1.6 GB STL 233 MB 1.3 GB OBJ 497 MB 3.0 GB Visual GLB 86 MB 1.6 GB OBJ 283 MB 2.0 GB

386. microphone-board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.1	0.3	0.1 ms	0.5	21 ms	60 ms	0.2	1.5
Simulation, STEP	0.2	0.1	0.3	0.1 ms	0.5	0.7	63 ms	0.2	2.3
Simulation, STL	0.3	0.1	0.3	0.1 ms	0.5	35 ms	63 ms	0.2	1.6
Simulation, OBJ	0.2	0.1	0.4	0.1 ms	0.6	0.6	70 ms	0.2	2.1
Visual, GLB	0.2	0.1	0.3	0.1 ms	1.1	15 ms	0.1	0.2	2.1
Visual, OBJ	0.2	0.1	0.3	0.1 ms	1.1	0.4	92 ms	0.2	2.4

Board Repo: antmicro/microphone-board Board: microphone-board.kicad_pcb Complexity 273 / 1000 (size 143, features 130) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 12, 60, 28 Triangles, simulation 147,964 in 16 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 5.1 MB 204 MB STEP 22 MB 212 MB STL 7.4 MB 211 MB OBJ 14 MB 201 MB Visual GLB 3.4 MB 163 MB OBJ 9.4 MB 163 MB

387. altera-modular-agilex-5-dc-scm

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	19.3	17.9	42.0	3 ms	79.3	3.6	10.6	0.9	173.6
Simulation, STEP	17.8	17.9	40.6	4 ms	77.0	37.8	10.8	0.8	202.6
Simulation, STL	18.6	17.8	40.1	2 ms	78.4	8.6	11.5	0.8	175.9
Simulation, OBJ	18.1	17.3	39.3	4 ms	75.9	94.2	11.1	0.8	256.7
Visual, GLB	17.3	16.6	38.2	3 ms	148.3	2.0	14.4	0.9	237.6
Visual, OBJ	17.9	18.0	39.9	3 ms	145.7	46.0	16.1	0.8	284.5

Board Repo: antmicro/modular-agilex5e-dc-scm Board: altera-modular-agilex-5-dc-scm.kicad_pcb Complexity 520 / 1000 (size 340, features 180) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 8 File format KiCad 10 (20260206) Parts, tracks, vias 782, 15,441, 1,606 Triangles, simulation 15,504,394 in 963 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 520 MB 3.6 GB STEP 1.8 GB 5.0 GB STL 775 MB 3.7 GB OBJ 1.7 GB 10 GB Visual GLB 282 MB 4.9 GB OBJ 934 MB 6.4 GB

388. myra-sip-interposer

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	0.9	3.9	0.4 ms	3.0	0.1	0.5	0.2	9.5
Simulation, STEP	0.7	0.9	4.0	0.3 ms	3.0	2.3	0.5	0.2	11.6
Simulation, STL	0.8	0.9	4.0	0.4 ms	3.0	0.3	0.6	0.2	9.8
Simulation, OBJ	0.9	0.9	4.1	0.4 ms	3.1	4.9	0.5	0.3	14.7
Visual, GLB	0.8	0.9	3.8	0.4 ms	6.4	75 ms	0.5	0.3	12.8
Visual, OBJ	0.8	1.0	4.0	0.6 ms	6.1	2.5	0.7	0.3	15.3

Board Repo: antmicro/myra-sip-interposer Board: myra-sip-interposer.kicad_pcb Complexity 405 / 1000 (size 240, features 165) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, stack-up, dielectric εr and tanδ, copper finish, castellated pads, plated board edge Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 31, 354, 164 Triangles, simulation 866,652 in 96 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 29 MB 377 MB STEP 103 MB 446 MB STL 43 MB 396 MB OBJ 86 MB 607 MB Visual GLB 15 MB 483 MB OBJ 46 MB 449 MB

389. oculink-to-10gbe-adapter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	12.0	6.8	23.7	2 ms	31.0	1.4	3.3	0.5	78.7
Simulation, STEP	12.3	7.2	23.6	2 ms	30.1	16.7	3.5	0.5	93.9
Simulation, STL	12.2	7.3	24.7	2 ms	31.7	3.6	3.5	0.5	83.5
Simulation, OBJ	12.7	7.5	26.7	3 ms	32.8	55.9	3.6	0.6	139.8
Visual, GLB	12.5	7.2	24.1	2 ms	101.6	0.7	7.4	0.4	153.9
Visual, OBJ	11.7	7.1	23.8	2 ms	99.8	28.1	7.6	0.4	178.5

Board Repo: antmicro/oculink-10gbe-adapter Board: oculink-to-10gbe-adapter.kicad_pcb Complexity 466 / 1000 (size 311, features 155) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 8 File format KiCad 9 (20241229) Parts, tracks, vias 460, 2,463, 1,174 Triangles, simulation 9,149,554 in 437 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 295 MB 2.7 GB STEP 962 MB 3.5 GB STL 458 MB 2.8 GB OBJ 950 MB 5.8 GB Visual GLB 167 MB 3.0 GB OBJ 537 MB 3.7 GB

390. oculink-to-pcie-adapter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	4.0	3.1	8.7	1 ms	10.1	0.5	1.1	0.3	27.9
Simulation, STEP	4.0	3.0	8.4	1 ms	10.1	6.2	1.0	0.3	33.0
Simulation, STL	4.2	3.0	8.4	2 ms	10.4	1.0	1.0	0.3	28.3
Simulation, OBJ	3.8	2.9	8.6	1 ms	9.6	14.9	1.0	0.3	41.1
Visual, GLB	3.9	2.8	8.4	1 ms	18.3	0.3	2.6	0.3	36.5
Visual, OBJ	3.9	3.0	8.7	1 ms	17.9	10.2	2.5	0.3	46.6

Board Repo: antmicro/oculink-pcie-adapter Board: oculink-to-pcie-adapter.kicad_pcb Complexity 366 / 1000 (size 221, features 145) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 144, 1,642, 583 Triangles, simulation 2,446,380 in 211 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 83 MB 934 MB STEP 283 MB 1.2 GB STL 122 MB 881 MB OBJ 253 MB 1.6 GB Visual GLB 56 MB 1.2 GB OBJ 172 MB 1.4 GB

391. optiga-tpm

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	0.4	1.7	0.3 ms	1.8	58 ms	0.2	0.2	4.8
Simulation, STEP	0.5	0.4	1.6	0.2 ms	1.8	2.0	0.2	0.2	6.7
Simulation, STL	0.5	0.4	1.6	0.2 ms	1.8	0.1	0.2	0.2	4.9
Simulation, OBJ	0.5	0.4	1.6	0.2 ms	1.8	1.9	0.3	0.3	6.9
Visual, GLB	0.5	0.4	1.6	0.2 ms	4.2	56 ms	0.3	0.2	7.2
Visual, OBJ	0.5	0.4	1.6	0.3 ms	4.0	1.3	0.2	0.2	8.4

Board Repo: antmicro/optiga-tpm Board: optiga-tpm.kicad_pcb Complexity 302 / 1000 (size 182, features 120) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text, knockout text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 10 (20260206) Parts, tracks, vias 22, 189, 27 Triangles, simulation 339,494 in 70 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 12 MB 302 MB STEP 77 MB 331 MB STL 17 MB 298 MB OBJ 35 MB 312 MB Visual GLB 8.5 MB 342 MB OBJ 25 MB 308 MB

392. bmc-reference-osm

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	12.1	11.9	40.1	2 ms	42.6	2.1	7.8	0.6	117.2
Simulation, STEP	12.7	12.3	40.8	2 ms	42.9	24.5	8.0	0.6	141.7
Simulation, STL	12.6	12.4	41.8	3 ms	43.3	4.1	7.8	0.7	122.7
Simulation, OBJ	12.3	12.5	41.1	3 ms	42.2	66.9	7.8	0.5	183.3
Visual, GLB	12.7	12.0	40.4	3 ms	141.6	1.0	7.3	0.5	215.6
Visual, OBJ	12.5	12.4	40.9	3 ms	143.6	33.7	7.2	0.5	250.9

Board Repo: antmicro/osm-l-bmc-som Board: bmc-reference-osm.kicad_pcb Complexity 553 / 1000 (size 338, features 215) KESE features through vias, blind and buried vias, microvias, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, TrueType text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 10 File format KiCad 9 (20241229) Parts, tracks, vias 376, 7,768, 1,763 Triangles, simulation 11,357,820 in 1082 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 371 MB 2.7 GB STEP 1.2 GB 3.8 GB STL 568 MB 2.8 GB OBJ 1.2 GB 7.2 GB Visual GLB 179 MB 3.4 GB OBJ 592 MB 4.0 GB

393. OV5640-dual-camera-board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.2	4.0	1 ms	4.8	0.2	0.7	0.2	11.6
Simulation, STEP	0.4	1.2	3.7	0.8 ms	4.9	3.8	0.7	0.3	14.9
Simulation, STL	0.4	1.2	3.6	0.6 ms	4.9	0.5	0.7	0.3	11.6
Simulation, OBJ	0.4	1.3	3.8	0.6 ms	5.0	7.2	0.7	0.3	18.7
Visual, GLB	0.4	1.1	3.7	0.7 ms	10.9	0.2	1.1	0.2	17.6
Visual, OBJ	0.4	1.2	3.7	0.6 ms	10.9	5.0	1.4	0.2	22.8

Board Repo: antmicro/ov5640-dual-camera-board Board: OV5640-dual-camera-board.kicad_pcb Complexity 308 / 1000 (size 203, features 105) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 6 (20211014) Parts, tracks, vias 82, 943, 234 Triangles, simulation 1,484,392 in 137 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 51 MB 688 MB STEP 231 MB 752 MB STL 74 MB 666 MB OBJ 154 MB 990 MB Visual GLB 34 MB 711 MB OBJ 103 MB 774 MB

394. ov9281-dual-camera-board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.2	1.5	4.6	0.6 ms	6.8	0.3	0.8	0.3	16.4
Simulation, STEP	2.1	1.5	4.6	0.7 ms	6.9	4.9	0.8	0.3	21.1
Simulation, STL	2.3	1.6	4.5	0.5 ms	6.9	0.5	0.7	0.2	16.7
Simulation, OBJ	2.1	1.4	4.4	0.6 ms	6.6	9.3	0.7	0.2	24.9
Visual, GLB	2.1	1.4	4.3	0.5 ms	13.7	0.2	1.4	0.3	23.5
Visual, OBJ	2.3	1.5	4.5	0.6 ms	13.9	6.8	1.5	0.3	30.7

Board Repo: antmicro/ov9281-camera-board Board: ov9281-dual-camera-board.kicad_pcb Complexity 329 / 1000 (size 204, features 125) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 77, 1,196, 233 Triangles, simulation 1,594,572 in 138 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 54 MB 770 MB STEP 244 MB 842 MB STL 80 MB 752 MB OBJ 164 MB 1.2 GB Visual GLB 39 MB 849 MB OBJ 119 MB 917 MB

395. pmod-i3c-driver

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.2	0.9	4.1	0.4 ms	3.9	0.2	0.6	0.3	11.1
Simulation, STEP	1.2	0.8	3.9	0.4 ms	3.9	3.4	0.4	0.3	14.0
Simulation, STL	1.1	0.9	3.8	0.3 ms	3.6	0.4	0.5	0.3	10.6
Simulation, OBJ	1.2	0.8	3.9	0.4 ms	3.6	4.9	0.6	0.3	15.2
Visual, GLB	1.2	0.8	4.0	0.4 ms	9.7	0.1	1.0	0.3	17.1
Visual, OBJ	1.1	0.9	3.8	0.9 ms	9.7	3.6	1.0	0.3	20.3

Board Repo: antmicro/pmod-i3c-driver Board: pmod-i3c-driver.kicad_pcb Complexity 304 / 1000 (size 189, features 115) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 62, 610, 83 Triangles, simulation 1,045,598 in 59 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 36 MB 504 MB STEP 162 MB 564 MB STL 52 MB 489 MB OBJ 106 MB 785 MB Visual GLB 23 MB 629 MB OBJ 69 MB 697 MB

396. pmod-i3c-sensor-board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.2	0.8	2.8	0.6 ms	3.4	0.2	0.4	0.2	8.9
Simulation, STEP	1.0	0.7	2.6	0.4 ms	3.3	2.7	0.4	0.3	11.0
Simulation, STL	1.1	0.7	2.6	0.3 ms	3.4	0.3	0.4	0.3	8.8
Simulation, OBJ	1.1	0.8	2.7	0.4 ms	3.4	4.2	0.4	0.3	12.9
Visual, GLB	1.1	0.8	2.7	0.4 ms	6.9	0.1	0.8	0.3	12.5
Visual, OBJ	1.1	0.8	2.6	0.7 ms	7.3	3.2	0.8	0.3	16.0

Board Repo: antmicro/pmod-i3c-sensor-board Board: pmod-i3c-sensor-board.kicad_pcb Complexity 311 / 1000 (size 191, features 120) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper text, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 75, 642, 71 Triangles, simulation 825,250 in 62 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 28 MB 415 MB STEP 135 MB 499 MB STL 41 MB 419 MB OBJ 84 MB 651 MB Visual GLB 21 MB 562 MB OBJ 62 MB 558 MB

397. antmicro-poe-to-usbc-pd-adapter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	5.2	4.2	15.9	0.8 ms	15.9	1.0	2.1	0.4	44.7
Simulation, STEP	4.7	4.0	15.8	2 ms	15.7	10.4	1.7	0.4	52.5
Simulation, STL	4.2	4.2	16.0	0.7 ms	15.2	2.1	1.8	0.4	43.8
Simulation, OBJ	4.9	4.5	15.8	2 ms	15.7	20.9	1.8	0.3	63.8
Visual, GLB	4.5	3.8	15.7	1 ms	40.2	0.4	4.7	0.4	69.7
Visual, OBJ	5.3	3.8	15.1	0.8 ms	39.7	14.1	7.0	0.4	85.5

Board Repo: antmicro/poe-usb-c-pd-converter Board: antmicro-poe-to-usbc-pd-adapter.kicad_pcb Complexity 394 / 1000 (size 269, features 125) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper text, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 230, 1,786, 767 Triangles, simulation 3,931,522 in 244 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 133 MB 1.3 GB STEP 481 MB 1.5 GB STL 197 MB 1.3 GB OBJ 411 MB 2.6 GB Visual GLB 83 MB 1.5 GB OBJ 261 MB 1.8 GB

398. polarfire-som

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	16.1	11.9	35.7	1 ms	57.0	3.3	8.5	0.6	133.1
Simulation, STEP	16.0	12.1	36.2	2 ms	60.9	33.6	9.5	0.6	168.8
Simulation, STL	15.2	11.0	32.7	2 ms	53.6	6.7	8.6	0.6	128.4
Simulation, OBJ	14.9	11.5	33.0	2 ms	54.4	98.5	8.8	0.7	221.9
Visual, GLB	15.7	11.4	33.1	2 ms	203.4	1.2	12.1	0.6	277.5
Visual, OBJ	15.9	12.0	35.1	2 ms	207.8	42.4	11.7	0.7	325.5

Board Repo: antmicro/polarfire-som Board: polarfire-som.kicad_pcb Complexity 517 / 1000 (size 357, features 160) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 14 File format KiCad 9 (20241229) Parts, tracks, vias 421, 13,972, 1,565 Triangles, simulation 15,008,058 in 793 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 476 MB 3.5 GB STEP 1.6 GB 4.7 GB STL 750 MB 3.4 GB OBJ 1.6 GB 9.4 GB Visual GLB 226 MB 4.3 GB OBJ 760 MB 4.9 GB

399. led-panel

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	10.6	7.8	23.3	2 ms	20.7	1.1	3.9	0.5	67.9
Simulation, STEP	10.2	7.2	24.0	2 ms	21.0	13.8	4.0	0.4	80.5
Simulation, STL	9.8	7.4	24.2	1 ms	21.1	2.1	4.2	0.5	69.2
Simulation, OBJ	10.3	7.5	23.2	0.8 ms	21.0	38.5	4.1	0.4	105.0
Visual, GLB	10.0	7.3	24.1	2 ms	32.6	0.5	3.8	0.4	78.7
Visual, OBJ	10.6	7.5	23.3	2 ms	33.9	15.3	3.8	0.4	94.8

Board Repo: antmicro/programmable-led-panel Board: led-panel.kicad_pcb Complexity 441 / 1000 (size 296, features 145) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, knockout text, TrueType text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 6 File format KiCad 8 (20240108) Parts, tracks, vias 294, 3,031, 741 Triangles, simulation 5,718,302 in 275 parts Note panel Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 194 MB 2.2 GB STEP 538 MB 2.4 GB STL 286 MB 2.1 GB OBJ 611 MB 3.9 GB Visual GLB 87 MB 1.6 GB OBJ 273 MB 2.1 GB

400. qomu-board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.4	3.2	0.4 ms	3.0	0.2	0.5	0.2	8.9
Simulation, STEP	0.3	1.4	3.4	0.4 ms	3.0	2.1	0.4	0.2	10.8
Simulation, STL	0.3	1.4	3.3	0.3 ms	3.0	0.2	0.4	0.2	8.9
Simulation, OBJ	0.3	1.4	3.6	0.3 ms	3.1	4.9	0.4	0.2	14.0
Visual, GLB	0.3	1.5	3.5	0.4 ms	6.8	76 ms	0.5	0.2	12.9
Visual, OBJ	0.3	1.4	3.4	0.3 ms	6.3	2.2	0.5	0.2	14.3

Board Repo: antmicro/qomu-dev-board Board: qomu-board.kicad_pcb Complexity 418 / 1000 (size 258, features 160) KESE features through vias, blind and buried vias, microvias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline Tested 9th November 2026 Copper layers 6 File format KiCad 5 (20171130) Parts, tracks, vias 56, 853, 194 Triangles, simulation 866,700 in 66 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 30 MB 353 MB STEP 118 MB 411 MB STL 43 MB 349 MB OBJ 89 MB 615 MB Visual GLB 15 MB 412 MB OBJ 44 MB 405 MB

401. quickfeather-board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.1	1.9	9.5	0.7 ms	8.2	0.3	0.9	0.3	23.2
Simulation, STEP	2.1	1.8	8.5	0.5 ms	8.0	4.7	0.9	0.3	26.2
Simulation, STL	2.1	1.8	8.3	0.9 ms	8.0	0.5	0.9	0.3	21.9
Simulation, OBJ	2.1	1.8	8.2	0.6 ms	8.2	10.7	0.9	0.3	32.1
Visual, GLB	2.2	1.8	8.4	0.6 ms	15.1	0.2	1.2	0.3	29.2
Visual, OBJ	2.1	1.8	8.3	0.6 ms	15.3	6.7	1.5	0.3	36.0

Board Repo: antmicro/quickfeather-dev-board Board: quickfeather-board.kicad_pcb Complexity 334 / 1000 (size 249, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 90, 1,689, 224 Triangles, simulation 1,752,598 in 158 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 60 MB 666 MB STEP 263 MB 799 MB STL 88 MB 674 MB OBJ 185 MB 1.3 GB Visual GLB 35 MB 796 MB OBJ 107 MB 906 MB

402. rpi-cm4-csi-adapter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.4	1.5	0.2 ms	1.8	78 ms	0.2	0.3	4.5
Simulation, STEP	0.2	0.4	1.5	0.2 ms	1.9	1.9	0.2	0.2	6.3
Simulation, STL	0.3	0.4	1.6	0.2 ms	2.0	0.1	0.2	0.3	4.9
Simulation, OBJ	0.2	0.4	1.4	0.3 ms	2.0	2.4	0.2	0.2	6.8
Visual, GLB	0.2	0.3	1.5	0.3 ms	4.5	52 ms	0.4	0.2	7.3
Visual, OBJ	0.2	0.3	1.4	0.2 ms	4.4	1.6	0.4	0.2	8.6

Board Repo: antmicro/raspberry-pi-cm4-csi-adapter Board: rpi-cm4-csi-adapter.kicad_pcb Complexity 227 / 1000 (size 172, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 6, 1,229, 38 Triangles, simulation 471,986 in 33 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 16 MB 297 MB STEP 93 MB 349 MB STL 24 MB 292 MB OBJ 48 MB 373 MB Visual GLB 11 MB 332 MB OBJ 32 MB 334 MB

403. rpi-led-flex-board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	1.5	0.3 ms	1.7	58 ms	0.2	0.2	4.1
Simulation, STEP	0.2	0.3	1.6	0.4 ms	1.8	1.6	0.2	0.2	5.7
Simulation, STL	0.2	0.3	1.5	0.2 ms	1.7	90 ms	0.2	0.2	4.1
Simulation, OBJ	0.2	0.3	1.6	0.2 ms	1.6	1.7	0.2	0.2	5.7
Visual, GLB	0.2	0.3	1.5	0.3 ms	2.7	44 ms	0.3	0.2	5.2
Visual, OBJ	0.2	0.3	1.5	0.2 ms	2.9	1.4	0.3	0.2	6.8

Board Repo: antmicro/rpi-led-flex-board Board: rpi-led-flex-board.kicad_pcb Complexity 245 / 1000 (size 190, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 27, 252, 43 Triangles, simulation 351,834 in 50 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 12 MB 272 MB STEP 64 MB 316 MB STL 18 MB 271 MB OBJ 35 MB 282 MB Visual GLB 9.5 MB 305 MB OBJ 27 MB 302 MB

404. scalenode-adapter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	2.5	9.1	0.9 ms	9.1	0.4	1.0	0.2	23.0
Simulation, STEP	0.7	2.5	8.9	0.8 ms	8.5	5.9	1.1	0.3	27.9
Simulation, STL	0.7	2.4	9.3	0.9 ms	9.0	0.9	1.1	0.2	23.7
Simulation, OBJ	0.6	2.3	9.3	0.8 ms	9.4	14.3	1.2	0.3	37.4
Visual, GLB	0.7	2.7	10.5	0.7 ms	20.6	0.2	2.4	0.3	37.4
Visual, OBJ	0.7	2.9	9.5	0.7 ms	20.0	9.2	2.4	0.3	45.0

Board Repo: antmicro/scalenode-adapter Board: scalenode-adapter.kicad_pcb Complexity 356 / 1000 (size 266, features 90) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 152, 2,106, 319 Triangles, simulation 2,397,452 in 181 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 84 MB 883 MB STEP 361 MB 985 MB STL 120 MB 888 MB OBJ 256 MB 1.6 GB Visual GLB 51 MB 944 MB OBJ 157 MB 1.1 GB

405. scalenode-cm4-baseboard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.7	2.5	7.9	0.8 ms	7.8	0.4	1.1	0.3	22.7
Simulation, STEP	2.6	2.5	7.7	0.9 ms	7.8	5.3	0.9	0.3	27.0
Simulation, STL	2.7	2.6	7.8	0.8 ms	7.7	0.9	0.9	0.3	22.8
Simulation, OBJ	2.9	2.7	7.9	0.9 ms	7.6	12.0	0.9	0.3	34.3
Visual, GLB	2.7	2.5	8.1	1 ms	21.9	0.3	3.4	0.3	39.1
Visual, OBJ	2.7	2.5	7.9	2 ms	22.0	8.1	3.1	0.3	46.6

Board Repo: antmicro/scalenode-cm4-baseboard Board: scalenode-cm4-baseboard.kicad_pcb Complexity 358 / 1000 (size 223, features 135) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper text, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 129, 2,743, 536 Triangles, simulation 2,773,950 in 292 parts Verifier Simulation, GLB: Verifier FAIL Simulation, STEP: Verifier FAIL Simulation, STL: Verifier FAIL Simulation, OBJ: Verifier FAIL Bad design Bad design according to KESE: copper of two nets on top of each other in the file, a short KiCad's DRC reports; U4 and U7 placed exactly on top of each other at (137.41, 83.21) mm: their TRIM pads, of two nets, coincide. KESE models what the file says, so the Verifier rightly finds the two nets' solids overlapping

File type File size Peak memory used Simulation GLB 97 MB 971 MB STEP 324 MB 1.1 GB STL 139 MB 920 MB OBJ 297 MB 2.0 GB Visual GLB 66 MB 1.3 GB OBJ 209 MB 1.5 GB

406. sdi-fiber-adapter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	3.4	1.8	6.4	0.8 ms	6.9	0.4	0.9	0.3	20.1
Simulation, STEP	3.3	2.0	6.4	0.7 ms	7.1	4.9	0.8	0.3	24.9
Simulation, STL	3.4	2.0	6.2	0.9 ms	7.4	0.7	0.9	0.3	20.9
Simulation, OBJ	3.8	2.1	6.8	1 ms	7.3	11.7	0.9	0.4	33.0
Visual, GLB	3.5	2.3	6.5	1.0 ms	18.7	0.2	2.1	0.3	33.5
Visual, OBJ	3.7	2.0	6.3	3 ms	17.8	7.0	2.2	0.3	39.4

Board Repo: antmicro/sdi-fiber-adapter Board: sdi-fiber-adapter.kicad_pcb Complexity 408 / 1000 (size 263, features 145) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper text, knockout text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 183, 1,386, 268 Triangles, simulation 2,048,802 in 137 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 71 MB 889 MB STEP 308 MB 988 MB STL 102 MB 923 MB OBJ 215 MB 1.4 GB Visual GLB 47 MB 1.0 GB OBJ 145 MB 1.1 GB

407. sdi-mipi-bridge

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	4.7	5.5	14.3	0.9 ms	14.6	0.7	1.7	0.4	41.9
Simulation, STEP	4.9	5.4	13.6	0.9 ms	14.7	9.0	1.5	0.4	49.4
Simulation, STL	4.8	5.4	14.6	0.9 ms	14.6	1.2	1.6	0.4	42.5
Simulation, OBJ	4.7	5.3	13.9	0.6 ms	14.6	23.9	1.5	0.4	64.3
Visual, GLB	4.7	5.4	14.0	0.9 ms	27.3	0.4	2.8	0.3	54.8
Visual, OBJ	4.4	5.4	15.2	1 ms	28.3	12.2	2.9	0.3	68.7

Board Repo: antmicro/sdi-mipi-bridge-hw Board: sdi-mipi-bridge.kicad_pcb Complexity 390 / 1000 (size 300, features 90) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 6 File format KiCad 7 (20221018) Parts, tracks, vias 166, 4,789, 374 Triangles, simulation 3,614,688 in 191 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 125 MB 1.1 GB STEP 535 MB 1.4 GB STL 181 MB 1.1 GB OBJ 388 MB 2.5 GB Visual GLB 69 MB 1.5 GB OBJ 218 MB 1.6 GB

408. sdi-mipi-video-converter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	8.8	8.2	21.0	2 ms	29.5	1.8	4.2	0.5	74.0
Simulation, STEP	8.5	7.4	20.0	1 ms	29.3	18.4	4.3	0.6	88.4
Simulation, STL	8.2	7.1	20.6	1 ms	30.2	3.5	4.5	0.5	74.6
Simulation, OBJ	8.8	7.5	20.5	3 ms	30.5	45.2	4.0	0.5	117.1
Visual, GLB	8.2	7.2	19.4	1 ms	76.9	0.9	9.1	0.5	122.2
Visual, OBJ	8.3	7.3	19.9	2 ms	74.4	26.3	10.1	0.5	147.0

Board Repo: antmicro/sdi-mipi-video-converter-hw Board: sdi-mipi-video-converter.kicad_pcb Complexity 469 / 1000 (size 329, features 140) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper text, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 8 File format KiCad 9 (20241229) Parts, tracks, vias 327, 8,337, 1,093 Triangles, simulation 8,040,594 in 419 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 259 MB 2.1 GB STEP 908 MB 3.0 GB STL 402 MB 2.1 GB OBJ 840 MB 5.1 GB Visual GLB 157 MB 2.8 GB OBJ 515 MB 3.6 GB

409. si-simulation-test-board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.8	0.8	3.8	0.2 ms	3.6	0.2	0.4	0.2	11.7
Simulation, STEP	2.8	0.8	4.0	0.3 ms	3.3	2.3	0.4	0.3	13.8
Simulation, STL	2.8	0.8	3.9	0.1 ms	3.3	0.3	0.4	0.3	11.7
Simulation, OBJ	2.7	0.8	4.1	0.4 ms	3.3	4.7	0.4	0.3	16.2
Visual, GLB	2.8	0.8	3.8	0.3 ms	6.9	84 ms	0.6	0.3	15.4
Visual, OBJ	2.6	0.8	3.9	0.4 ms	6.9	2.6	0.6	0.3	17.7

Board Repo: antmicro/signal-integrity-test-board Board: si-simulation-test-board.kicad_pcb Complexity 277 / 1000 (size 182, features 95) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 6 (20211014) Parts, tracks, vias 27, 189, 252 Triangles, simulation 1,024,056 in 26 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 33 MB 533 MB STEP 110 MB 584 MB STL 51 MB 561 MB OBJ 102 MB 749 MB Visual GLB 17 MB 545 MB OBJ 52 MB 545 MB

410. sc606-baseboard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	13.4	8.8	23.5	3 ms	33.7	1.6	4.3	0.7	85.8
Simulation, STEP	13.8	9.5	23.3	4 ms	34.6	18.6	4.4	0.6	104.8
Simulation, STL	12.4	8.9	23.7	3 ms	35.7	3.2	4.1	0.6	88.5
Simulation, OBJ	13.9	9.1	23.6	3 ms	34.8	46.6	5.1	0.7	133.7
Visual, GLB	14.6	10.0	25.0	3 ms	92.7	0.9	8.9	0.5	152.6
Visual, OBJ	13.7	9.2	25.2	2 ms	91.2	28.8	8.7	0.6	177.4

Board Repo: antmicro/snapdragon-625-baseboard Board: sc606-baseboard.kicad_pcb Complexity 470 / 1000 (size 315, features 155) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 6 File format KiCad 7 (20221018) Parts, tracks, vias 530, 8,510, 930 Triangles, simulation 7,974,702 in 672 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 269 MB 2.6 GB STEP 1.1 GB 3.0 GB STL 399 MB 2.6 GB OBJ 850 MB 5.3 GB Visual GLB 170 MB 3.0 GB OBJ 550 MB 3.7 GB

411. sa800u-baseboard-hw

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	12.4	9.7	21.6	3 ms	34.6	1.7	3.7	0.6	84.2
Simulation, STEP	12.1	9.6	20.2	2 ms	33.4	18.6	3.9	0.6	98.4
Simulation, STL	11.8	9.8	19.9	4 ms	33.2	3.3	3.7	0.6	82.3
Simulation, OBJ	12.2	9.8	20.4	3 ms	33.2	46.3	3.9	0.5	126.4
Visual, GLB	12.2	9.5	20.3	3 ms	76.9	1.0	8.5	0.4	129.0
Visual, OBJ	12.3	9.8	20.5	1 ms	78.2	25.9	8.8	0.4	155.9

Board Repo: antmicro/snapdragon-845-baseboard Board: sa800u-baseboard-hw.kicad_pcb Complexity 459 / 1000 (size 319, features 140) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, drill offsets, filled zones, copper drawings, copper text, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 6 File format KiCad 6 (20211014) Parts, tracks, vias 474, 13,038, 992 Triangles, simulation 8,203,048 in 683 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 275 MB 2.5 GB STEP 1.1 GB 2.9 GB STL 410 MB 2.4 GB OBJ 881 MB 5.4 GB Visual GLB 166 MB 2.9 GB OBJ 538 MB 3.8 GB

412. snickerdoodle-hdmi-breakout

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.0	3.7	0.4 ms	3.4	0.1	0.4	0.2	9.3
Simulation, STEP	0.3	1.0	3.6	0.5 ms	3.4	2.6	0.4	0.2	11.6
Simulation, STL	0.3	1.0	3.5	0.2 ms	3.6	0.2	0.4	0.2	9.3
Simulation, OBJ	0.3	1.0	3.6	0.3 ms	3.6	4.4	0.4	0.2	13.7
Visual, GLB	0.3	1.0	3.7	0.3 ms	7.7	90 ms	0.6	0.2	13.6
Visual, OBJ	0.4	1.0	3.7	0.4 ms	7.9	3.0	0.7	0.3	16.9

Board Repo: antmicro/snickerdoodle-hdmi-breakout Board: snickerdoodle-hdmi-breakout.kicad_pcb Complexity 289 / 1000 (size 199, features 90) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 37, 1,980, 66 Triangles, simulation 737,764 in 70 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 26 MB 412 MB STEP 149 MB 478 MB STL 37 MB 422 MB OBJ 77 MB 573 MB Visual GLB 17 MB 506 MB OBJ 52 MB 512 MB

413. sodimm-ddr5-tester

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	17.8	24.3	38.1	3 ms	82.2	5.9	12.7	1.1	182.0
Simulation, STEP	18.6	23.7	39.4	2 ms	81.7	39.0	13.5	1.0	216.9
Simulation, STL	17.2	24.1	37.2	2 ms	79.5	10.8	13.0	0.9	182.7
Simulation, OBJ									exceeded 11 GB on a 15 GB machine (stopped there, not a KESE failure); it will be run again on a machine with more memory
Visual, GLB	18.4	24.0	37.5	2 ms	146.8	1.4	15.9	0.7	244.8
Visual, OBJ	18.5	24.5	38.6	7 ms	142.6	46.5	16.0	0.9	287.6

Board Repo: antmicro/sodimm-ddr5-tester Board: sodimm-ddr5-tester.kicad_pcb Complexity 538 / 1000 (size 358, features 180) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, curved board outline, TrueType text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 12 File format KiCad 9 (20241229) Parts, tracks, vias 546, 16,830, 2,115 Triangles, simulation 23,485,012 in 784 parts Verifier Simulation, OBJ: exceeded 11 GB on a 15 GB machine (stopped there, not a KESE failure); it will be run again on a machine with more memory

File type File size Peak memory used Simulation GLB 768 MB 5.0 GB STEP 2.0 GB 6.8 GB STL 1.2 GB 5.1 GB OBJ – 11 GB Visual GLB 269 MB 5.4 GB OBJ 940 MB 6.7 GB

414. stm32h7-hdmi-board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	17.5	19.3	51.8	5 ms	70.5	4.8	13.1	0.8	177.7
Simulation, STEP	16.0	19.6	50.3	4 ms	70.8	43.3	13.6	0.8	214.6
Simulation, STL	16.7	19.2	52.5	3 ms	74.0	9.2	12.9	1.0	185.4
Simulation, OBJ	11.8	15.5	42.2	3 ms	56.4	84.6	10.3	0.7	221.6
Visual, GLB	16.6	18.2	51.3	3 ms	217.9	1.8	16.4	0.7	323.0
Visual, OBJ	15.8	18.4	49.0	4 ms	198.6	55.6	16.0	0.7	354.1

Board Repo: antmicro/stm32h7-hdmi-board Board: stm32h7-hdmi-board.kicad_pcb Complexity 521 / 1000 (size 351, features 170) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, knockout text, TrueType text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 to 10th November 2026 Copper layers 8 File format KiCad 9 (20241229) Parts, tracks, vias 749, 15,474, 1,703 Triangles, simulation 17,829,614 in 925 parts Verifier PASS in all six runs Run again Simulation, OBJ: failed in the corpus run, run again with the memory cap raised from 11 GB to 14.5 GB, and passed

File type File size Peak memory used Simulation GLB 595 MB 4.0 GB STEP 2.0 GB 5.2 GB STL 892 MB 4.1 GB OBJ 1.9 GB 11 GB Visual GLB 290 MB 5.1 GB OBJ 944 MB 6.1 GB

415. stm32h7-hdmi-board-sodimm-module

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	3.6	2.3	4.1	1 ms	10.2	0.5	1.0	0.4	22.1
Simulation, STEP	3.5	2.1	4.0	1 ms	10.4	6.8	1.0	0.3	28.1
Simulation, STL	3.4	2.0	4.0	0.9 ms	10.2	1.0	1.1	0.4	22.0
Simulation, OBJ	3.4	2.4	4.2	1.0 ms	10.5	12.7	1.1	0.4	34.6
Visual, GLB	3.2	2.1	4.1	1 ms	21.0	0.3	2.9	0.3	33.9
Visual, OBJ	3.6	2.1	4.1	1.0 ms	21.1	9.4	3.2	0.3	43.7

Board Repo: antmicro/stm32h7-hdmi-board-sodimm Board: stm32h7-hdmi-board-sodimm-module.kicad_pcb Complexity 389 / 1000 (size 274, features 115) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 6 File format KiCad 10 (20260206) Parts, tracks, vias 86, 5,173, 247 Triangles, simulation 2,444,492 in 235 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 83 MB 894 MB STEP 354 MB 1.1 GB STL 122 MB 870 MB OBJ 258 MB 1.7 GB Visual GLB 59 MB 1.2 GB OBJ 183 MB 1.4 GB

416. thunderbolt-to-10gbe-adapter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	18.7	11.1	35.4	2 ms	43.8	2.6	6.3	0.7	118.6
Simulation, STEP	18.6	9.8	32.6	3 ms	43.5	26.6	6.0	0.8	138.0
Simulation, STL	19.7	9.6	33.6	3 ms	46.9	5.1	6.3	0.7	121.8
Simulation, OBJ	20.2	10.2	34.4	2 ms	46.8	76.4	6.5	0.8	195.2
Visual, GLB	20.0	9.8	34.1	2 ms	151.6	1.3	9.7	0.6	227.0
Visual, OBJ	19.3	10.1	34.1	3 ms	154.0	41.4	10.1	0.7	269.7

Board Repo: antmicro/thunderbolt-10gbe-adapter Board: thunderbolt-to-10gbe-adapter.kicad_pcb Complexity 463 / 1000 (size 323, features 140) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 8 File format KiCad 9 (20241229) Parts, tracks, vias 652, 5,595, 1,411 Triangles, simulation 11,099,384 in 620 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 358 MB 3.3 GB STEP 1.3 GB 4.1 GB STL 555 MB 3.3 GB OBJ 1.2 GB 7.1 GB Visual GLB 216 MB 3.9 GB OBJ 708 MB 5.0 GB

417. thunderbolt-gpu-adapter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	8.4	7.5	23.2	1 ms	28.0	1.4	3.5	0.5	72.6
Simulation, STEP	7.7	6.9	22.9	2 ms	28.3	14.7	3.5	0.7	84.7
Simulation, STL	7.6	7.0	24.0	2 ms	28.8	3.2	3.9	0.5	75.0
Simulation, OBJ	8.3	7.4	22.8	2 ms	29.1	41.0	3.5	0.6	112.7
Visual, GLB	8.6	7.1	23.8	3 ms	77.0	0.8	8.5	0.5	126.3
Visual, OBJ	8.2	7.3	23.4	1 ms	79.2	23.1	8.6	0.5	150.3

Board Repo: antmicro/thunderbolt-gpu-adapter Board: thunderbolt-gpu-adapter.kicad_pcb Complexity 433 / 1000 (size 293, features 140) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 6 File format KiCad 8 (20240108) Parts, tracks, vias 344, 4,545, 1,092 Triangles, simulation 7,315,338 in 378 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 245 MB 1.9 GB STEP 811 MB 2.6 GB STL 366 MB 1.9 GB OBJ 779 MB 4.7 GB Visual GLB 139 MB 2.5 GB OBJ 448 MB 3.0 GB

418. thunderbolt-pcie-adapter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	6.8	5.5	18.5	0.9 ms	21.0	1.2	2.6	0.4	56.0
Simulation, STEP	6.7	5.3	18.8	1 ms	22.2	12.8	2.5	0.5	68.7
Simulation, STL	6.7	5.3	16.9	1.0 ms	20.7	2.2	2.6	0.4	54.8
Simulation, OBJ	6.7	4.9	17.7	1.0 ms	22.0	39.5	2.5	0.4	93.5
Visual, GLB	7.1	5.3	17.5	1 ms	58.4	0.5	5.6	0.3	94.7
Visual, OBJ	7.0	5.5	17.7	0.9 ms	62.7	21.2	7.4	0.4	121.8

Board Repo: antmicro/thunderbolt-pcie-adapter Board: thunderbolt-pcie-adapter.kicad_pcb Complexity 438 / 1000 (size 283, features 155) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, curved board outline, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 6 File format KiCad 7 (20221018) Parts, tracks, vias 250, 2,631, 833 Triangles, simulation 5,556,214 in 286 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 186 MB 1.9 GB STEP 592 MB 2.1 GB STL 278 MB 1.9 GB OBJ 588 MB 3.6 GB Visual GLB 103 MB 2.1 GB OBJ 332 MB 2.3 GB

419. usb-c-power-adapter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.5	1.1	3.8	0.6 ms	4.0	0.2	0.4	0.2	12.2
Simulation, STEP	2.3	1.0	3.7	0.4 ms	3.7	3.1	0.5	0.3	14.5
Simulation, STL	2.2	1.1	3.8	0.6 ms	3.6	0.4	0.5	0.3	11.9
Simulation, OBJ	2.5	1.1	3.9	0.6 ms	3.8	5.7	0.5	0.2	17.8
Visual, GLB	2.2	1.0	3.8	0.4 ms	9.1	0.1	1.2	0.3	17.9
Visual, OBJ	2.1	1.1	3.9	0.3 ms	9.3	3.9	1.4	0.3	22.1

Board Repo: antmicro/usb-c-power-adapter Board: usb-c-power-adapter.kicad_pcb Complexity 332 / 1000 (size 202, features 130) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 108, 600, 229 Triangles, simulation 1,245,326 in 84 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 43 MB 567 MB STEP 174 MB 626 MB STL 62 MB 549 MB OBJ 128 MB 929 MB Visual GLB 28 MB 736 MB OBJ 85 MB 711 MB

420. video-latency-testing-probe

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.4	0.9	2.6	0.4 ms	3.4	0.2	0.6	0.3	10.4
Simulation, STEP	2.2	0.9	2.3	0.6 ms	3.5	2.8	0.5	0.3	12.5
Simulation, STL	2.0	0.9	2.4	0.6 ms	3.6	0.3	0.5	0.3	10.0
Simulation, OBJ	2.3	1.0	2.3	0.4 ms	3.6	5.9	0.5	0.2	15.8
Visual, GLB	2.1	0.9	2.7	0.4 ms	10.1	0.1	0.6	0.3	16.8
Visual, OBJ	2.0	0.9	2.5	0.6 ms	10.2	3.5	0.7	0.3	20.0

Board Repo: antmicro/video-latency-testing-probe Board: video-latency-testing-probe.kicad_pcb Complexity 365 / 1000 (size 250, features 115) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 86, 1,028, 128 Triangles, simulation 1,121,652 in 114 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 38 MB 556 MB STEP 159 MB 599 MB STL 56 MB 558 MB OBJ 114 MB 840 MB Visual GLB 22 MB 630 MB OBJ 68 MB 637 MB

421. video-booster-board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	3.0	9.1	1 ms	8.1	0.3	1.1	0.3	22.3
Simulation, STEP	0.5	2.7	8.6	0.7 ms	8.1	5.3	1.1	0.3	26.6
Simulation, STL	0.5	3.0	8.9	0.8 ms	8.0	0.8	1.0	0.3	22.4
Simulation, OBJ	0.5	2.8	8.4	0.7 ms	8.0	10.6	1.1	0.3	31.6
Visual, GLB	0.5	2.8	8.4	0.8 ms	17.2	0.2	2.0	0.3	31.4
Visual, OBJ	0.5	2.6	8.4	0.8 ms	17.7	7.1	2.1	0.3	38.8

Board Repo: antmicro/video-signal-booster-board Board: video-booster-board.kicad_pcb Complexity 361 / 1000 (size 271, features 90) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 141, 2,792, 242 Triangles, simulation 2,129,152 in 151 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 74 MB 788 MB STEP 340 MB 876 MB STL 106 MB 748 MB OBJ 229 MB 1.5 GB Visual GLB 45 MB 907 MB OBJ 138 MB 1.0 GB

422. vna-se-probe

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	96 ms	0.3	0.1 ms	0.5	14 ms	55 ms	0.2	1.4
Simulation, STEP	0.2	0.1	0.3	0.1 ms	0.6	0.7	49 ms	0.2	2.2
Simulation, STL	0.2	95 ms	0.3	0.1 ms	0.5	19 ms	65 ms	0.2	1.5
Simulation, OBJ	0.2	0.1	0.3	0.1 ms	0.5	0.5	55 ms	0.2	1.8
Visual, GLB	0.2	0.1	0.4	0.1 ms	1.1	12 ms	64 ms	0.2	2.1
Visual, OBJ	0.2	0.1	0.4	0.1 ms	1.2	0.3	60 ms	0.2	2.5

Board Repo: antmicro/vna-se-probe Board: vna-se-probe.kicad_pcb Complexity 241 / 1000 (size 116, features 125) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, stack-up, dielectric εr and tanδ, castellated pads Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 2, 5, 23 Triangles, simulation 90,012 in 17 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 3.1 MB 181 MB STEP 9.3 MB 184 MB STL 4.5 MB 184 MB OBJ 8.6 MB 183 MB Visual GLB 1.8 MB 162 MB OBJ 5.1 MB 163 MB

423. ATMEGA328_Motor_Board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	2.4	12.3	0.6 ms	9.7	0.4	1.2	0.3	27.0
Simulation, STEP	0.8	2.6	11.4	0.5 ms	9.4	6.8	1.1	0.3	32.3
Simulation, STL	0.8	2.5	11.9	1 ms	9.8	0.8	1.2	0.3	27.3
Simulation, OBJ	0.7	2.5	12.1	0.5 ms	10.0	11.8	1.3	0.3	38.6
Visual, GLB	0.7	2.5	12.0	0.5 ms	24.8	0.3	3.6	0.3	44.3
Visual, OBJ	0.7	2.5	11.5	0.5 ms	23.7	10.4	3.7	0.3	53.0

Board Repo: AntonioMR/ATMEGA328-Motor-Board Board: ATMEGA328_Motor_Board.kicad_pcb Folder pcb Complexity 285 / 1000 (size 250, features 35) KESE features through vias, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 4 (4) Parts, tracks, vias 171, 4,134, 136 Triangles, simulation 2,315,194 in 137 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 82 MB 823 MB STEP 478 MB 1.1 GB STL 116 MB 804 MB OBJ 248 MB 1.6 GB Visual GLB 71 MB 1.2 GB OBJ 220 MB 1.5 GB

424. pcb

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	2.8	11.6	2 ms	11.3	0.5	2.0	0.3	29.4
Simulation, STEP	0.7	2.8	11.1	2 ms	11.0	7.1	1.8	0.3	34.9
Simulation, STL	0.7	2.6	10.8	1 ms	11.2	1.0	1.9	0.3	28.5
Simulation, OBJ	0.7	2.7	11.0	2 ms	10.9	13.3	1.8	0.3	40.5
Visual, GLB	0.7	2.6	10.7	1 ms	22.4	0.3	2.7	0.3	39.7
Visual, OBJ	0.7	2.8	11.3	2 ms	23.6	9.3	3.0	0.3	51.0

Board Repo: apertus-open-source-cinema/axiom-micro-mainboard Board: pcb.kicad_pcb Folder pcb Complexity 270 / 1000 (size 215, features 55) KESE features through vias, slotted holes, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 83, 2,555, 310 Triangles, simulation 2,695,538 in 165 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 92 MB 853 MB STEP 376 MB 1.1 GB STL 135 MB 864 MB OBJ 282 MB 1.8 GB Visual GLB 61 MB 1.1 GB OBJ 189 MB 1.3 GB

425. NxtPX4

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	1.5	5.8	0.4 ms	6.0	0.3	0.8	0.2	15.1
Simulation, STEP	0.6	1.5	5.8	0.8 ms	6.1	4.9	0.9	0.2	20.0
Simulation, STL	0.6	1.6	5.9	0.4 ms	5.9	0.5	0.9	0.3	15.5
Simulation, OBJ	0.6	1.5	6.4	0.4 ms	6.3	9.9	1.0	0.3	25.9
Visual, GLB	0.6	1.6	5.8	0.4 ms	18.5	0.2	1.3	0.3	28.3
Visual, OBJ	0.6	1.6	6.0	0.4 ms	17.9	6.2	1.2	0.2	33.8

Board Repo: ardupilot/hardware Board: NxtPX4.kicad_pcb Folder HKUST-UAV-Group / NxtPX4v2 Complexity 393 / 1000 (size 263, features 130) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, TrueType text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 122, 1,193, 296 Triangles, simulation 1,917,514 in 147 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 65 MB 648 MB STEP 281 MB 793 MB STL 96 MB 642 MB OBJ 200 MB 1.3 GB Visual GLB 42 MB 809 MB OBJ 130 MB 993 MB

426. Sparky2

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	0.4	99 ms	0.2 ms	76 ms	2 ms	11 ms	0.3	1.3
Simulation, STEP	0.3	0.4	0.1	0.1 ms	72 ms	90 ms	11 ms	0.3	1.3
Simulation, STL	0.3	0.4	0.1	0.1 ms	63 ms	2 ms	8 ms	0.2	1.1
Simulation, OBJ	0.3	0.4	0.1	0.1 ms	73 ms	23 ms	13 ms	0.2	1.1
Visual, GLB	0.3	0.4	0.1	0.1 ms	0.1	2 ms	17 ms	0.2	1.2
Visual, OBJ	0.3	0.4	0.1	0.2 ms	0.1	17 ms	15 ms	0.2	1.3

Board Repo: ardupilot/hardware Board: Sparky2.kicad_pcb Folder TauLabs-Sparky / sparky2 / hw / kicad Complexity 241 / 1000 (size 196, features 45) KESE features through vias, copper drawings, copper text, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 4 (4) Parts, tracks, vias 78, 864, 79 Triangles, simulation 3,856 in 9 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 143 kB 82 MB STEP 895 kB 82 MB STL 194 kB 82 MB OBJ 374 kB 82 MB Visual GLB 117 kB 82 MB OBJ 281 kB 82 MB

427. motherboard-hk10

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	4.9	28.8	1 ms	21.9	0.9	2.2	0.4	59.7
Simulation, STEP	0.7	4.8	28.2	1 ms	22.6	16.2	2.4	0.4	75.3
Simulation, STL	0.7	4.9	27.6	2 ms	21.7	1.8	2.0	0.4	59.1
Simulation, OBJ	0.6	4.8	28.7	1 ms	21.5	29.7	2.1	0.4	87.8
Visual, GLB	0.7	4.9	27.8	1 ms	25.7	0.4	3.4	0.3	63.2
Visual, OBJ	0.7	4.8	28.7	2 ms	27.2	12.9	3.5	0.3	78.3

Board Repo: artemisamsx/motherboard-hk10 Board: motherboard-hk10.kicad_pcb Complexity 88 / 1000 (size 68, features 20) KESE features rounded, trapezoid or chamfered pads, drill offsets Tested 9th November 2026 Copper layers 2 File format KiCad 10 (20260206) Parts, tracks, vias 111, 0, 0 Triangles, simulation 4,952,416 in 256 parts Note mostly unrouted Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 156 MB 1.4 GB STEP 784 MB 1.9 GB STL 248 MB 1.4 GB OBJ 525 MB 3.2 GB Visual GLB 73 MB 1.5 GB OBJ 230 MB 1.7 GB

428. ICE40HXDevBoardHDMI

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.9	3.1	0.4 ms	3.2	0.2	0.5	0.3	8.5
Simulation, STEP	0.3	0.9	3.1	0.4 ms	3.1	2.9	0.5	0.3	11.1
Simulation, STL	0.4	0.9	3.3	0.3 ms	3.4	0.3	0.5	0.3	9.0
Simulation, OBJ	0.3	0.9	3.4	0.3 ms	3.4	5.0	0.5	0.2	13.6
Visual, GLB	0.3	0.9	3.1	0.3 ms	7.1	85 ms	0.5	0.2	12.3
Visual, OBJ	0.4	0.9	3.1	0.5 ms	7.1	2.7	0.6	0.2	15.1

Board Repo: aslak3/ICE40HXDevBoard Board: ICE40HXDevBoardHDMI.kicad_pcb Folder ExpansionCards / ICE40HXDevBoardHDMI Complexity 344 / 1000 (size 224, features 120) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 48, 542, 64 Triangles, simulation 899,090 in 84 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 31 MB 414 MB STEP 122 MB 457 MB STL 45 MB 397 MB OBJ 92 MB 633 MB Visual GLB 17 MB 416 MB OBJ 53 MB 500 MB

429. ICE40HXDevBoardVGA

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.8	2.5	0.4 ms	2.7	0.1	0.5	0.3	7.1
Simulation, STEP	0.2	0.8	2.6	0.5 ms	2.7	2.6	0.6	0.3	9.7
Simulation, STL	0.2	0.8	2.4	0.5 ms	2.7	0.3	0.6	0.2	7.4
Simulation, OBJ	0.3	0.8	2.4	0.5 ms	2.3	3.7	0.4	0.3	10.2
Visual, GLB	0.3	0.8	2.6	0.3 ms	6.3	78 ms	0.6	0.3	10.9
Visual, OBJ	0.2	0.6	2.9	0.4 ms	5.8	1.9	0.8	0.3	12.5

Board Repo: aslak3/ICE40HXDevBoard Board: ICE40HXDevBoardVGA.kicad_pcb Folder ExpansionCards / ICE40HXDevBoardVGA Complexity 299 / 1000 (size 214, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 36, 379, 39 Triangles, simulation 765,242 in 78 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 26 MB 346 MB STEP 89 MB 392 MB STL 38 MB 357 MB OBJ 77 MB 553 MB Visual GLB 15 MB 431 MB OBJ 43 MB 411 MB

430. ICE40HXDevBoard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	2.6	7.3	1 ms	8.1	0.4	1.1	0.3	20.4
Simulation, STEP	0.8	2.3	7.3	0.8 ms	8.0	6.1	1.1	0.3	26.0
Simulation, STL	0.8	2.3	7.8	0.9 ms	7.9	0.6	1.1	0.3	20.8
Simulation, OBJ	0.6	2.2	7.0	0.9 ms	7.6	12.0	1.0	0.4	30.9
Visual, GLB	0.6	2.2	7.0	0.9 ms	17.4	0.2	1.7	0.3	29.5
Visual, OBJ	0.6	2.2	6.9	0.9 ms	17.7	7.6	2.0	0.3	37.3

Board Repo: aslak3/ICE40HXDevBoard Board: ICE40HXDevBoard.kicad_pcb Complexity 345 / 1000 (size 250, features 95) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 111, 1,526, 194 Triangles, simulation 1,898,466 in 175 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 65 MB 636 MB STEP 250 MB 818 MB STL 95 MB 630 MB OBJ 198 MB 1.2 GB Visual GLB 43 MB 862 MB OBJ 131 MB 953 MB

431. ICE40UPDevBoard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.3	3.9	0.7 ms	3.9	0.2	0.6	0.3	10.5
Simulation, STEP	0.4	1.2	3.7	0.3 ms	3.9	3.0	0.6	0.3	13.0
Simulation, STL	0.4	1.2	4.0	0.4 ms	3.8	0.3	0.5	0.2	10.4
Simulation, OBJ	0.3	1.3	3.8	0.3 ms	3.8	5.4	0.5	0.2	15.4
Visual, GLB	0.4	1.2	3.8	0.5 ms	8.5	0.1	1.0	0.2	15.3
Visual, OBJ	0.4	1.2	3.5	0.6 ms	8.5	3.6	1.0	0.2	18.6

Board Repo: aslak3/ICE40UPDevBoard Board: ICE40UPDevBoard.kicad_pcb Complexity 339 / 1000 (size 244, features 95) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 92, 734, 133 Triangles, simulation 1,231,682 in 97 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 42 MB 496 MB STEP 157 MB 561 MB STL 62 MB 486 MB OBJ 126 MB 843 MB Visual GLB 27 MB 657 MB OBJ 81 MB 646 MB

432. Printer+Sticks

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.6	6.4	0.6 ms	4.8	0.2	0.6	0.3	14.3
Simulation, STEP	0.3	1.7	6.2	0.6 ms	4.7	3.7	0.7	0.3	17.6
Simulation, STL	0.3	1.7	6.6	0.7 ms	4.8	0.5	0.7	0.2	14.8
Simulation, OBJ	0.3	1.7	6.1	0.6 ms	4.9	8.8	0.7	0.3	22.8
Visual, GLB	0.3	1.7	6.3	0.5 ms	9.4	0.1	0.9	0.2	19.0
Visual, OBJ	0.3	1.7	6.3	0.6 ms	9.1	4.2	1.0	0.2	22.9

Board Repo: aslak3/maxi030 Board: Printer+Sticks.kicad_pcb Folder ExpansionCards / Printer+Sticks Complexity 269 / 1000 (size 224, features 45) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 4 File format KiCad 6 (20211014) Parts, tracks, vias 26, 810, 98 Triangles, simulation 1,489,044 in 88 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 52 MB 526 MB STEP 196 MB 596 MB STL 74 MB 502 MB OBJ 155 MB 1.0 GB Visual GLB 25 MB 606 MB OBJ 75 MB 604 MB

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