Corpus Testing 12

Corpus Page 12

Part 12 of 29 of Corpus Testing: boards 1,189 to 1,296, six runs each, one file format a run, as Corpus Testing describes.

1189. syzygy-txr-breakout

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.4	4.1	0.5 ms	4.7	0.2	0.6	0.3	11.9
Simulation, STEP	0.5	1.2	4.0	0.4 ms	4.8	3.5	0.7	0.3	15.0
Simulation, STL	0.4	1.2	4.2	0.4 ms	5.1	0.5	0.7	0.3	12.2
Simulation, OBJ	0.5	1.4	4.2	0.4 ms	4.9	8.1	0.7	0.3	19.9
Visual, GLB	0.4	1.1	4.0	0.5 ms	10.3	0.1	1.1	0.3	17.3
Visual, OBJ	0.4	1.2	4.2	0.4 ms	11.1	4.4	1.3	0.3	22.9

Board Repo: gregdavill/advent-calendar-of-circuits-2020 Board: syzygy-txr-breakout.kicad_pcb Folder syzygy-txr-breakout / kicad-src Complexity 314 / 1000 (size 199, features 115) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 6 (20201116) Parts, tracks, vias 28, 2,385, 68 Triangles, simulation 1,349,284 in 70 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 45 MB 655 MB STEP 196 MB 645 MB STL 67 MB 602 MB OBJ 137 MB 927 MB Visual GLB 24 MB 684 MB OBJ 74 MB 705 MB

1190. obsidian-boa-r0.1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.0	3.3	0.5 ms	3.7	0.2	0.6	0.3	9.4
Simulation, STEP	0.4	1.1	3.5	0.5 ms	3.9	3.0	0.6	0.2	12.7
Simulation, STL	0.3	1.1	3.3	0.5 ms	3.7	0.3	0.6	0.3	9.7
Simulation, OBJ	0.3	1.1	3.4	0.5 ms	3.7	5.8	0.6	0.2	15.1
Visual, GLB	0.3	1.0	3.3	0.6 ms	9.0	0.1	0.9	0.2	14.9
Visual, OBJ	0.3	1.1	3.5	0.5 ms	9.2	3.3	1.0	0.2	18.7

Board Repo: gregdavill/obsidian-boa Board: obsidian-boa-r0.1.kicad_pcb Folder hw / obsidian-boa-r0.1 Complexity 364 / 1000 (size 239, features 125) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 6 (20201002) Parts, tracks, vias 83, 975, 113 Triangles, simulation 1,191,616 in 87 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 40 MB 452 MB STEP 180 MB 539 MB STL 60 MB 450 MB OBJ 121 MB 820 MB Visual GLB 23 MB 644 MB OBJ 71 MB 642 MB

1191. FreshTwinkie

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	1.1	3.8	0.3 ms	3.5	0.1	0.5	0.2	9.4
Simulation, STEP	0.3	1.1	3.8	0.4 ms	3.6	2.8	0.5	0.2	12.3
Simulation, STL	0.2	1.1	3.8	0.4 ms	3.6	0.3	0.5	0.2	9.7
Simulation, OBJ	0.3	1.1	3.8	0.3 ms	3.7	5.4	0.4	0.2	14.9
Visual, GLB	0.3	1.1	3.8	0.5 ms	7.3	97 ms	0.9	0.2	13.7
Visual, OBJ	0.3	1.1	3.8	0.4 ms	6.7	3.4	0.8	0.2	16.3

Board Repo: gregdavill/PD-sniffer Board: FreshTwinkie.kicad_pcb Folder hw / FreshTwinkie_v0.1 Complexity 325 / 1000 (size 235, features 90) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 50, 1,014, 145 Triangles, simulation 1,049,192 in 93 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 36 MB 468 MB STEP 155 MB 555 MB STL 52 MB 484 MB OBJ 109 MB 736 MB Visual GLB 21 MB 501 MB OBJ 65 MB 523 MB

1192. FreshTwinkie_v0.1_panel

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	2.6	10.0	0.6 ms	9.5	0.4	1.0	0.3	24.2
Simulation, STEP	0.6	2.6	9.5	0.6 ms	9.7	6.2	1.0	0.3	29.9
Simulation, STL	0.7	2.7	9.4	0.7 ms	9.3	0.6	1.0	0.3	24.1
Simulation, OBJ	0.6	2.6	9.9	0.6 ms	9.8	13.4	1.0	0.3	37.6
Visual, GLB	0.7	2.7	10.1	0.6 ms	19.1	0.2	1.9	0.3	35.1
Visual, OBJ	0.6	2.8	10.2	0.8 ms	19.0	8.2	2.2	0.2	43.1

Board Repo: gregdavill/PD-sniffer Board: FreshTwinkie_v0.1_panel.kicad_pcb Folder hw / FreshTwinkie_v0.1_panel Complexity 361 / 1000 (size 261, features 100) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 100, 2,028, 290 Triangles, simulation 2,186,448 in 94 parts Note panel Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 76 MB 752 MB STEP 323 MB 941 MB STL 109 MB 750 MB OBJ 235 MB 1.5 GB Visual GLB 46 MB 1.0 GB OBJ 144 MB 1.0 GB

1193. kimchi_micro

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.7	9.6	23.3	1 ms	29.9	1.5	4.6	0.4	71.0
Simulation, STEP	1.6	9.5	23.4	1 ms	30.1	16.2	4.4	0.4	85.6
Simulation, STL	1.6	9.1	22.8	1.0 ms	30.6	3.3	4.3	0.4	72.0
Simulation, OBJ	1.6	9.0	23.3	1 ms	31.0	46.3	4.5	0.5	116.3
Visual, GLB	1.8	9.1	23.0	1.0 ms	53.5	0.7	6.9	0.3	95.3
Visual, OBJ	1.7	9.4	24.3	1 ms	53.0	18.3	7.1	0.3	114.1

Board Repo: groupgets/kimchi-micro Board: kimchi_micro.kicad_pcb Folder hardware_sbc Complexity 404 / 1000 (size 334, features 70) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings Tested 9th November 2026 Copper layers 8 File format KiCad 8 (20240108) Parts, tracks, vias 289, 10,738, 1,058 Triangles, simulation 9,560,528 in 411 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 330 MB 2.1 GB STEP 1.2 GB 2.9 GB STL 478 MB 2.1 GB OBJ 1.1 GB 6.1 GB Visual GLB 143 MB 2.5 GB OBJ 480 MB 3.1 GB

1194. LevelShifter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.4	1.6	0.3 ms	2.1	93 ms	0.3	0.2	5.0
Simulation, STEP	0.2	0.4	1.5	0.3 ms	2.6	2.2	0.3	0.3	7.5
Simulation, STL	0.3	0.4	1.5	0.3 ms	2.2	0.1	0.3	0.2	5.1
Simulation, OBJ	0.2	0.4	1.6	0.3 ms	2.4	2.7	0.3	0.2	7.8
Visual, GLB	0.2	0.4	1.4	0.3 ms	5.8	79 ms	0.6	0.2	8.7
Visual, OBJ	0.2	0.4	1.6	0.3 ms	5.2	2.3	0.8	0.2	10.8

Board Repo: gusmanb/logicanalyzer Board: LevelShifter.kicad_pcb Folder Electronics / LogicAnalyzer / LevelShifter Complexity 224 / 1000 (size 164, features 60) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 6 (20211014) Parts, tracks, vias 21, 986, 10 Triangles, simulation 659,382 in 76 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 22 MB 370 MB STEP 114 MB 426 MB STL 33 MB 346 MB OBJ 66 MB 472 MB Visual GLB 18 MB 512 MB OBJ 54 MB 526 MB

1195. LogicAnalyzer

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.5	2.7	0.4 ms	2.9	0.1	0.4	0.3	7.2
Simulation, STEP	0.2	0.6	2.5	0.4 ms	3.1	2.9	0.4	0.2	10.0
Simulation, STL	0.2	0.5	2.6	0.4 ms	3.3	0.2	0.4	0.2	7.4
Simulation, OBJ	0.2	0.5	2.4	0.3 ms	3.0	3.6	0.4	0.2	10.3
Visual, GLB	0.2	0.5	2.3	0.4 ms	6.1	93 ms	0.8	0.2	10.3
Visual, OBJ	0.2	0.5	2.3	1 ms	6.3	2.8	0.8	0.2	13.1

Board Repo: gusmanb/logicanalyzer Board: LogicAnalyzer.kicad_pcb Folder Electronics / LogicAnalyzer / LogicAnalyzer Complexity 228 / 1000 (size 158, features 70) KESE features through vias, rounded, trapezoid or chamfered pads, drill offsets, arc tracks, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 6 (20211014) Parts, tracks, vias 10, 1,119, 1 Triangles, simulation 881,842 in 50 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 29 MB 423 MB STEP 165 MB 502 MB STL 44 MB 436 MB OBJ 88 MB 598 MB Visual GLB 24 MB 651 MB OBJ 72 MB 649 MB

1196. AnalyzerBoxPCB_fork

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.7	2.8	0.5 ms	3.6	0.1	0.5	0.2	8.3
Simulation, STEP	0.3	0.7	2.7	0.3 ms	3.3	2.7	0.4	0.2	10.4
Simulation, STL	0.3	0.7	2.8	0.4 ms	3.4	0.3	0.4	0.2	8.2
Simulation, OBJ	0.3	0.7	2.7	0.3 ms	3.5	5.3	0.4	0.2	13.2
Visual, GLB	0.4	0.7	2.8	0.3 ms	7.8	0.1	0.9	0.3	12.9
Visual, OBJ	0.3	0.7	2.9	0.4 ms	7.7	4.2	1.2	0.3	17.2

Board Repo: gusmanb/logicanalyzer Board: AnalyzerBoxPCB_fork.kicad_pcb Folder Electronics / LogicAnalyzer / LogicAnalyzer_JasonYANG170 / KiCad 8 Complexity 250 / 1000 (size 190, features 60) KESE features through vias, arc tracks, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 54, 796, 63 Triangles, simulation 935,662 in 67 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 32 MB 492 MB STEP 145 MB 515 MB STL 47 MB 485 MB OBJ 94 MB 662 MB Visual GLB 25 MB 582 MB OBJ 75 MB 620 MB

1197. jitx-design

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.3	4.7	0.6 ms	9.7	0.2	0.7	0.3	17.4
Simulation, STEP	0.5	1.2	4.7	0.4 ms	9.7	5.9	0.7	0.2	22.9
Simulation, STL	0.5	1.2	4.8	0.6 ms	9.3	0.4	0.7	0.3	17.2
Simulation, OBJ	0.4	1.2	5.1	0.4 ms	9.4	7.6	0.8	0.3	24.8
Visual, GLB	0.5	1.1	4.9	0.4 ms	12.7	0.2	1.8	0.2	21.3
Visual, OBJ	0.4	1.1	4.9	0.3 ms	13.4	6.5	1.7	0.3	28.3

Board Repo: gusmanb/logicanalyzer Board: jitx-design.kicad_pcb Folder Electronics / LogicAnalyzer / LogicAnalyzerV2 / designs / jitx-design / kicad Complexity 308 / 1000 (size 193, features 115) KESE features through vias, slotted holes, arc tracks, filled zones, copper drawings, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 26, 1,778, 50 Triangles, simulation 1,448,730 in 69 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 49 MB 665 MB STEP 274 MB 710 MB STL 72 MB 670 MB OBJ 150 MB 961 MB Visual GLB 41 MB 694 MB OBJ 123 MB 881 MB

1198. StackLink

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	32 ms	0.1	0.4	0.1 ms	0.6	20 ms	65 ms	0.2	1.4
Simulation, STEP	35 ms	0.1	0.4	0.2 ms	0.6	0.8	67 ms	0.2	2.2
Simulation, STL	34 ms	0.1	0.4	0.1 ms	0.5	27 ms	63 ms	0.2	1.4
Simulation, OBJ	34 ms	0.1	0.4	0.1 ms	0.6	0.6	92 ms	0.2	2.1
Visual, GLB	33 ms	0.1	0.4	0.1 ms	1.0	12 ms	86 ms	0.2	1.9
Visual, OBJ	36 ms	0.1	0.5	0.2 ms	1.0	0.4	83 ms	0.2	2.3

Board Repo: gusmanb/logicanalyzer Board: StackLink.kicad_pcb Folder Electronics / LogicAnalyzer / StackLink / StackLink Complexity 137 / 1000 (size 92, features 45) KESE features through vias, slotted holes, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 5, 12, 6 Triangles, simulation 108,050 in 13 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 3.6 MB 170 MB STEP 16 MB 170 MB STL 5.4 MB 162 MB OBJ 10 MB 169 MB Visual GLB 2.4 MB 130 MB OBJ 6.6 MB 133 MB

1199. sprig_console

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.7	2.9	0.3 ms	2.6	0.1	0.4	0.2	7.2
Simulation, STEP	0.3	0.6	2.9	0.2 ms	2.6	2.1	0.3	0.2	9.1
Simulation, STL	0.3	0.6	2.8	0.3 ms	2.5	0.3	0.4	0.2	7.0
Simulation, OBJ	0.3	0.6	2.9	0.2 ms	2.5	4.1	0.3	0.2	11.0
Visual, GLB	0.3	0.6	3.0	0.3 ms	6.1	98 ms	0.7	0.2	10.9
Visual, OBJ	0.3	0.6	2.9	0.4 ms	6.2	2.9	0.9	0.2	14.0

Board Repo: hackclub/sprig Board: sprig_console.kicad_pcb Folder hardware / mainboard_PCB / kicad Complexity 231 / 1000 (size 146, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 25, 254, 19 Triangles, simulation 808,388 in 55 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 28 MB 409 MB STEP 137 MB 435 MB STL 40 MB 408 MB OBJ 82 MB 590 MB Visual GLB 19 MB 502 MB OBJ 58 MB 472 MB

1200. pico-reset

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.9	0.3 ms	0.8	38 ms	0.1	0.2	2.4
Simulation, STEP	94 ms	0.2	1.0	0.3 ms	0.9	1.1	0.1	0.2	3.6
Simulation, STL	95 ms	0.2	0.9	0.3 ms	0.8	68 ms	0.2	0.2	2.4
Simulation, OBJ	91 ms	0.2	0.9	0.2 ms	0.7	0.9	0.1	0.2	3.1
Visual, GLB	85 ms	0.1	0.8	0.2 ms	1.7	14 ms	99 ms	0.2	3.0
Visual, OBJ	97 ms	0.2	0.8	0.5 ms	1.6	0.4	93 ms	0.2	3.4

Board Repo: hackclub/sprig Board: pico-reset.kicad_pcb Folder sprig-hax / hardware / DebugShimPCB Complexity 82 / 1000 (size 82, features 0) Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 3, 21, 0 Triangles, simulation 162,188 in 52 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 5.1 MB 194 MB STEP 22 MB 213 MB STL 8.1 MB 194 MB OBJ 16 MB 194 MB Visual GLB 2.7 MB 158 MB OBJ 7.6 MB 159 MB

1201. sprig_console

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.6	3.2	0.3 ms	2.5	0.1	0.4	0.2	7.2
Simulation, STEP	0.3	0.6	3.3	0.3 ms	2.5	2.2	0.4	0.2	9.5
Simulation, STL	0.3	0.6	3.1	0.3 ms	2.5	0.3	0.4	0.2	7.2
Simulation, OBJ	0.3	0.6	3.2	0.2 ms	2.5	4.3	0.4	0.2	11.5
Visual, GLB	0.3	0.6	3.1	0.3 ms	5.8	88 ms	0.8	0.2	10.9
Visual, OBJ	0.3	0.6	3.2	0.4 ms	5.7	2.8	0.8	0.2	13.7

Board Repo: hackclub/sprig Board: sprig_console.kicad_pcb Folder sprig-hax / hardware / SprigHaxPCB / kicad Complexity 230 / 1000 (size 145, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 25, 242, 16 Triangles, simulation 816,372 in 55 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 28 MB 382 MB STEP 144 MB 463 MB STL 41 MB 399 MB OBJ 83 MB 597 MB Visual GLB 19 MB 439 MB OBJ 58 MB 460 MB

1202. ZU64DR_RFSOC_A5

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	4.3	23.5	0.8 ms	30.1	0.6	1.6	0.4	61.1
Simulation, STEP	0.7	4.5	24.2	0.7 ms	30.6	15.1	1.5	0.4	77.1
Simulation, STL	0.6	4.3	23.4	0.2 ms	28.7	1.4	1.5	0.3	60.1
Simulation, OBJ	0.6	4.2	22.9	0.1 ms	29.7	18.5	1.6	0.3	78.0
Visual, GLB	0.7	4.2	23.4	0.8 ms	36.0	0.3	4.3	0.3	69.3
Visual, OBJ	0.6	4.4	23.9	0.1 ms	36.6	10.9	4.5	0.3	81.2

Board Repo: hamedroghani/zu64dr_rfsoc_kicad Board: ZU64DR_RFSOC_A5.kicad_pcb Complexity 229 / 1000 (size 184, features 45) KESE features stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 12 File format KiCad 8 (20231120) Parts, tracks, vias 75, 0, 0 Triangles, simulation 3,488,834 in 35 parts Note mostly unrouted Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 123 MB 1.5 GB STEP 685 MB 2.0 GB STL 174 MB 1.5 GB OBJ 374 MB 2.4 GB Visual GLB 72 MB 1.6 GB OBJ 221 MB 1.6 GB

1203. Easyduino_Atmega_Nano

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.5	1.6	0.3 ms	1.7	87 ms	0.3	0.2	4.5
Simulation, STEP	0.2	0.5	1.6	0.3 ms	1.8	1.6	0.3	0.2	6.1
Simulation, STL	0.2	0.5	1.5	0.2 ms	1.7	0.2	0.3	0.3	4.7
Simulation, OBJ	0.2	0.5	1.5	0.3 ms	1.6	2.5	0.3	0.2	6.9
Visual, GLB	0.2	0.5	1.5	0.2 ms	3.9	51 ms	0.5	0.2	6.9
Visual, OBJ	0.2	0.5	1.5	0.3 ms	3.8	1.5	0.5	0.2	8.3

Board Repo: Hanqaqa/Easyduino Board: Easyduino_Atmega_Nano.kicad_pcb Folder Atmega328p Arduino Nano Complexity 304 / 1000 (size 219, features 85) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 10 (20260206) Parts, tracks, vias 31, 332, 57 Triangles, simulation 632,874 in 75 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 21 MB 312 MB STEP 78 MB 369 MB STL 32 MB 318 MB OBJ 63 MB 462 MB Visual GLB 13 MB 366 MB OBJ 39 MB 363 MB

1204. Easyduino_Atmega

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.8	2.6	0.4 ms	2.8	0.2	0.5	0.2	7.3
Simulation, STEP	0.3	0.7	2.4	0.4 ms	2.8	2.4	0.5	0.2	9.4
Simulation, STL	0.3	0.8	2.5	0.3 ms	2.9	0.2	0.5	0.2	7.4
Simulation, OBJ	0.3	0.8	2.3	0.2 ms	2.8	4.2	0.5	0.2	11.3
Visual, GLB	0.3	0.8	2.6	0.3 ms	5.5	81 ms	0.8	0.3	10.2
Visual, OBJ	0.3	0.8	2.5	0.3 ms	5.3	2.4	0.8	0.2	12.3

Board Repo: Hanqaqa/Easyduino Board: Easyduino_Atmega.kicad_pcb Folder Atmega328p Arduino Uno Complexity 320 / 1000 (size 220, features 100) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 10 (20260206) Parts, tracks, vias 36, 391, 106 Triangles, simulation 859,494 in 68 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 29 MB 388 MB STEP 99 MB 470 MB STL 43 MB 382 MB OBJ 86 MB 622 MB Visual GLB 17 MB 498 MB OBJ 52 MB 458 MB

1205. Easyduino_ESP32

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.7	2.3	0.5 ms	2.4	0.1	0.4	0.3	6.5
Simulation, STEP	0.2	0.7	2.5	0.3 ms	2.4	2.4	0.5	0.2	9.0
Simulation, STL	0.3	0.7	2.4	0.3 ms	2.4	0.2	0.5	0.2	6.6
Simulation, OBJ	0.2	0.7	2.5	0.3 ms	2.3	3.9	0.4	0.3	10.3
Visual, GLB	0.2	0.6	2.4	0.4 ms	5.8	67 ms	0.5	0.3	9.9
Visual, OBJ	0.3	0.7	2.5	0.3 ms	5.4	2.5	0.5	0.3	12.2

Board Repo: Hanqaqa/Easyduino Board: Easyduino_ESP32.kicad_pcb Folder ESP32 Complexity 299 / 1000 (size 214, features 85) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 10 (20260206) Parts, tracks, vias 29, 372, 64 Triangles, simulation 663,478 in 86 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 23 MB 324 MB STEP 98 MB 385 MB STL 33 MB 324 MB OBJ 67 MB 494 MB Visual GLB 14 MB 412 MB OBJ 42 MB 377 MB

1206. Easyduino_ESP32S3

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.9	2.6	0.5 ms	3.1	0.2	0.6	0.2	7.9
Simulation, STEP	0.2	0.9	2.5	0.4 ms	2.9	2.4	0.5	0.2	9.6
Simulation, STL	0.2	0.8	2.4	0.5 ms	3.0	0.3	0.5	0.2	7.5
Simulation, OBJ	0.3	0.8	2.4	0.6 ms	3.0	4.3	0.6	0.2	11.6
Visual, GLB	0.3	0.9	2.4	0.3 ms	6.2	0.1	0.9	0.2	11.1
Visual, OBJ	0.2	0.8	2.6	0.5 ms	6.2	2.5	0.7	0.2	13.3

Board Repo: Hanqaqa/Easyduino Board: Easyduino_ESP32S3.kicad_pcb Folder ESP32S3 Complexity 312 / 1000 (size 227, features 85) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 10 (20260206) Parts, tracks, vias 35, 703, 137 Triangles, simulation 980,336 in 89 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 33 MB 420 MB STEP 135 MB 519 MB STL 49 MB 409 MB OBJ 99 MB 696 MB Visual GLB 19 MB 536 MB OBJ 58 MB 509 MB

1207. Easyduino_RP2040

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.8	2.8	0.3 ms	3.0	0.2	0.6	0.2	7.7
Simulation, STEP	0.3	0.9	2.7	0.2 ms	3.0	2.8	0.6	0.3	10.4
Simulation, STL	0.3	0.8	2.7	0.2 ms	3.0	0.2	0.5	0.2	7.9
Simulation, OBJ	0.3	0.8	2.7	0.2 ms	3.0	5.1	0.6	0.2	12.7
Visual, GLB	0.3	0.8	2.7	0.3 ms	6.1	85 ms	0.5	0.3	10.6
Visual, OBJ	0.3	0.8	2.8	0.3 ms	6.0	3.1	0.5	0.2	13.6

Board Repo: Hanqaqa/Easyduino Board: Easyduino_RP2040.kicad_pcb Folder Raspberry Pi Pico 2040 Complexity 325 / 1000 (size 225, features 100) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 10 (20260206) Parts, tracks, vias 47, 570, 88 Triangles, simulation 947,692 in 74 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 32 MB 399 MB STEP 133 MB 493 MB STL 47 MB 399 MB OBJ 95 MB 702 MB Visual GLB 20 MB 492 MB OBJ 61 MB 515 MB

1208. Easyduino_STM32F103

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.7	2.3	0.4 ms	3.0	0.1	0.5	0.2	7.2
Simulation, STEP	0.2	0.7	2.4	0.6 ms	3.0	2.2	0.4	0.3	9.3
Simulation, STL	0.2	0.7	2.3	0.3 ms	2.9	0.2	0.5	0.2	7.0
Simulation, OBJ	0.2	0.7	2.2	0.4 ms	3.0	3.9	0.5	0.3	10.8
Visual, GLB	0.2	0.7	2.4	0.5 ms	5.5	68 ms	0.6	0.3	9.8
Visual, OBJ	0.3	0.7	2.2	0.4 ms	5.9	2.2	0.6	0.2	12.1

Board Repo: Hanqaqa/Easyduino Board: Easyduino_STM32F103.kicad_pcb Folder STM32F103 Bluepill Complexity 313 / 1000 (size 218, features 95) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 10 (20260206) Parts, tracks, vias 30, 484, 75 Triangles, simulation 780,722 in 62 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 26 MB 355 MB STEP 93 MB 435 MB STL 39 MB 355 MB OBJ 78 MB 586 MB Visual GLB 16 MB 388 MB OBJ 48 MB 472 MB

1209. stepperdriver front panel

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	0.7	1.9	0.3 ms	1.5	67 ms	0.3	0.3	5.2
Simulation, STEP	0.4	0.6	1.6	0.2 ms	1.4	1.5	0.2	0.2	6.1
Simulation, STL	0.3	0.7	1.8	0.2 ms	1.4	0.1	0.2	0.2	4.7
Simulation, OBJ	0.4	0.7	1.8	0.3 ms	1.5	2.0	0.2	0.2	6.8
Visual, GLB	0.3	0.7	1.7	0.3 ms	3.9	59 ms	0.4	0.2	7.3
Visual, OBJ	0.3	0.8	1.8	0.2 ms	3.6	1.7	0.5	0.3	8.9

Board Repo: harp-tech/device.stepperdriver Board: stepperdriver front panel.kicad_pcb Folder Hardware / PCB / stepper driver front panel Complexity 239 / 1000 (size 149, features 90) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 22, 219, 57 Triangles, simulation 410,638 in 37 parts Note panel Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 14 MB 291 MB STEP 73 MB 326 MB STL 21 MB 290 MB OBJ 42 MB 345 MB Visual GLB 11 MB 326 MB OBJ 34 MB 329 MB

1210. stepper driver rear panel

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	90 ms	88 ms	0.2	0.1 ms	0.4	11 ms	32 ms	0.2	1.1
Simulation, STEP	95 ms	89 ms	0.3	0.1 ms	0.4	0.7	28 ms	0.2	1.9
Simulation, STL	95 ms	89 ms	0.3	0.3 ms	0.4	20 ms	31 ms	0.2	1.1
Simulation, OBJ	90 ms	87 ms	0.3	0.1 ms	0.4	0.4	33 ms	0.2	1.5
Visual, GLB	92 ms	86 ms	0.3	0.1 ms	0.6	10 ms	65 ms	0.2	1.4
Visual, OBJ	91 ms	89 ms	0.3	0.1 ms	0.6	0.3	62 ms	0.3	1.6

Board Repo: harp-tech/device.stepperdriver Board: stepper driver rear panel.kicad_pcb Folder Hardware / PCB / stepper driver rear panel Complexity 156 / 1000 (size 66, features 90) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 1, 0, 4 Triangles, simulation 61,040 in 12 parts Note panel Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 2.1 MB 72 MB STEP 8.5 MB 177 MB STL 3.1 MB 74 MB OBJ 5.9 MB 85 MB Visual GLB 1.6 MB 109 MB OBJ 4.5 MB 109 MB

1211. stepper driver

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.2	5.4	17.4	1 ms	16.8	0.8	2.7	0.3	44.5
Simulation, STEP	1.3	5.0	17.4	0.6 ms	17.3	12.4	3.0	0.3	56.7
Simulation, STL	1.2	5.1	17.6	1 ms	18.3	1.4	2.9	0.4	47.0
Simulation, OBJ	1.2	5.1	17.2	1 ms	17.0	25.4	2.8	0.3	68.9
Visual, GLB	1.1	5.0	16.9	0.7 ms	34.0	0.5	5.3	0.3	63.1
Visual, OBJ	1.2	4.8	16.5	0.7 ms	33.8	17.9	5.6	0.2	80.1

Board Repo: harp-tech/device.stepperdriver Board: stepper driver.kicad_pcb Folder Hardware / PCB / stepper driver Complexity 408 / 1000 (size 283, features 125) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 207, 2,022, 900 Triangles, simulation 4,340,758 in 241 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 144 MB 1.3 GB STEP 566 MB 1.9 GB STL 217 MB 1.4 GB OBJ 457 MB 2.7 GB Visual GLB 100 MB 1.7 GB OBJ 320 MB 2.1 GB

1212. HALMET

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.0	2.5	6.4	0.9 ms	8.1	0.4	0.9	0.3	19.5
Simulation, STEP	0.9	2.4	6.2	0.7 ms	8.0	5.8	0.9	0.2	24.5
Simulation, STL	1.0	2.4	6.1	0.8 ms	7.9	0.7	0.9	0.3	19.2
Simulation, OBJ	1.0	2.5	6.7	1.0 ms	8.4	13.1	0.9	0.3	32.9
Visual, GLB	1.0	2.4	6.2	0.8 ms	18.5	0.2	2.4	0.3	31.1
Visual, OBJ	1.0	2.4	7.5	2 ms	18.8	8.6	2.4	0.2	41.0

Board Repo: hatlabs/halmet-hardware Board: HALMET.kicad_pcb Complexity 369 / 1000 (size 219, features 150) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 215, 1,395, 333 Triangles, simulation 2,383,058 in 156 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 80 MB 816 MB STEP 325 MB 972 MB STL 119 MB 800 MB OBJ 249 MB 1.6 GB Visual GLB 53 MB 1.1 GB OBJ 164 MB 1.2 GB

1213. HALPI2

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	6.4	12.6	53.6	2 ms	62.7	3.2	10.0	0.6	149.2
Simulation, STEP	6.8	12.8	54.3	2 ms	63.7	40.2	10.4	0.7	188.9
Simulation, STL	6.8	13.0	53.1	2 ms	61.9	7.1	10.4	0.7	152.9
Simulation, OBJ	6.9	12.8	53.6	2 ms	63.8	96.8	10.0	0.7	244.6
Visual, GLB	7.0	13.0	54.5	2 ms	190.6	1.5	14.6	0.6	281.7
Visual, OBJ	6.7	12.6	51.9	2 ms	185.5	53.6	12.9	0.6	323.8

Board Repo: hatlabs/halpi2-hardware Board: HALPI2.kicad_pcb Complexity 495 / 1000 (size 310, features 185) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 6 File format KiCad 10 (20260206) Parts, tracks, vias 552, 5,434, 1,660 Triangles, simulation 14,008,076 in 554 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 464 MB 3.5 GB STEP 2.1 GB 4.7 GB STL 700 MB 3.6 GB OBJ 1.5 GB 8.8 GB Visual GLB 283 MB 4.7 GB OBJ 929 MB 6.1 GB

1214. HALSER

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	2.2	7.2	0.9 ms	8.2	0.4	0.8	0.3	19.7
Simulation, STEP	0.6	2.4	7.1	1 ms	7.4	5.3	0.9	0.3	24.1
Simulation, STL	0.6	2.4	6.9	0.8 ms	7.8	0.6	0.9	0.2	19.5
Simulation, OBJ	0.6	2.4	6.9	0.8 ms	7.7	10.8	0.8	0.3	29.6
Visual, GLB	0.6	2.3	7.3	0.9 ms	18.8	0.2	2.1	0.2	31.6
Visual, OBJ	0.6	2.3	7.2	0.8 ms	17.7	7.2	2.4	0.2	37.7

Board Repo: hatlabs/halser-hardware Board: HALSER.kicad_pcb Complexity 366 / 1000 (size 216, features 150) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 174, 1,183, 354 Triangles, simulation 2,423,634 in 129 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 81 MB 771 MB STEP 301 MB 972 MB STL 121 MB 767 MB OBJ 252 MB 1.6 GB Visual GLB 54 MB 1.1 GB OBJ 165 MB 1.2 GB

1215. SH-RPi

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	2.5	7.8	0.9 ms	8.9	0.4	1.0	0.3	21.6
Simulation, STEP	0.9	2.9	7.5	0.7 ms	8.1	6.2	0.9	0.4	26.9
Simulation, STL	0.7	2.3	8.0	1.0 ms	8.0	0.7	1.0	0.3	21.0
Simulation, OBJ	0.8	2.5	7.7	1 ms	8.9	13.4	0.9	0.3	34.6
Visual, GLB	0.8	2.5	8.0	0.8 ms	19.2	0.2	2.0	0.3	33.0
Visual, OBJ	0.6	2.6	8.7	0.7 ms	21.7	10.6	2.2	0.3	46.7

Board Repo: hatlabs/sh-rpi-hardware Board: SH-RPi.kicad_pcb Complexity 343 / 1000 (size 213, features 130) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 153, 925, 364 Triangles, simulation 2,241,942 in 132 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 75 MB 719 MB STEP 275 MB 955 MB STL 112 MB 743 MB OBJ 234 MB 1.5 GB Visual GLB 50 MB 926 MB OBJ 155 MB 1.1 GB

1216. motor-controller-hw

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	3.4	12.1	0.6 ms	11.1	0.5	1.5	0.3	29.7
Simulation, STEP	0.6	3.5	12.6	0.6 ms	11.3	7.7	1.4	0.3	37.4
Simulation, STL	0.6	3.5	12.8	0.6 ms	11.4	0.8	1.6	0.3	31.1
Simulation, OBJ	0.6	3.8	12.9	0.6 ms	11.0	17.6	1.6	0.3	47.8
Visual, GLB	0.6	3.7	12.1	0.6 ms	23.3	0.3	2.7	0.3	43.1
Visual, OBJ	0.7	3.5	13.4	1.0 ms	23.3	10.8	2.6	0.2	54.4

Board Repo: heev/motor-controller-2018 Board: motor-controller-hw.kicad_pcb Folder motor-controller-hw Complexity 318 / 1000 (size 263, features 55) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 156, 1,989, 192 Triangles, simulation 3,029,272 in 206 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 106 MB 1.0 GB STEP 513 MB 1.1 GB STL 151 MB 933 MB OBJ 327 MB 2.0 GB Visual GLB 65 MB 1.2 GB OBJ 202 MB 1.3 GB

1217. MotorControllerPowerBoard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	2.6	9.9	0.7 ms	7.5	0.3	1.0	0.2	22.1
Simulation, STEP	0.4	2.4	9.0	0.5 ms	7.0	5.0	0.9	0.3	25.1
Simulation, STL	0.5	2.4	9.5	0.5 ms	7.2	0.6	1.0	0.3	21.3
Simulation, OBJ	0.5	2.4	9.0	0.6 ms	7.2	11.7	1.0	0.3	32.1
Visual, GLB	0.4	2.4	9.2	0.7 ms	13.5	0.2	1.4	0.2	27.4
Visual, OBJ	0.4	2.5	9.0	0.6 ms	13.4	5.9	1.7	0.3	33.3

Board Repo: heev/motor-controller-2018 Board: MotorControllerPowerBoard.kicad_pcb Folder MotorControllerPowerBoardRev2 / MotorControllerPowerBoard Complexity 271 / 1000 (size 201, features 70) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 131, 747, 108 Triangles, simulation 2,114,558 in 108 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 72 MB 652 MB STEP 303 MB 793 MB STL 106 MB 635 MB OBJ 222 MB 1.4 GB Visual GLB 38 MB 764 MB OBJ 115 MB 836 MB

1218. voltage-regulator-module

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	95 ms	82 ms	0.4	0.1 ms	0.5	18 ms	64 ms	0.2	1.3
Simulation, STEP	90 ms	84 ms	0.4	0.2 ms	0.5	0.7	54 ms	0.2	2.1
Simulation, STL	85 ms	74 ms	0.3	0.1 ms	0.5	20 ms	49 ms	0.2	1.2
Simulation, OBJ	86 ms	79 ms	0.3	0.2 ms	0.5	0.4	50 ms	0.2	1.7
Visual, GLB	84 ms	75 ms	0.4	0.1 ms	1.2	13 ms	0.1	0.2	2.0
Visual, OBJ	86 ms	76 ms	0.4	0.2 ms	1.1	0.3	91 ms	0.2	2.3

Board Repo: heev/motor-controller-2018 Board: voltage-regulator-module.kicad_pcb Folder voltage-regulator-module Complexity 174 / 1000 (size 129, features 45) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 14, 127, 10 Triangles, simulation 107,936 in 21 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 3.8 MB 178 MB STEP 21 MB 189 MB STL 5.4 MB 185 MB OBJ 11 MB 178 MB Visual GLB 2.7 MB 156 MB OBJ 7.4 MB 157 MB

1219. ISA_CGA

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.9	9.2	39.2	3 ms	42.4	2.4	7.3	0.5	103.0
Simulation, STEP	2.0	9.1	37.8	2 ms	40.1	25.2	6.8	0.5	121.7
Simulation, STL	1.9	9.3	39.7	4 ms	41.7	4.8	7.1	0.6	105.0
Simulation, OBJ	2.0	9.5	40.8	2 ms	41.1	67.3	7.2	0.6	168.6
Visual, GLB	2.3	9.4	42.0	3 ms	102.4	1.0	10.8	0.4	168.4
Visual, OBJ	2.0	9.4	39.8	2 ms	101.2	29.2	10.7	0.3	192.6

Board Repo: hkzlab/CGA_Redux Board: ISA_CGA.kicad_pcb Complexity 307 / 1000 (size 237, features 70) KESE features through vias, custom pads, filled zones, copper drawings, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 170, 7,503, 328 Triangles, simulation 11,388,894 in 316 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 387 MB 2.5 GB STEP 1.5 GB 3.5 GB STL 569 MB 2.4 GB OBJ 1.2 GB 7.1 GB Visual GLB 196 MB 3.2 GB OBJ 634 MB 4.0 GB

1220. ISA_ES1868

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.0	3.1	11.8	0.7 ms	11.3	0.6	1.7	0.3	29.7
Simulation, STEP	0.9	3.0	11.7	1 ms	11.8	8.0	1.7	0.4	37.5
Simulation, STL	1.0	3.3	11.8	0.8 ms	11.7	1.1	1.9	0.3	30.9
Simulation, OBJ	1.2	3.1	11.7	0.8 ms	12.3	19.2	1.8	0.3	49.7
Visual, GLB	0.9	3.1	12.2	0.7 ms	26.8	0.3	3.1	0.3	46.8
Visual, OBJ	1.0	3.5	12.6	0.7 ms	28.4	11.3	3.6	0.2	60.5

Board Repo: hkzlab/ES1868_ISA8 Board: ISA_ES1868.kicad_pcb Complexity 329 / 1000 (size 249, features 80) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 119, 1,607, 85 Triangles, simulation 3,227,944 in 148 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 110 MB 1.1 GB STEP 478 MB 1.3 GB STL 161 MB 1.1 GB OBJ 340 MB 2.1 GB Visual GLB 65 MB 1.4 GB OBJ 200 MB 1.3 GB

1221. ISA_ES688

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.0	3.3	11.5	1 ms	11.3	0.5	1.6	0.3	29.6
Simulation, STEP	0.9	3.1	11.5	0.9 ms	11.5	8.4	1.6	0.3	37.4
Simulation, STL	1.0	3.2	11.4	0.8 ms	11.6	1.0	1.7	0.3	30.2
Simulation, OBJ	1.1	3.3	12.5	0.8 ms	11.6	18.6	1.7	0.3	49.1
Visual, GLB	0.9	3.3	11.6	0.8 ms	27.8	0.3	3.3	0.3	47.5
Visual, OBJ	0.9	3.0	12.0	0.8 ms	26.8	11.4	3.6	0.2	58.1

Board Repo: hkzlab/ES688_ISA8 Board: ISA_ES688.kicad_pcb Complexity 335 / 1000 (size 255, features 80) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 125, 2,157, 166 Triangles, simulation 3,361,666 in 167 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 115 MB 1.1 GB STEP 512 MB 1.3 GB STL 168 MB 1.1 GB OBJ 355 MB 2.2 GB Visual GLB 71 MB 1.4 GB OBJ 221 MB 1.5 GB

1222. allwinner-h3

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.6	2.7	0.5 ms	5.2	0.1	0.5	0.2	9.6
Simulation, STEP	0.2	0.6	2.8	0.2 ms	5.1	3.5	0.5	0.2	13.0
Simulation, STL	0.2	0.6	2.7	0.4 ms	5.1	0.3	0.5	0.2	9.7
Simulation, OBJ	0.2	0.7	2.5	0.4 ms	5.0	3.7	0.4	0.2	12.7
Visual, GLB	0.2	0.7	2.6	0.2 ms	8.2	0.1	0.6	0.2	12.7
Visual, OBJ	0.2	0.6	2.8	0.2 ms	8.7	3.6	1.0	0.2	17.2

Board Repo: hvwyl/allwinner-h3-ddr3-16x1-kicad Board: allwinner-h3.kicad_pcb Folder project Complexity 293 / 1000 (size 223, features 70) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 6 (20211014) Parts, tracks, vias 20, 1,320, 119 Triangles, simulation 867,728 in 91 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 29 MB 506 MB STEP 137 MB 533 MB STL 43 MB 494 MB OBJ 86 MB 615 MB Visual GLB 25 MB 683 MB OBJ 76 MB 678 MB

1223. FCCU-v2-schematic-pcb

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	4.3	16.9	1 ms	17.4	0.9	1.8	0.3	42.6
Simulation, STEP	0.9	4.6	16.8	0.7 ms	18.0	9.3	1.8	0.3	51.6
Simulation, STL	0.9	4.6	17.2	2 ms	18.1	2.0	1.9	0.3	45.0
Simulation, OBJ	0.9	4.3	17.4	0.8 ms	18.1	20.0	1.7	0.2	62.7
Visual, GLB	0.9	4.6	16.4	0.7 ms	35.2	0.3	4.0	0.3	61.7
Visual, OBJ	0.9	4.4	17.0	2 ms	37.0	10.8	4.5	0.3	74.8

Board Repo: hydrogreenpollub/fuel_cell_control_unit_pcb_fccu_v2_1 Board: FCCU-v2-schematic-pcb.kicad_pcb Complexity 400 / 1000 (size 270, features 130) KESE features through vias, padstacks, rounded, trapezoid or chamfered pads, drill offsets, filled zones, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 10 (20260206) Parts, tracks, vias 207, 3,324, 532 Triangles, simulation 4,737,866 in 182 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 161 MB 1.4 GB STEP 635 MB 1.7 GB STL 237 MB 1.4 GB OBJ 501 MB 3.0 GB Visual GLB 86 MB 1.6 GB OBJ 268 MB 1.8 GB

1224. FCCU-v21-schematic-pcb

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.6	6.3	24.0	0.9 ms	23.4	0.8	2.8	0.4	59.3
Simulation, STEP	1.6	6.7	23.5	2 ms	23.2	13.0	2.7	0.4	71.1
Simulation, STL	1.7	6.3	24.5	0.9 ms	24.2	2.1	2.6	0.4	61.7
Simulation, OBJ	1.4	6.4	24.6	1 ms	24.1	30.8	2.7	0.4	90.5
Visual, GLB	1.4	6.3	23.2	1 ms	46.5	0.5	4.2	0.3	82.3
Visual, OBJ	1.4	6.3	23.6	1.0 ms	45.6	15.6	4.5	0.3	97.3

Board Repo: hydrogreenpollub/fuel_cell_control_unit_pcb_fccu_v2_1 Board: FCCU-v21-schematic-pcb.kicad_pcb Complexity 404 / 1000 (size 274, features 130) KESE features through vias, padstacks, rounded, trapezoid or chamfered pads, drill offsets, filled zones, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 10 (20260206) Parts, tracks, vias 258, 3,794, 507 Triangles, simulation 4,809,760 in 228 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 165 MB 1.2 GB STEP 677 MB 1.7 GB STL 241 MB 1.2 GB OBJ 511 MB 3.1 GB Visual GLB 90 MB 1.6 GB OBJ 280 MB 1.9 GB

1225. Amiga 2000R6

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	4.6	33.1	235.2	4 ms	166.1	8.0	25.6	1.0	473.6
Simulation, STEP	4.2	32.6	238.4	4 ms	168.2	106.9	27.7	1.2	579.1
Simulation, STL	4.7	33.9	239.0	6 ms	177.7	17.7	25.7	1.1	499.8
Simulation, OBJ	3.9	30.8	231.5	8 ms	174.2	237.4	30.9	3.1	711.9
Visual, GLB	4.8	33.2	240.8	5 ms	422.0	4.3	43.4	1.0	749.6
Visual, OBJ	4.0	30.3	227.1	7 ms	366.9	98.2	35.3	0.9	762.7

Board Repo: iansbremner/Amiga-2000-KiCAD Board: Amiga 2000R6.kicad_pcb Complexity 346 / 1000 (size 291, features 55) KESE features through vias, filled zones, copper drawings, curved board outline Tested 9th November 2026 to 11th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 543, 21,184, 1,195 Triangles, simulation 28,431,494 in 828 parts Verifier PASS in all six runs Run again Visual, OBJ: failed in the corpus run, run again with the memory cap raised from 11 GB to 14.5 GB, and passed Run again Simulation, OBJ: failed in the corpus run, run again with no memory cap and no time limit (swap added to a 16 GB machine), and passed

File type File size Peak memory used Simulation GLB 975 MB 6.2 GB STEP 5.1 GB 8.9 GB STL 1.4 GB 6.5 GB OBJ 3.2 GB 18 GB Visual GLB 548 MB 8.0 GB OBJ 1.8 GB 11 GB

1226. Daughterboard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	4.7	32.8	2 ms	26.8	1.5	4.4	0.3	71.4
Simulation, STEP	0.8	5.0	33.5	2 ms	27.0	17.3	4.2	0.4	88.2
Simulation, STL	0.8	4.9	32.8	2 ms	27.1	2.9	4.3	0.4	73.1
Simulation, OBJ	0.8	5.0	32.2	2 ms	26.9	40.0	4.1	0.4	109.5
Visual, GLB	0.8	5.1	33.5	2 ms	50.0	0.5	6.3	0.3	96.5
Visual, OBJ	0.8	5.1	33.4	2 ms	49.5	16.1	6.2	0.3	111.4

Board Repo: iansbremner/Amiga-3000-Daughterboard Board: Daughterboard.kicad_pcb Complexity 253 / 1000 (size 218, features 35) KESE features through vias, filled zones Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 90, 3,667, 102 Triangles, simulation 8,425,376 in 307 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 285 MB 1.9 GB STEP 1.2 GB 2.6 GB STL 421 MB 1.9 GB OBJ 908 MB 5.3 GB Visual GLB 125 MB 2.3 GB OBJ 396 MB 2.6 GB

1227. Issue 4

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.9	5.0	36.1	0.8 ms	21.9	1.0	2.8	0.3	68.0
Simulation, STEP	1.0	5.1	36.1	0.9 ms	22.0	16.3	3.0	0.3	83.8
Simulation, STL	0.9	5.0	36.5	0.5 ms	22.0	2.0	2.9	0.3	69.6
Simulation, OBJ	0.9	4.9	36.6	0.6 ms	21.9	34.3	2.8	0.3	101.8
Visual, GLB	1.0	5.1	36.2	0.7 ms	48.0	0.6	5.1	0.3	96.2
Visual, OBJ	0.9	5.1	36.3	0.7 ms	46.6	19.6	4.7	0.3	113.5

Board Repo: iansbremner/ZX-Spectrum-Issue-4B-KiCAD Board: Issue 4.kicad_pcb Complexity 283 / 1000 (size 218, features 65) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 195, 5,111, 429 Triangles, simulation 6,255,428 in 166 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 215 MB 1.8 GB STEP 1.1 GB 2.2 GB STL 313 MB 1.8 GB OBJ 673 MB 4.0 GB Visual GLB 125 MB 2.0 GB OBJ 397 MB 2.6 GB

1228. tomu-fpga

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.7	3.1	0.2 ms	2.0	84 ms	0.3	0.2	6.5
Simulation, STEP	0.2	0.7	2.9	0.2 ms	2.0	1.6	0.2	0.3	7.9
Simulation, STL	0.2	0.7	3.0	0.2 ms	1.8	0.2	0.2	0.2	6.3
Simulation, OBJ	0.2	0.8	3.1	0.2 ms	2.1	3.0	0.3	0.2	9.7
Visual, GLB	0.2	0.8	3.1	0.3 ms	3.6	48 ms	0.3	0.3	8.4
Visual, OBJ	0.2	0.8	3.7	0.2 ms	3.8	1.5	0.3	0.2	10.5

Board Repo: im-tomu/fomu-hardware Board: tomu-fpga.kicad_pcb Folder archive / dvt / pcb Complexity 347 / 1000 (size 192, features 155) KESE features blind and buried vias, microvias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 41, 579, 249 Triangles, simulation 513,942 in 44 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 18 MB 313 MB STEP 74 MB 348 MB STL 26 MB 312 MB OBJ 53 MB 408 MB Visual GLB 9.8 MB 310 MB OBJ 29 MB 307 MB

1229. tomu-fpga

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.4	6.2	0.7 ms	6.3	0.2	0.6	0.3	15.3
Simulation, STEP	0.3	1.3	6.5	0.6 ms	6.3	3.7	0.5	0.2	18.9
Simulation, STL	0.3	1.3	6.3	0.5 ms	6.2	0.3	0.5	0.3	15.2
Simulation, OBJ	0.3	1.4	6.3	0.5 ms	6.2	6.3	0.6	0.2	21.2
Visual, GLB	0.3	1.4	6.2	0.3 ms	9.3	0.2	0.9	0.2	18.6
Visual, OBJ	0.3	1.4	6.3	0.5 ms	9.3	4.7	0.9	0.2	23.1

Board Repo: im-tomu/fomu-hardware Board: tomu-fpga.kicad_pcb Folder archive / evt / pcb Complexity 265 / 1000 (size 220, features 45) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 62, 919, 162 Triangles, simulation 1,100,316 in 79 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 38 MB 474 MB STEP 194 MB 565 MB STL 55 MB 466 MB OBJ 113 MB 811 MB Visual GLB 27 MB 613 MB OBJ 80 MB 616 MB

1230. tomu

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.7	0.2 ms	0.8	30 ms	0.1	0.2	2.2
Simulation, STEP	0.1	0.2	0.8	0.2 ms	0.8	0.9	84 ms	0.2	3.0
Simulation, STL	0.1	0.2	0.8	0.2 ms	0.8	46 ms	0.1	0.2	2.3
Simulation, OBJ	0.1	0.2	0.6	0.2 ms	0.8	0.7	0.1	0.2	2.7
Visual, GLB	0.1	0.2	0.6	0.2 ms	1.8	21 ms	0.1	0.2	3.0
Visual, OBJ	99 ms	0.2	0.6	0.1 ms	1.9	0.6	0.1	0.3	3.7

Board Repo: im-tomu/tomu-hardware Board: tomu.kicad_pcb Folder pcb Complexity 193 / 1000 (size 138, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 4 (4) Parts, tracks, vias 14, 193, 25 Triangles, simulation 162,358 in 34 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 5.7 MB 206 MB STEP 26 MB 212 MB STL 8.1 MB 204 MB OBJ 16 MB 204 MB Visual GLB 3.9 MB 173 MB OBJ 11 MB 172 MB

1231. tomu

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.6	0.2 ms	1.3	25 ms	87 ms	0.2	2.5
Simulation, STEP	0.1	0.2	0.6	0.2 ms	1.3	1.0	77 ms	0.2	3.5
Simulation, STL	0.1	0.2	0.6	0.2 ms	1.3	37 ms	79 ms	0.2	2.5
Simulation, OBJ	0.1	0.2	0.6	0.1 ms	1.3	0.8	84 ms	0.2	3.2
Visual, GLB	0.1	0.2	0.6	0.2 ms	1.6	20 ms	0.1	0.2	2.9
Visual, OBJ	0.1	0.2	0.6	0.2 ms	1.7	0.6	0.1	0.2	3.4

Board Repo: im-tomu/tomu-hardware Board: tomu.kicad_pcb Folder releases / v0.0 / gerbers Complexity 211 / 1000 (size 136, features 75) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 4 (4) Parts, tracks, vias 15, 198, 13 Triangles, simulation 122,700 in 35 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 4.4 MB 196 MB STEP 24 MB 205 MB STL 6.1 MB 195 MB OBJ 12 MB 195 MB Visual GLB 3.5 MB 163 MB OBJ 9.8 MB 165 MB

1232. tomu

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.5	0.2 ms	1.2	24 ms	80 ms	0.2	2.3
Simulation, STEP	0.1	0.2	0.5	0.1 ms	1.2	0.8	70 ms	0.2	3.1
Simulation, STL	0.1	0.2	0.5	0.2 ms	1.2	37 ms	98 ms	0.2	2.3
Simulation, OBJ	0.1	0.2	0.7	0.2 ms	1.1	0.6	85 ms	0.2	3.0
Visual, GLB	0.1	0.2	0.5	0.2 ms	1.6	19 ms	0.1	0.3	2.8
Visual, OBJ	0.1	0.2	0.5	0.2 ms	1.6	0.5	0.1	0.2	3.2

Board Repo: im-tomu/tomu-hardware Board: tomu.kicad_pcb Folder releases / v0.1 / gerbers Complexity 211 / 1000 (size 136, features 75) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 4 (4) Parts, tracks, vias 15, 198, 13 Triangles, simulation 122,368 in 35 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 4.4 MB 195 MB STEP 23 MB 214 MB STL 6.1 MB 195 MB OBJ 12 MB 195 MB Visual GLB 3.5 MB 165 MB OBJ 9.8 MB 163 MB

1233. tomu

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.4	0.2 ms	0.8	23 ms	72 ms	0.2	1.8
Simulation, STEP	0.1	0.2	0.5	0.1 ms	0.7	1.0	81 ms	0.2	2.7
Simulation, STL	0.1	0.2	0.5	0.2 ms	0.8	32 ms	70 ms	0.2	1.8
Simulation, OBJ	0.1	0.2	0.4	0.1 ms	0.7	0.6	66 ms	0.2	2.3
Visual, GLB	99 ms	0.2	0.5	0.1 ms	1.4	17 ms	99 ms	0.2	2.5
Visual, OBJ	0.1	0.2	0.4	0.2 ms	1.5	0.6	0.1	0.2	3.1

Board Repo: im-tomu/tomu-hardware Board: tomu.kicad_pcb Folder releases / v0.2 / gerbers Complexity 210 / 1000 (size 135, features 75) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 4 (4) Parts, tracks, vias 15, 176, 13 Triangles, simulation 121,252 in 34 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 4.3 MB 194 MB STEP 24 MB 203 MB STL 6.1 MB 193 MB OBJ 12 MB 192 MB Visual GLB 3.5 MB 162 MB OBJ 9.7 MB 162 MB

1234. tomu

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.6	0.1 ms	0.8	25 ms	74 ms	0.2	1.9
Simulation, STEP	0.1	0.2	0.6	0.1 ms	0.8	1.0	78 ms	0.2	3.0
Simulation, STL	0.1	0.2	0.6	0.2 ms	0.8	37 ms	74 ms	0.2	1.9
Simulation, OBJ	0.1	0.1	0.5	0.1 ms	0.8	0.7	77 ms	0.2	2.5
Visual, GLB	0.1	0.1	0.5	0.1 ms	1.5	20 ms	0.1	0.2	2.7
Visual, OBJ	0.1	0.2	0.6	0.2 ms	1.5	0.5	0.1	0.2	3.2

Board Repo: im-tomu/tomu-hardware Board: tomu.kicad_pcb Folder releases / v0.3 / gerber Complexity 200 / 1000 (size 135, features 65) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 4 (4) Parts, tracks, vias 15, 177, 13 Triangles, simulation 132,304 in 34 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 4.7 MB 198 MB STEP 26 MB 209 MB STL 6.6 MB 196 MB OBJ 13 MB 196 MB Visual GLB 3.7 MB 168 MB OBJ 10 MB 169 MB

1235. alu

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	3.5	14.5	1 ms	11.9	0.5	1.2	0.3	32.3
Simulation, STEP	0.4	3.3	14.1	1 ms	11.0	8.4	1.2	0.3	38.7
Simulation, STL	0.5	3.4	14.3	1.0 ms	11.7	1.0	1.3	0.3	32.5
Simulation, OBJ	0.5	3.6	13.9	1 ms	12.4	14.6	1.2	0.3	46.4
Visual, GLB	0.5	3.4	14.3	1 ms	32.2	0.4	4.6	0.3	55.6
Visual, OBJ	0.5	3.4	14.9	1 ms	31.3	13.3	5.5	0.2	69.3

Board Repo: imihajlow/ccpu Board: alu.kicad_pcb Folder boards / alu Complexity 262 / 1000 (size 207, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 66, 4,386, 780 Triangles, simulation 3,122,734 in 178 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 108 MB 1.3 GB STEP 542 MB 1.4 GB STL 156 MB 1.3 GB OBJ 332 MB 2.0 GB Visual GLB 95 MB 1.7 GB OBJ 300 MB 1.9 GB

1236. control

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	2.3	10.5	1 ms	9.7	0.3	0.8	0.3	24.3
Simulation, STEP	0.4	2.4	10.3	1 ms	9.5	6.2	0.8	0.3	29.9
Simulation, STL	0.4	2.3	10.7	1 ms	10.0	0.7	0.8	0.3	25.2
Simulation, OBJ	0.4	2.3	10.2	0.9 ms	9.6	9.8	0.8	0.3	33.5
Visual, GLB	0.4	2.3	10.3	0.9 ms	17.6	0.3	2.4	0.2	33.5
Visual, OBJ	0.4	2.3	10.3	1 ms	18.0	8.5	3.0	0.2	42.7

Board Repo: imihajlow/ccpu Board: control.kicad_pcb Folder boards / control Complexity 250 / 1000 (size 195, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 89, 1,430, 408 Triangles, simulation 1,991,990 in 129 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 69 MB 733 MB STEP 343 MB 942 MB STL 100 MB 747 MB OBJ 209 MB 1.3 GB Visual GLB 57 MB 1.1 GB OBJ 176 MB 1.2 GB

1237. eth

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	4.9	11.7	3 ms	21.3	0.7	1.7	0.4	41.6
Simulation, STEP	0.8	5.0	11.3	2 ms	21.4	11.0	1.6	0.4	51.7
Simulation, STL	0.8	4.8	11.1	2 ms	21.3	1.7	1.6	0.4	41.6
Simulation, OBJ	0.9	4.9	11.8	0.7 ms	21.3	22.4	1.6	0.3	63.3
Visual, GLB	0.9	5.1	11.5	2 ms	33.2	0.6	5.6	0.3	57.2
Visual, OBJ	0.9	4.8	11.5	2 ms	32.5	15.2	5.3	0.3	70.5

Board Repo: imihajlow/ccpu Board: eth.kicad_pcb Folder boards / eth Complexity 323 / 1000 (size 223, features 100) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 92, 2,811, 853 Triangles, simulation 4,559,284 in 229 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 151 MB 1.4 GB STEP 514 MB 1.7 GB STL 228 MB 1.4 GB OBJ 494 MB 2.9 GB Visual GLB 98 MB 1.6 GB OBJ 323 MB 2.1 GB

1238. io

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	2.9	14.5	1 ms	11.6	0.5	1.2	0.2	31.4
Simulation, STEP	0.5	2.9	14.9	1 ms	12.1	8.6	1.2	0.3	40.3
Simulation, STL	0.6	3.0	14.3	1 ms	11.6	0.7	1.3	0.3	31.9
Simulation, OBJ	0.5	3.0	14.7	0.9 ms	12.1	15.9	1.3	0.3	47.8
Visual, GLB	0.5	3.1	15.2	0.7 ms	23.3	0.3	3.2	0.3	46.0
Visual, OBJ	0.5	3.0	14.9	1 ms	21.4	11.0	2.5	0.4	53.7

Board Repo: imihajlow/ccpu Board: io.kicad_pcb Folder boards / io Complexity 306 / 1000 (size 241, features 65) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 119, 1,990, 399 Triangles, simulation 2,577,618 in 121 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 89 MB 879 MB STEP 447 MB 1.2 GB STL 129 MB 832 MB OBJ 272 MB 1.7 GB Visual GLB 67 MB 1.2 GB OBJ 208 MB 1.4 GB

1239. registers

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	5.6	20.2	2 ms	16.8	0.8	2.1	0.3	46.5
Simulation, STEP	0.7	5.5	21.5	2 ms	16.4	12.1	2.1	0.3	58.6
Simulation, STL	0.8	5.5	20.7	2 ms	16.6	1.7	2.2	0.4	47.9
Simulation, OBJ	0.9	5.8	21.1	2 ms	16.3	23.1	2.0	0.3	69.5
Visual, GLB	0.7	5.5	23.2	2 ms	52.8	0.7	7.6	0.3	90.8
Visual, OBJ	0.8	6.1	24.2	3 ms	52.9	20.0	7.5	0.4	111.8

Board Repo: imihajlow/ccpu Board: registers.kicad_pcb Folder boards / registers Complexity 278 / 1000 (size 223, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 213, 5,186, 1,072 Triangles, simulation 4,822,450 in 238 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 166 MB 1.7 GB STEP 859 MB 2.0 GB STL 241 MB 2.0 GB OBJ 517 MB 3.1 GB Visual GLB 135 MB 2.2 GB OBJ 434 MB 2.9 GB

1240. stack

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	2.5	10.3	2 ms	15.9	0.5	1.2	0.3	31.2
Simulation, STEP	0.4	2.5	10.8	1 ms	15.8	11.1	1.4	0.3	42.3
Simulation, STL	0.6	2.6	10.5	2 ms	16.4	1.2	1.3	0.3	32.8
Simulation, OBJ	0.5	2.6	10.9	1 ms	16.2	16.2	1.3	0.3	48.0
Visual, GLB	0.5	2.4	10.4	2 ms	32.8	0.5	5.0	0.3	51.9
Visual, OBJ	0.5	2.4	11.3	1 ms	32.3	13.7	5.5	0.3	65.8

Board Repo: imihajlow/ccpu Board: stack.kicad_pcb Folder boards / stack Complexity 293 / 1000 (size 238, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 75, 2,008, 574 Triangles, simulation 3,306,378 in 155 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 110 MB 1.2 GB STEP 477 MB 1.4 GB STL 165 MB 1.2 GB OBJ 343 MB 2.1 GB Visual GLB 94 MB 1.5 GB OBJ 297 MB 1.9 GB

1241. vario

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	2.7	12.9	0.5 ms	16.1	0.4	1.4	0.3	34.5
Simulation, STEP	0.6	2.6	12.3	1 ms	15.8	7.9	1.3	0.3	40.8
Simulation, STL	0.5	2.5	12.2	1 ms	15.8	1.0	1.3	0.3	33.6
Simulation, OBJ	0.5	2.6	12.2	1.0 ms	16.0	14.0	1.4	0.3	47.1
Visual, GLB	0.5	2.8	12.5	1 ms	30.0	0.4	4.7	0.2	51.2
Visual, OBJ	0.6	2.6	12.4	1 ms	28.8	13.2	5.3	0.3	63.2

Board Repo: imihajlow/ccpu Board: vario.kicad_pcb Folder boards / vario Complexity 263 / 1000 (size 208, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 117, 2,905, 737 Triangles, simulation 3,018,872 in 181 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 105 MB 1.1 GB STEP 485 MB 1.4 GB STL 151 MB 1.1 GB OBJ 322 MB 2.0 GB Visual GLB 93 MB 1.5 GB OBJ 296 MB 1.9 GB

1242. vga

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	3.7	19.1	1 ms	19.1	0.6	1.9	0.4	45.6
Simulation, STEP	0.6	3.5	20.4	1.0 ms	20.7	13.5	1.8	0.4	61.0
Simulation, STL	0.8	3.6	20.0	1 ms	19.8	1.4	1.6	0.3	47.5
Simulation, OBJ	0.7	3.4	19.6	0.6 ms	19.7	22.3	1.6	0.3	67.7
Visual, GLB	0.6	3.4	19.6	3 ms	39.9	0.5	4.7	0.4	69.0
Visual, OBJ	0.7	3.3	21.7	1 ms	39.0	16.9	4.6	0.3	86.5

Board Repo: imihajlow/ccpu Board: vga.kicad_pcb Folder boards / vga Complexity 300 / 1000 (size 245, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 80, 3,075, 715 Triangles, simulation 3,380,028 in 171 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 116 MB 1.2 GB STEP 593 MB 1.5 GB STL 169 MB 1.1 GB OBJ 358 MB 2.2 GB Visual GLB 95 MB 1.6 GB OBJ 302 MB 2.0 GB

1243. 4in1-panel

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.5	51.4	65.0	2 ms	62.1	2.7	8.3	0.5	191.7
Simulation, STEP	1.6	51.7	64.6	2 ms	61.0	23.9	8.6	0.5	211.8
Simulation, STL	1.8	50.9	64.2	2 ms	62.6	5.8	8.6	0.6	194.4
Simulation, OBJ	1.6	53.4	63.9	2 ms	62.7	80.3	8.9	0.6	271.3
Visual, GLB	1.6	53.2	65.0	4 ms	215.5	1.0	11.5	0.4	348.3
Visual, OBJ	1.6	51.6	62.2	2 ms	212.4	29.0	11.5	0.4	368.7

Board Repo: incutec-hw/openesc-30x30 Board: 4in1-panel.kicad_pcb Folder hardware Complexity 464 / 1000 (size 259, features 205) KESE features through vias, padstacks, custom pads, rounded, trapezoid or chamfered pads, drill offsets, filled zones, copper drawings, curved board outline, TrueType text, stack-up, dielectric εr and tanδ, copper finish, plated board edge Tested 9th November 2026 Copper layers 6 File format KiCad 10 (20260206) Parts, tracks, vias 388, 2,655, 2,604 Triangles, simulation 13,067,554 in 279 parts Note panel Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 427 MB 2.9 GB STEP 1.4 GB 3.8 GB STL 653 MB 2.8 GB OBJ 1.4 GB 8.0 GB Visual GLB 196 MB 3.4 GB OBJ 636 MB 4.2 GB

1244. 4in1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	14.9	31.9	1 ms	29.5	1.4	3.5	0.3	82.3
Simulation, STEP	0.8	15.5	32.6	1 ms	29.9	12.2	3.9	0.4	95.3
Simulation, STL	0.7	15.9	32.9	1 ms	30.4	2.7	3.4	0.4	86.4
Simulation, OBJ	0.8	15.4	32.8	1 ms	29.0	35.4	3.8	0.3	117.5
Visual, GLB	0.8	14.9	33.3	1 ms	107.0	0.4	5.2	0.3	162.0
Visual, OBJ	0.8	15.1	32.7	1 ms	102.7	15.7	5.6	0.3	173.0

Board Repo: incutec-hw/openesc-30x30 Board: 4in1.kicad_pcb Folder hardware Complexity 415 / 1000 (size 245, features 170) KESE features through vias, padstacks, rounded, trapezoid or chamfered pads, drill offsets, filled zones, TrueType text, stack-up, dielectric εr and tanδ, copper finish, plated board edge Tested 9th November 2026 Copper layers 6 File format KiCad 10 (20260206) Parts, tracks, vias 214, 1,220, 1,702 Triangles, simulation 7,517,890 in 211 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 243 MB 1.6 GB STEP 760 MB 2.2 GB STL 376 MB 1.6 GB OBJ 786 MB 4.6 GB Visual GLB 113 MB 2.3 GB OBJ 366 MB 2.4 GB

1245. H745 CM4 module

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	3.2	8.0	1 ms	10.2	0.6	1.6	0.3	24.5
Simulation, STEP	0.5	3.4	8.1	1 ms	10.6	6.3	1.6	0.3	30.8
Simulation, STL	0.5	3.1	8.2	1 ms	10.6	1.2	1.5	0.3	25.4
Simulation, OBJ	0.6	3.4	8.1	2 ms	10.3	14.6	1.5	0.3	38.7
Visual, GLB	0.5	3.2	8.1	1 ms	23.1	0.3	2.4	0.2	37.8
Visual, OBJ	0.5	3.3	7.6	1.0 ms	21.4	8.1	2.8	0.3	44.0

Board Repo: intergalaktik/bb3-cm4 Board: H745 CM4 module.kicad_pcb Folder EEZ_BB3_CM4_H7 Complexity 356 / 1000 (size 271, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 6 File format KiCad 7 (20221018) Parts, tracks, vias 110, 2,859, 483 Triangles, simulation 3,491,940 in 292 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 119 MB 1.1 GB STEP 439 MB 1.3 GB STL 175 MB 1.0 GB OBJ 375 MB 2.3 GB Visual GLB 65 MB 1.2 GB OBJ 213 MB 1.5 GB

1246. EEZ_BB3_CM4_R1B0

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.7	8.0	38.2	1 ms	29.3	1.5	4.0	0.4	83.0
Simulation, STEP	1.7	7.7	38.0	1 ms	29.0	16.7	3.9	0.5	97.5
Simulation, STL	1.8	8.2	36.2	2 ms	29.2	3.2	3.4	0.4	82.5
Simulation, OBJ	1.6	7.6	35.5	1 ms	29.6	39.3	3.9	0.4	118.0
Visual, GLB	1.8	8.0	37.4	2 ms	71.5	0.8	7.8	0.3	127.6
Visual, OBJ	1.8	8.4	36.6	1 ms	72.0	23.1	9.2	0.4	151.5

Board Repo: intergalaktik/bb3-cm4 Board: EEZ_BB3_CM4_R1B0.kicad_pcb Folder EEZ_BB3_CM4_R1B0 Complexity 376 / 1000 (size 281, features 95) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 6 (20211014) Parts, tracks, vias 239, 5,730, 914 Triangles, simulation 7,322,202 in 347 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 252 MB 2.0 GB STEP 1.1 GB 2.5 GB STL 366 MB 1.9 GB OBJ 799 MB 4.7 GB Visual GLB 149 MB 2.5 GB OBJ 480 MB 3.2 GB

1247. EEZ_DIB_BP3C_r3B3

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	3.0	12.4	0.7 ms	10.9	0.5	1.6	0.3	29.4
Simulation, STEP	0.7	3.2	12.8	0.7 ms	10.8	6.4	1.6	0.3	35.9
Simulation, STL	0.8	3.2	12.9	0.7 ms	11.3	0.9	1.6	0.4	31.2
Simulation, OBJ	0.7	3.3	13.8	0.7 ms	10.8	15.8	1.9	0.4	46.7
Visual, GLB	0.8	3.2	14.2	0.7 ms	21.9	0.3	2.0	0.4	42.7
Visual, OBJ	0.9	4.2	13.7	0.8 ms	23.7	7.8	1.9	0.3	52.5

Board Repo: intergalaktik/bb3-cm4 Board: EEZ_DIB_BP3C_r3B3.kicad_pcb Folder EEZ_BB3_CM4_R1B0 Complexity 288 / 1000 (size 193, features 95) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 6 (20211014) Parts, tracks, vias 55, 718, 161 Triangles, simulation 2,232,070 in 92 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 78 MB 652 MB STEP 333 MB 847 MB STL 112 MB 684 MB OBJ 240 MB 1.5 GB Visual GLB 43 MB 856 MB OBJ 131 MB 974 MB

1248. EEZ_DIB_MCU_r3B4

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.2	5.9	21.7	0.8 ms	19.7	0.8	2.0	0.3	51.7
Simulation, STEP	1.2	5.9	21.2	0.8 ms	19.5	11.4	2.0	0.3	61.4
Simulation, STL	1.2	5.7	21.4	0.8 ms	19.5	1.4	2.0	0.3	51.7
Simulation, OBJ	1.2	5.6	21.6	2 ms	19.6	27.9	2.0	0.3	78.2
Visual, GLB	1.2	5.8	21.9	0.8 ms	41.4	0.5	3.7	0.3	74.8
Visual, OBJ	1.2	5.9	22.1	0.8 ms	42.0	16.5	3.6	0.3	91.6

Board Repo: intergalaktik/bb3-cm4 Board: EEZ_DIB_MCU_r3B4.kicad_pcb Folder EEZ_BB3_CM4_R1B0 Complexity 371 / 1000 (size 276, features 95) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 6 (20211014) Parts, tracks, vias 185, 5,012, 755 Triangles, simulation 5,098,868 in 274 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 174 MB 1.4 GB STEP 787 MB 1.9 GB STL 255 MB 1.5 GB OBJ 549 MB 3.3 GB Visual GLB 106 MB 1.8 GB OBJ 342 MB 2.4 GB

1249. EEZ_BB3_CM4_SoM

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	84 ms	87 ms	0.2	0.6 ms	0.7	17 ms	74 ms	0.2	1.4
Simulation, STEP	0.1	90 ms	0.3	0.3 ms	0.7	0.4	63 ms	0.2	1.8
Simulation, STL	99 ms	89 ms	0.2	0.3 ms	0.6	26 ms	66 ms	0.2	1.3
Simulation, OBJ	85 ms	75 ms	0.2	0.4 ms	0.6	0.2	56 ms	0.2	1.4
Visual, GLB	95 ms	89 ms	0.2	0.4 ms	1.5	11 ms	83 ms	0.2	2.2
Visual, OBJ	0.1	93 ms	0.2	0.5 ms	1.5	0.2	69 ms	0.2	2.4

Board Repo: intergalaktik/bb3-cm4 Board: EEZ_BB3_CM4_SoM.kicad_pcb Folder EEZ_BB3_CM4_SoM Complexity 75 / 1000 (size 45, features 30) KESE features stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 2, 0, 0 Triangles, simulation 32,988 in 181 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 1.3 MB 75 MB STEP 6.6 MB 78 MB STL 1.7 MB 74 MB OBJ 3.8 MB 81 MB Visual GLB 1.8 MB 118 MB OBJ 5.0 MB 115 MB

1250. EEZ_DIB_BP3C_r3B3

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	2.5	10.6	0.4 ms	9.0	0.4	1.3	0.3	24.6
Simulation, STEP	0.6	2.5	10.5	0.7 ms	8.9	4.9	1.4	0.3	29.1
Simulation, STL	0.5	2.7	10.7	0.8 ms	9.0	0.7	1.4	0.3	25.4
Simulation, OBJ	0.6	2.6	10.7	0.5 ms	8.8	12.0	1.3	0.3	36.2
Visual, GLB	0.5	2.5	11.1	1 ms	20.0	0.2	1.7	0.2	36.3
Visual, OBJ	0.6	2.6	10.8	0.3 ms	19.2	6.4	2.3	0.3	42.2

Board Repo: intergalaktik/bb3-cm4 Board: EEZ_DIB_BP3C_r3B3.kicad_pcb Folder EEZ_DIB_BP3C_R3B3 Complexity 288 / 1000 (size 193, features 95) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 6 (20211014) Parts, tracks, vias 55, 718, 161 Triangles, simulation 2,205,946 in 89 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 77 MB 660 MB STEP 328 MB 851 MB STL 110 MB 701 MB OBJ 238 MB 1.5 GB Visual GLB 42 MB 904 MB OBJ 128 MB 958 MB

1251. EEZ_DIB_MCU_r3B4

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.9	4.6	14.6	0.9 ms	13.6	0.6	1.9	0.3	36.6
Simulation, STEP	0.7	4.6	13.8	1 ms	13.2	8.9	1.8	0.3	43.3
Simulation, STL	0.7	4.4	14.0	1 ms	12.9	1.3	1.8	0.4	35.5
Simulation, OBJ	0.9	4.8	13.9	0.9 ms	12.6	19.5	1.6	0.3	53.5
Visual, GLB	0.8	4.5	13.1	1 ms	32.6	0.3	4.1	0.3	55.7
Visual, OBJ	0.6	4.5	14.1	1 ms	34.4	12.6	5.0	0.2	71.4

Board Repo: intergalaktik/bb3-cm4 Board: EEZ_DIB_MCU_r3B4.kicad_pcb Folder EEZ_DIB_MCU_r3B4 Complexity 359 / 1000 (size 264, features 95) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 118, 2,912, 638 Triangles, simulation 3,889,020 in 275 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 131 MB 1.1 GB STEP 509 MB 1.6 GB STL 194 MB 1.2 GB OBJ 414 MB 2.6 GB Visual GLB 86 MB 1.4 GB OBJ 274 MB 1.8 GB

1252. Intergalaktik_proto

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.9	0.9	10.0	0.5 ms	12.5	0.3	0.7	0.3	25.5
Simulation, STEP	0.8	0.9	9.9	0.4 ms	13.0	5.5	0.6	0.3	30.8
Simulation, STL	0.8	0.9	9.6	0.3 ms	12.5	0.4	0.6	0.2	25.1
Simulation, OBJ	0.8	0.9	9.6	0.3 ms	12.8	9.1	0.6	0.2	34.1
Visual, GLB	0.8	0.9	9.6	0.6 ms	16.9	0.2	1.0	0.3	29.7
Visual, OBJ	0.9	0.9	9.7	0.5 ms	17.0	4.1	1.0	0.3	33.9

Board Repo: intergalaktik/business-card-smd-proto Board: Intergalaktik_proto.kicad_pcb Folder KiCad / Intergalaktik_proto Complexity 183 / 1000 (size 98, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper drawings, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 0, 119, 8 Triangles, simulation 1,533,816 in 24 parts Note no components Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 53 MB 649 MB STEP 319 MB 826 MB STL 77 MB 683 MB OBJ 161 MB 1.1 GB Visual GLB 24 MB 675 MB OBJ 74 MB 652 MB

1253. EMC_antenna

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	85 ms	0.2	0.1 ms	0.4	10 ms	28 ms	0.2	1.1
Simulation, STEP	0.1	84 ms	0.2	0.1 ms	0.4	0.7	27 ms	0.2	1.8
Simulation, STL	0.1	0.1	0.2	0.1 ms	0.4	17 ms	25 ms	0.2	1.1
Simulation, OBJ	0.1	83 ms	0.2	0.1 ms	0.4	0.3	42 ms	0.2	1.4
Visual, GLB	0.1	93 ms	0.2	0.1 ms	0.4	9 ms	0.1	0.2	1.2
Visual, OBJ	0.1	79 ms	0.2	0.1 ms	0.4	0.3	0.1	0.2	1.4

Board Repo: intergalaktik/EMC-experiments Board: EMC_antenna.kicad_pcb Folder EMC_antenna Complexity 69 / 1000 (size 24, features 45) KESE features arc tracks, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 1, 0, 0 Triangles, simulation 75,346 in 9 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 2.8 MB 79 MB STEP 19 MB 193 MB STL 3.8 MB 76 MB OBJ 7.6 MB 107 MB Visual GLB 2.1 MB 115 MB OBJ 5.7 MB 142 MB

1254. adcIO

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.6	1.8	0.4 ms	2.1	99 ms	0.3	0.3	5.4
Simulation, STEP	0.3	0.6	1.8	0.4 ms	2.1	1.8	0.3	0.2	7.1
Simulation, STL	0.3	0.6	1.8	0.3 ms	2.0	0.2	0.3	0.2	5.3
Simulation, OBJ	0.3	0.5	1.8	0.4 ms	2.0	3.0	0.4	0.3	8.2
Visual, GLB	0.3	0.5	2.0	0.4 ms	4.6	64 ms	0.6	0.2	8.3
Visual, OBJ	0.3	0.5	1.7	0.5 ms	4.7	2.0	0.6	0.3	10.1

Board Repo: intergalaktik/Extension_Boards_for_Olimex_GateMate Board: adcIO.kicad_pcb Folder adcIO Complexity 286 / 1000 (size 171, features 115) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 36, 212, 66 Triangles, simulation 640,134 in 52 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 22 MB 355 MB STEP 96 MB 393 MB STL 32 MB 390 MB OBJ 65 MB 469 MB Visual GLB 15 MB 392 MB OBJ 43 MB 383 MB

1255. camIO

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.4	1.0	0.2 ms	1.1	58 ms	0.2	0.2	3.1
Simulation, STEP	0.2	0.4	1.0	0.2 ms	1.2	1.1	0.2	0.2	4.2
Simulation, STL	0.2	0.4	1.0	0.1 ms	1.2	0.1	0.2	0.2	3.2
Simulation, OBJ	0.2	0.4	1.0	0.2 ms	1.2	1.8	0.2	0.2	4.9
Visual, GLB	0.2	0.4	1.0	0.2 ms	3.0	49 ms	0.4	0.2	5.3
Visual, OBJ	0.2	0.4	1.0	0.3 ms	3.0	1.3	0.3	0.2	6.4

Board Repo: intergalaktik/Extension_Boards_for_Olimex_GateMate Board: camIO.kicad_pcb Folder camIO Complexity 286 / 1000 (size 171, features 115) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 25, 296, 76 Triangles, simulation 422,226 in 40 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 15 MB 290 MB STEP 66 MB 323 MB STL 21 MB 303 MB OBJ 43 MB 337 MB Visual GLB 12 MB 321 MB OBJ 34 MB 315 MB

1256. dualTranslation

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.1	5.4	0.3 ms	4.2	0.2	0.5	0.3	12.2
Simulation, STEP	0.4	1.1	5.3	0.2 ms	4.5	3.0	0.5	0.3	15.1
Simulation, STL	0.4	1.3	5.2	0.3 ms	4.2	0.3	0.6	0.3	12.2
Simulation, OBJ	0.4	1.2	5.3	0.3 ms	4.5	6.2	0.6	0.3	18.5
Visual, GLB	0.4	1.1	4.9	0.3 ms	9.4	0.1	0.8	0.2	17.0
Visual, OBJ	0.4	1.3	5.1	0.5 ms	9.6	4.0	0.9	0.3	21.5

Board Repo: intergalaktik/Extension_Boards_for_Olimex_GateMate Board: dualTranslation.kicad_pcb Folder dualTranslation Complexity 273 / 1000 (size 188, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 54, 521, 119 Triangles, simulation 941,732 in 56 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 33 MB 477 MB STEP 153 MB 504 MB STL 47 MB 443 MB OBJ 97 MB 690 MB Visual GLB 21 MB 537 MB OBJ 64 MB 528 MB

1257. dvi

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.5	1.6	0.3 ms	1.7	84 ms	0.3	0.2	4.9
Simulation, STEP	0.3	0.5	1.6	0.3 ms	1.8	1.6	0.3	0.2	6.3
Simulation, STL	0.3	0.6	1.6	0.3 ms	1.8	0.1	0.3	0.2	4.9
Simulation, OBJ	0.3	0.6	1.7	0.5 ms	1.9	3.2	0.3	0.2	8.2
Visual, GLB	0.3	0.6	1.8	0.2 ms	4.8	88 ms	0.5	0.3	8.4
Visual, OBJ	0.3	0.6	1.6	0.3 ms	4.8	2.3	0.6	0.2	10.5

Board Repo: intergalaktik/Extension_Boards_for_Olimex_GateMate Board: dvi.kicad_pcb Folder dvi Complexity 285 / 1000 (size 185, features 100) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 47, 518, 89 Triangles, simulation 576,678 in 53 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 20 MB 339 MB STEP 91 MB 384 MB STL 29 MB 331 MB OBJ 58 MB 439 MB Visual GLB 15 MB 403 MB OBJ 45 MB 403 MB

1258. eduIO

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	1.2	0.2 ms	1.2	53 ms	0.2	0.2	3.4
Simulation, STEP	0.2	0.3	1.3	0.5 ms	1.2	1.3	0.2	0.2	4.7
Simulation, STL	0.2	0.3	1.3	0.3 ms	1.2	85 ms	0.2	0.2	3.5
Simulation, OBJ	0.2	0.3	1.3	0.3 ms	1.3	1.6	0.2	0.2	5.1
Visual, GLB	0.2	0.3	1.3	0.5 ms	3.2	49 ms	0.3	0.3	5.7
Visual, OBJ	0.2	0.4	1.3	0.3 ms	3.2	1.2	0.4	0.2	7.0

Board Repo: intergalaktik/Extension_Boards_for_Olimex_GateMate Board: eduIO.kicad_pcb Folder eduIO Complexity 257 / 1000 (size 142, features 115) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 22, 180, 25 Triangles, simulation 305,672 in 65 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 11 MB 246 MB STEP 52 MB 279 MB STL 15 MB 245 MB OBJ 31 MB 270 MB Visual GLB 8.7 MB 272 MB OBJ 25 MB 271 MB

1259. ethIO

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.0	3.1	0.2 ms	2.7	0.1	0.4	0.2	7.9
Simulation, STEP	0.4	1.0	2.8	0.3 ms	2.7	2.1	0.4	0.3	9.6
Simulation, STL	0.3	0.9	3.0	0.3 ms	2.6	0.2	0.4	0.2	7.8
Simulation, OBJ	0.3	1.0	2.9	0.2 ms	2.7	4.5	0.4	0.2	12.1
Visual, GLB	0.3	1.0	2.9	0.2 ms	6.8	0.1	0.6	0.2	11.9
Visual, OBJ	0.3	1.0	3.1	0.2 ms	6.5	2.9	0.8	0.2	14.9

Board Repo: intergalaktik/Extension_Boards_for_Olimex_GateMate Board: ethIO.kicad_pcb Folder ethIO Complexity 320 / 1000 (size 190, features 130) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 46, 708, 122 Triangles, simulation 860,620 in 62 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 30 MB 379 MB STEP 141 MB 457 MB STL 43 MB 379 MB OBJ 89 MB 626 MB Visual GLB 20 MB 466 MB OBJ 61 MB 489 MB

1260. extension_template

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.2	0.4	0.1 ms	0.7	22 ms	55 ms	0.2	1.7
Simulation, STEP	0.1	0.1	0.4	0.2 ms	0.6	0.9	69 ms	0.2	2.5
Simulation, STL	0.2	0.2	0.4	0.1 ms	0.6	40 ms	61 ms	0.2	1.7
Simulation, OBJ	0.2	0.2	0.4	0.2 ms	0.6	0.7	80 ms	0.3	2.4
Visual, GLB	0.1	0.1	0.4	0.1 ms	1.5	23 ms	0.2	0.2	2.6
Visual, OBJ	0.1	0.1	0.4	0.1 ms	1.6	0.5	0.2	0.2	3.1

Board Repo: intergalaktik/Extension_Boards_for_Olimex_GateMate Board: extension_template.kicad_pcb Folder extension_template Complexity 241 / 1000 (size 126, features 115) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 7, 51, 6 Triangles, simulation 139,358 in 36 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 5.0 MB 213 MB STEP 28 MB 220 MB STL 7.0 MB 211 MB OBJ 14 MB 205 MB Visual GLB 4.4 MB 170 MB OBJ 12 MB 179 MB

1261. GamePad_I2S_audio

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.4	0.6	0.2 ms	0.7	31 ms	91 ms	0.3	2.4
Simulation, STEP	0.3	0.4	0.7	0.3 ms	0.7	1.3	80 ms	0.3	3.7
Simulation, STL	0.3	0.4	0.7	0.4 ms	0.7	41 ms	73 ms	0.3	2.5
Simulation, OBJ	0.3	0.3	0.6	0.2 ms	0.7	0.7	67 ms	0.3	3.0
Visual, GLB	0.3	0.4	0.6	0.4 ms	2.0	26 ms	0.2	0.2	3.7
Visual, OBJ	0.3	0.4	0.6	0.2 ms	2.3	0.8	0.2	0.2	4.7

Board Repo: intergalaktik/Extension_Boards_for_Olimex_GateMate Board: GamePad_I2S_audio.kicad_pcb Folder GamePad_I2S_audio / KiCad Complexity 265 / 1000 (size 180, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 81, 268, 51 Triangles, simulation 131,540 in 65 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 4.8 MB 213 MB STEP 21 MB 215 MB STL 6.6 MB 212 MB OBJ 14 MB 207 MB Visual GLB 4.7 MB 197 MB OBJ 13 MB 200 MB

1262. GamePad_I2S_audio

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	0.8	3.2	0.4 ms	3.2	0.1	0.6	0.2	8.5
Simulation, STEP	0.4	0.9	3.1	0.3 ms	3.1	2.7	0.5	0.2	10.8
Simulation, STL	0.4	0.9	2.9	0.3 ms	3.0	0.2	0.5	0.2	8.1
Simulation, OBJ	0.4	0.9	3.0	0.4 ms	3.4	4.7	0.5	0.2	13.0
Visual, GLB	0.4	0.9	3.0	0.4 ms	6.8	0.1	0.6	0.2	12.0
Visual, OBJ	0.4	0.9	3.0	0.4 ms	7.1	3.6	0.6	0.2	15.8

Board Repo: intergalaktik/Extension_Boards_for_Olimex_GateMate Board: GamePad_I2S_audio.kicad_pcb Folder GamePad_I2S_audio_Buttons / KiCad Complexity 280 / 1000 (size 195, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 77, 713, 127 Triangles, simulation 866,552 in 91 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 30 MB 404 MB STEP 135 MB 500 MB STL 43 MB 405 MB OBJ 88 MB 619 MB Visual GLB 23 MB 579 MB OBJ 69 MB 516 MB

1263. MikroBusIO

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	0.8	2.6	0.4 ms	2.6	0.1	0.5	0.2	7.3
Simulation, STEP	0.4	0.8	2.6	0.4 ms	2.7	2.1	0.5	0.2	9.3
Simulation, STL	0.4	0.8	2.6	0.3 ms	2.6	0.2	0.5	0.2	7.4
Simulation, OBJ	0.4	0.9	2.6	0.4 ms	2.6	4.4	0.5	0.2	11.6
Visual, GLB	0.4	0.8	2.7	0.3 ms	6.6	95 ms	0.6	0.2	11.4
Visual, OBJ	0.4	0.8	2.7	0.3 ms	6.5	3.3	0.7	0.2	14.5

Board Repo: intergalaktik/Extension_Boards_for_Olimex_GateMate Board: MikroBusIO.kicad_pcb Folder MikroBusIO Complexity 300 / 1000 (size 185, features 115) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 55, 388, 109 Triangles, simulation 755,740 in 59 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 26 MB 382 MB STEP 111 MB 432 MB STL 38 MB 396 MB OBJ 77 MB 537 MB Visual GLB 19 MB 473 MB OBJ 58 MB 479 MB

1264. pwrIO

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.6	1.7	0.3 ms	1.8	93 ms	0.3	0.2	5.0
Simulation, STEP	0.3	0.6	1.8	0.3 ms	1.8	1.7	0.4	0.3	6.7
Simulation, STL	0.3	0.6	1.9	0.3 ms	1.7	0.2	0.4	0.2	5.3
Simulation, OBJ	0.4	0.6	1.7	0.3 ms	1.7	3.3	0.4	0.2	8.3
Visual, GLB	0.3	0.6	1.8	0.3 ms	4.8	73 ms	0.5	0.2	8.3
Visual, OBJ	0.3	0.6	1.8	0.3 ms	5.3	2.3	0.5	0.2	11.1

Board Repo: intergalaktik/Extension_Boards_for_Olimex_GateMate Board: pwrIO.kicad_pcb Folder pwrIO Complexity 255 / 1000 (size 180, features 75) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 45, 441, 59 Triangles, simulation 577,794 in 60 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 20 MB 329 MB STEP 94 MB 370 MB STL 29 MB 324 MB OBJ 59 MB 434 MB Visual GLB 15 MB 394 MB OBJ 44 MB 409 MB

1265. simpleIO

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.5	1.4	0.3 ms	1.7	84 ms	0.3	0.2	4.4
Simulation, STEP	0.2	0.5	1.3	0.3 ms	1.8	1.6	0.3	0.2	5.9
Simulation, STL	0.2	0.5	1.5	0.3 ms	1.8	0.2	0.3	0.2	4.6
Simulation, OBJ	0.3	0.5	1.4	0.3 ms	1.9	2.7	0.3	0.2	7.4
Visual, GLB	0.2	0.5	1.4	0.3 ms	4.2	55 ms	0.4	0.2	7.0
Visual, OBJ	0.3	0.5	1.4	0.2 ms	3.8	2.3	0.5	0.2	9.0

Board Repo: intergalaktik/Extension_Boards_for_Olimex_GateMate Board: simpleIO.kicad_pcb Folder simpleIO / KiCad Complexity 252 / 1000 (size 177, features 75) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 48, 247, 82 Triangles, simulation 455,592 in 69 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 16 MB 289 MB STEP 63 MB 350 MB STL 23 MB 288 MB OBJ 46 MB 370 MB Visual GLB 12 MB 365 MB OBJ 36 MB 345 MB

1266. tmrIO

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.4	1.2	0.3 ms	1.2	56 ms	0.2	0.2	3.6
Simulation, STEP	0.2	0.4	1.3	0.2 ms	1.2	1.2	0.2	0.2	4.7
Simulation, STL	0.2	0.4	1.2	0.4 ms	1.1	86 ms	0.2	0.2	3.4
Simulation, OBJ	0.2	0.4	1.3	0.2 ms	1.1	1.7	0.2	0.2	5.1
Visual, GLB	0.3	0.4	1.2	0.3 ms	3.0	46 ms	0.4	0.2	5.5
Visual, OBJ	0.3	0.4	1.3	0.3 ms	3.2	1.3	0.3	0.2	6.9

Board Repo: intergalaktik/Extension_Boards_for_Olimex_GateMate Board: tmrIO.kicad_pcb Folder tmrIO Complexity 270 / 1000 (size 170, features 100) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 23, 282, 76 Triangles, simulation 442,664 in 51 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 15 MB 304 MB STEP 62 MB 318 MB STL 22 MB 291 MB OBJ 45 MB 339 MB Visual GLB 11 MB 309 MB OBJ 33 MB 315 MB

1267. USB

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	0.9	2.7	0.4 ms	3.0	0.1	0.5	0.3	7.8
Simulation, STEP	0.4	0.9	2.7	0.3 ms	3.0	2.3	0.5	0.2	9.9
Simulation, STL	0.3	0.9	2.7	0.4 ms	2.9	0.2	0.5	0.2	7.8
Simulation, OBJ	0.3	0.9	2.8	0.2 ms	2.8	4.4	0.5	0.2	11.9
Visual, GLB	0.3	0.8	2.7	0.4 ms	5.7	84 ms	0.6	0.2	10.5
Visual, OBJ	0.3	0.9	2.6	0.3 ms	5.4	3.1	0.7	0.2	13.2

Board Repo: intergalaktik/Extension_Boards_for_Olimex_GateMate Board: USB.kicad_pcb Folder USB Complexity 285 / 1000 (size 185, features 100) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 38, 364, 189 Triangles, simulation 760,970 in 51 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 26 MB 402 MB STEP 102 MB 458 MB STL 38 MB 421 MB OBJ 77 MB 553 MB Visual GLB 18 MB 482 MB OBJ 55 MB 448 MB

1268. intergalaktik

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	74 ms	0.3	0.1 ms	0.4	13 ms	39 ms	0.2	1.2
Simulation, STEP	97 ms	71 ms	0.2	0.1 ms	0.4	0.7	43 ms	0.2	1.8
Simulation, STL	0.1	73 ms	0.3	0.2 ms	0.5	21 ms	39 ms	0.2	1.2
Simulation, OBJ	0.1	76 ms	0.3	0.1 ms	0.5	0.4	47 ms	0.2	1.5
Visual, GLB	0.1	71 ms	0.3	0.1 ms	0.8	8 ms	73 ms	0.3	1.7
Visual, OBJ	94 ms	67 ms	0.2	0.1 ms	0.9	0.2	61 ms	0.2	1.8

Board Repo: intergalaktik/KiCad-PCB Board: intergalaktik.kicad_pcb Folder hardware Complexity 160 / 1000 (size 80, features 80) KESE features rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 3, 6, 0 Triangles, simulation 68,008 in 16 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 2.4 MB 169 MB STEP 9.1 MB 176 MB STL 3.4 MB 167 MB OBJ 6.6 MB 171 MB Visual GLB 1.4 MB 152 MB OBJ 4.0 MB 151 MB

1269. mono_addon

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.6	5.1	0.3 ms	2.9	0.1	0.4	0.2	9.7
Simulation, STEP	0.3	0.6	5.2	0.4 ms	2.9	2.3	0.4	0.2	12.0
Simulation, STL	0.3	0.6	5.5	0.6 ms	2.8	0.2	0.5	0.2	10.2
Simulation, OBJ	0.3	0.6	5.0	0.3 ms	2.8	4.1	0.4	0.2	13.6
Visual, GLB	0.3	0.7	5.4	0.3 ms	8.7	84 ms	0.7	0.3	16.1
Visual, OBJ	0.3	0.6	5.2	0.3 ms	8.6	3.1	0.7	0.2	18.8

Board Repo: intergalaktik/mono_addon Board: mono_addon.kicad_pcb Folder KiCad / mono_addon Complexity 271 / 1000 (size 161, features 110) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 44, 238, 95 Triangles, simulation 764,454 in 59 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 27 MB 399 MB STEP 163 MB 475 MB STL 38 MB 402 MB OBJ 81 MB 579 MB Visual GLB 20 MB 498 MB OBJ 58 MB 509 MB

1270. ulx4m-panel

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	4.0	22.4	72.7	5 ms	91.7	5.1	11.8	0.9	208.7
Simulation, STEP	4.5	23.2	71.9	4 ms	88.3	52.0	13.1	0.9	254.0
Simulation, STL	4.4	21.9	74.1	3 ms	90.4	9.4	11.0	0.8	211.9
Simulation, OBJ	5.1	26.6	89.5	6 ms	113.1	187.5	22.5	2.1	446.4
Visual, GLB	4.4	20.3	70.0	4 ms	208.0	2.0	24.5	0.6	329.9
Visual, OBJ	4.2	20.6	68.0	3 ms	215.5	64.0	24.3	0.6	397.4

Board Repo: intergalaktik/ULX4M Board: ulx4m-panel.kicad_pcb Folder plot / panel Complexity 402 / 1000 (size 357, features 45) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 to 11th November 2026 Copper layers 6 File format KiCad 5 (20171130) Parts, tracks, vias 860, 35,844, 2,856 Triangles, simulation 23,814,454 in 1200 parts Note panel Verifier PASS in all six runs Run again Simulation, OBJ: failed in the corpus run, run again with no memory cap and no time limit (swap added to a 16 GB machine), and passed

File type File size Peak memory used Simulation GLB 788 MB 5.3 GB STEP 3.2 GB 6.4 GB STL 1.2 GB 5.2 GB OBJ 2.6 GB 15 GB Visual GLB 446 MB 7.2 GB OBJ 1.5 GB 9.5 GB

1271. ulx4m

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.4	5.6	17.8	1 ms	22.2	1.0	2.9	0.3	51.4
Simulation, STEP	1.4	5.7	18.5	2 ms	22.9	14.2	3.0	0.4	66.1
Simulation, STL	1.4	5.6	18.4	0.8 ms	22.4	2.1	3.0	0.3	53.1
Simulation, OBJ	1.4	5.9	18.2	1 ms	22.4	35.2	3.0	0.3	86.4
Visual, GLB	1.5	6.0	18.3	1 ms	50.6	0.5	5.8	0.3	83.2
Visual, OBJ	1.4	6.0	18.6	2 ms	49.5	21.4	6.3	0.3	103.5

Board Repo: intergalaktik/ULX4M Board: ulx4m.kicad_pcb Folder plot / panel Complexity 361 / 1000 (size 306, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 6 File format KiCad 5 (20171130) Parts, tracks, vias 215, 8,961, 714 Triangles, simulation 5,933,356 in 312 parts Note panel Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 203 MB 1.5 GB STEP 778 MB 2.0 GB STL 297 MB 1.5 GB OBJ 635 MB 3.8 GB Visual GLB 112 MB 2.2 GB OBJ 367 MB 2.4 GB

1272. ulx4m

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.8	6.6	23.4	2 ms	26.6	1.3	3.9	0.4	64.0
Simulation, STEP	2.1	7.7	24.0	2 ms	26.2	16.6	4.2	0.4	81.1
Simulation, STL	1.8	6.8	24.3	2 ms	23.6	2.3	3.8	0.5	63.1
Simulation, OBJ	1.8	6.3	20.5	2 ms	24.0	38.8	3.5	0.4	95.3
Visual, GLB	1.7	6.2	19.4	1 ms	53.4	0.6	5.8	0.4	87.5
Visual, OBJ	1.6	6.0	19.7	3 ms	52.6	20.7	5.2	0.3	106.1

Board Repo: intergalaktik/ULX4M Board: ulx4m.kicad_pcb Complexity 390 / 1000 (size 305, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 6 File format KiCad 8 (20240108) Parts, tracks, vias 218, 8,560, 700 Triangles, simulation 5,597,444 in 372 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 187 MB 1.6 GB STEP 777 MB 1.9 GB STL 280 MB 1.6 GB OBJ 598 MB 3.6 GB Visual GLB 111 MB 1.9 GB OBJ 361 MB 2.4 GB

1273. ulx4m-cm4-hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.8	2.6	0.6 ms	3.2	0.1	0.6	0.2	7.7
Simulation, STEP	0.2	0.7	2.6	0.6 ms	3.2	2.5	0.5	0.3	9.9
Simulation, STL	0.2	0.7	2.6	0.5 ms	3.1	0.2	0.5	0.2	7.6
Simulation, OBJ	0.2	0.7	2.5	0.4 ms	3.3	4.2	0.5	0.2	11.6
Visual, GLB	0.2	0.8	2.6	0.5 ms	6.1	90 ms	0.8	0.3	10.8
Visual, OBJ	0.2	0.7	2.6	0.4 ms	6.3	2.8	0.8	0.2	13.6

Board Repo: intergalaktik/ULX4M-CM4-HAT Board: ulx4m-cm4-hat.kicad_pcb Complexity 241 / 1000 (size 186, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 37, 708, 95 Triangles, simulation 860,812 in 59 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 28 MB 374 MB STEP 112 MB 460 MB STL 43 MB 373 MB OBJ 86 MB 622 MB Visual GLB 19 MB 463 MB OBJ 57 MB 509 MB

1274. ulx4m-ld

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.4	5.0	16.7	1 ms	21.6	0.9	3.0	0.3	48.9
Simulation, STEP	1.4	5.1	17.2	0.9 ms	21.2	12.5	2.7	0.3	60.5
Simulation, STL	1.3	5.3	16.6	0.8 ms	21.4	2.0	2.7	0.3	49.7
Simulation, OBJ	1.3	5.1	16.9	1 ms	21.1	30.1	2.9	0.3	77.7
Visual, GLB	1.5	5.1	16.1	0.8 ms	49.5	0.6	7.2	0.3	80.2
Visual, OBJ	1.4	5.0	16.5	0.9 ms	50.4	17.5	4.9	0.3	96.0

Board Repo: intergalaktik/ULX4M-LD Board: ulx4m-ld.kicad_pcb Complexity 409 / 1000 (size 324, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 6 File format KiCad 8 (20240108) Parts, tracks, vias 253, 15,844, 801 Triangles, simulation 6,595,260 in 384 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 221 MB 1.8 GB STEP 945 MB 2.2 GB STL 330 MB 1.7 GB OBJ 707 MB 4.2 GB Visual GLB 135 MB 2.3 GB OBJ 440 MB 3.0 GB

1275. ulx4m_panel

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	5.2	22.8	86.8	4 ms	106.6	5.5	14.2	0.8	241.9
Simulation, STEP	5.1	22.7	84.5	4 ms	105.3	58.8	13.0	0.9	290.3
Simulation, STL	5.5	22.5	85.0	4 ms	105.8	11.2	13.0	0.9	243.9
Simulation, OBJ	5.5	24.7	91.1	4 ms	118.4	178.7	24.5	2.1	445.0
Visual, GLB	5.2	22.7	83.4	6 ms	269.6	3.0	25.6	0.7	410.2
Visual, OBJ	5.2	23.3	85.4	4 ms	270.1	78.5	26.3	0.6	489.4

Board Repo: intergalaktik/ULX4M-LS Board: ulx4m_panel.kicad_pcb Folder panel Complexity 432 / 1000 (size 357, features 75) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 to 11th November 2026 Copper layers 6 File format KiCad 8 (20240108) Parts, tracks, vias 872, 34,240, 2,800 Triangles, simulation 23,074,944 in 1440 parts Note panel Verifier PASS in all six runs Run again Simulation, OBJ: failed in the corpus run, run again with no memory cap and no time limit (swap added to a 16 GB machine), and passed

File type File size Peak memory used Simulation GLB 746 MB 4.8 GB STEP 3.5 GB 6.8 GB STL 1.2 GB 4.8 GB OBJ 2.6 GB 15 GB Visual GLB 451 MB 7.2 GB OBJ 1.5 GB 9.5 GB

1276. ULX4M-PCIe-IO_x4_half

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.4	6.1	21.0	2 ms	17.6	0.8	2.6	0.4	49.9
Simulation, STEP	1.5	6.0	21.4	3 ms	18.1	11.2	2.7	0.4	61.2
Simulation, STL	1.5	6.1	21.1	2 ms	17.8	2.1	2.8	0.3	51.8
Simulation, OBJ	1.4	6.2	21.4	2 ms	18.0	25.4	2.7	0.4	75.6
Visual, GLB	1.4	6.3	21.6	2 ms	47.3	0.6	7.0	0.3	84.5
Visual, OBJ	1.5	6.6	21.6	2 ms	47.6	16.8	6.7	0.3	101.1

Board Repo: intergalaktik/ULX4M-PCIe-IO Board: ULX4M-PCIe-IO_x4_half.kicad_pcb Folder kicad Complexity 341 / 1000 (size 231, features 110) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 118, 6,055, 477 Triangles, simulation 4,666,562 in 233 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 160 MB 1.6 GB STEP 718 MB 1.7 GB STL 233 MB 1.5 GB OBJ 503 MB 3.1 GB Visual GLB 112 MB 2.0 GB OBJ 357 MB 2.4 GB

1277. ULX4M_GPDI

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.1	3.8	0.9 ms	5.2	0.3	0.6	0.2	11.5
Simulation, STEP	0.3	1.1	4.0	0.3 ms	5.2	3.9	0.5	0.2	15.2
Simulation, STL	0.3	1.0	3.8	0.4 ms	5.1	0.4	0.6	0.2	11.5
Simulation, OBJ	0.3	1.1	3.7	0.6 ms	5.1	6.9	0.5	0.2	17.9
Visual, GLB	0.3	1.0	3.9	0.6 ms	11.4	0.2	1.6	0.2	18.6
Visual, OBJ	0.3	1.1	3.9	0.6 ms	11.4	5.0	1.8	0.3	23.9

Board Repo: intergalaktik/ULX4M_documents Board: ULX4M_GPDI.kicad_pcb Folder ULX4M_test Complexity 240 / 1000 (size 185, features 55) KESE features through vias, slotted holes, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 27, 690, 156 Triangles, simulation 1,632,014 in 83 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 57 MB 675 MB STEP 260 MB 849 MB STL 82 MB 704 MB OBJ 172 MB 1.2 GB Visual GLB 41 MB 864 MB OBJ 126 MB 929 MB

1278. ulx5m-gs_panel_checked_v002

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	5.7	24.6	80.1	4 ms	88.0	4.6	12.7	0.8	216.5
Simulation, STEP	5.9	23.0	76.3	3 ms	88.1	55.8	12.6	0.7	262.5
Simulation, STL	5.9	22.2	76.2	4 ms	90.9	10.7	13.4	0.9	220.1
Simulation, OBJ	7.1	27.0	94.8	4 ms	126.2	201.0	22.9	2.2	481.1
Visual, GLB	5.8	22.3	76.2	4 ms	305.0	2.9	33.0	0.7	445.8
Visual, OBJ	5.5	21.5	72.9	4 ms	289.5	78.4	26.9	0.6	495.3

Board Repo: intergalaktik/ulx5m-gs Board: ulx5m-gs_panel_checked_v002.kicad_pcb Folder hardware / panel Complexity 501 / 1000 (size 361, features 140) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 to 11th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 1,148, 30,512, 3,416 Triangles, simulation 25,478,436 in 1392 parts Note panel Verifier PASS in all six runs Run again Simulation, OBJ: failed in the corpus run, run again with no memory cap and no time limit (swap added to a 16 GB machine), and passed

File type File size Peak memory used Simulation GLB 822 MB 6.0 GB STEP 3.5 GB 7.6 GB STL 1.3 GB 6.1 GB OBJ 2.8 GB 16 GB Visual GLB 507 MB 8.0 GB OBJ 1.7 GB 11 GB

1279. ulx5m-gs

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.5	5.8	18.3	1 ms	25.8	1.0	3.1	0.5	56.0
Simulation, STEP	1.5	5.7	18.3	1 ms	26.1	13.7	3.1	0.4	68.9
Simulation, STL	1.6	6.0	17.3	1 ms	25.4	2.3	3.3	0.4	56.3
Simulation, OBJ	1.5	5.8	18.6	1 ms	26.4	33.7	3.2	0.4	89.6
Visual, GLB	1.6	5.7	17.3	1 ms	59.9	0.6	7.0	0.3	92.4
Visual, OBJ	1.5	5.8	18.0	2 ms	60.2	19.2	7.1	0.3	112.2

Board Repo: intergalaktik/ulx5m-gs Board: ulx5m-gs.kicad_pcb Folder hardware Complexity 460 / 1000 (size 310, features 150) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 287, 7,628, 854 Triangles, simulation 6,349,706 in 360 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 212 MB 1.5 GB STEP 844 MB 2.2 GB STL 318 MB 1.6 GB OBJ 677 MB 4.0 GB Visual GLB 127 MB 2.1 GB OBJ 409 MB 2.6 GB

1280. ulx5m-m2

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.6	3.7	10.4	1 ms	13.6	0.6	1.6	0.3	31.9
Simulation, STEP	1.4	3.8	9.9	2 ms	13.9	9.1	1.6	0.3	40.0
Simulation, STL	1.5	3.8	10.8	0.9 ms	14.4	1.3	1.8	0.3	33.9
Simulation, OBJ	1.4	3.8	10.7	1 ms	14.8	22.5	1.9	0.3	55.4
Visual, GLB	1.5	4.0	10.6	1 ms	37.6	0.4	4.0	0.3	58.4
Visual, OBJ	1.6	3.8	11.1	2 ms	39.2	13.3	4.2	0.3	73.4

Board Repo: intergalaktik/ulx5m-m2 Board: ulx5m-m2.kicad_pcb Complexity 405 / 1000 (size 295, features 110) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 6 File format KiCad 10 (20260206) Parts, tracks, vias 208, 4,044, 559 Triangles, simulation 3,982,396 in 294 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 134 MB 1.2 GB STEP 534 MB 1.5 GB STL 199 MB 1.1 GB OBJ 429 MB 2.6 GB Visual GLB 77 MB 1.5 GB OBJ 249 MB 1.7 GB

1281. arena_10_of_10_v1r1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.6	5.9	27.5	4 ms	38.5	1.7	3.5	0.4	80.0
Simulation, STEP	2.7	6.1	27.5	2 ms	36.4	21.3	3.2	0.3	97.5
Simulation, STL	2.7	5.8	27.0	4 ms	36.9	2.7	3.1	0.3	78.5
Simulation, OBJ	2.4	5.8	26.9	1 ms	38.0	44.2	3.5	0.4	121.3
Visual, GLB	2.6	6.0	27.4	1 ms	66.8	0.9	7.1	0.3	111.1
Visual, OBJ	2.8	6.7	30.0	1 ms	65.9	29.0	7.1	0.4	142.0

Board Repo: iorodeo/led-display_g6_hardware_arena Board: arena_10_of_10_v1r1.kicad_pcb Folder arena_10-10 / arena_10-10_v1 Complexity 402 / 1000 (size 262, features 140) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, tracks bare of mask, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 509, 8,133, 666 Triangles, simulation 7,355,260 in 516 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 244 MB 2.2 GB STEP 1.0 GB 2.7 GB STL 368 MB 2.1 GB OBJ 773 MB 4.6 GB Visual GLB 168 MB 2.7 GB OBJ 541 MB 3.5 GB

1282. arena_10_of_10_v1r1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.9	1.9	9.8	1 ms	10.0	0.3	0.6	0.2	23.8
Simulation, STEP	0.8	2.0	9.7	2 ms	10.3	6.4	0.7	0.2	30.1
Simulation, STL	0.9	2.0	9.8	1 ms	10.4	0.6	0.7	0.2	24.5
Simulation, OBJ	0.8	2.1	10.3	1 ms	10.0	10.5	0.7	0.2	34.6
Visual, GLB	0.7	2.0	9.6	1 ms	22.6	0.2	2.6	0.2	38.0
Visual, OBJ	0.7	1.9	9.3	2 ms	21.8	8.4	3.6	0.2	46.0

Board Repo: iorodeo/led-display_g6_hardware_arena Board: arena_10_of_10_v1r1.kicad_pcb Folder arena_10-10 / arena_10-10_v1 / layout_tool Complexity 94 / 1000 (size 84, features 10) KESE features rounded, trapezoid or chamfered pads Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 495, 0, 0 Triangles, simulation 2,474,306 in 511 parts Note mostly unrouted Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 83 MB 922 MB STEP 344 MB 1.2 GB STL 124 MB 931 MB OBJ 264 MB 1.7 GB Visual GLB 67 MB 1.3 GB OBJ 208 MB 1.5 GB

1283. modified_arena_10_of_10_v1r1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.1	1.7	5.6	2 ms	3.4	0.2	0.4	0.3	12.6
Simulation, STEP	1.1	1.7	5.5	0.8 ms	3.4	3.5	0.6	0.2	15.9
Simulation, STL	1.0	1.6	5.4	0.8 ms	3.7	0.3	0.5	0.3	12.8
Simulation, OBJ	1.1	1.8	5.6	1 ms	3.5	6.0	0.5	0.2	18.8
Visual, GLB	1.1	2.0	5.4	0.8 ms	8.5	0.1	1.1	0.3	18.6
Visual, OBJ	1.1	1.6	5.3	0.8 ms	8.8	4.5	1.1	0.2	22.6

Board Repo: iorodeo/led-display_g6_hardware_arena Board: modified_arena_10_of_10_v1r1.kicad_pcb Folder arena_10-10 / arena_10-10_v1 / layout_tool Complexity 104 / 1000 (size 84, features 20) KESE features rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 495, 0, 0 Triangles, simulation 990,208 in 253 parts Note mostly unrouted Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 34 MB 473 MB STEP 139 MB 576 MB STL 50 MB 458 MB OBJ 102 MB 715 MB Visual GLB 26 MB 633 MB OBJ 79 MB 671 MB

1284. arena_10_of_10_v1r1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.4	4.8	23.2	2 ms	22.3	1.1	2.3	0.3	55.4
Simulation, STEP	1.3	5.0	22.9	3 ms	23.0	16.0	2.4	0.4	71.0
Simulation, STL	1.3	4.6	23.7	2 ms	23.4	2.6	2.5	0.3	58.6
Simulation, OBJ	1.3	5.1	24.3	2 ms	22.4	34.3	2.3	0.3	90.0
Visual, GLB	1.4	5.2	22.7	2 ms	48.3	0.5	5.9	0.3	84.2
Visual, OBJ	1.5	4.9	23.2	2 ms	47.6	18.7	6.8	0.3	103.1

Board Repo: iorodeo/led-display_g6_hardware_arena Board: arena_10_of_10_v1r1.kicad_pcb Folder arena_10-10 / arena_10-10_v1 / manual_route / v1 Complexity 387 / 1000 (size 242, features 145) KESE features through vias, blind and buried vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, curved board outline, tracks bare of mask, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 505, 1,743, 403 Triangles, simulation 5,647,298 in 516 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 186 MB 1.5 GB STEP 659 MB 2.0 GB STL 282 MB 1.5 GB OBJ 591 MB 3.5 GB Visual GLB 103 MB 2.0 GB OBJ 327 MB 2.2 GB

1285. arena_10_of_10_v1r1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.7	5.7	22.2	3 ms	24.0	1.2	3.4	0.3	58.6
Simulation, STEP	1.6	5.7	23.9	2 ms	23.7	16.1	3.1	0.4	74.4
Simulation, STL	1.6	5.6	23.1	2 ms	24.2	2.4	3.4	0.4	60.6
Simulation, OBJ	1.5	5.3	21.9	2 ms	23.4	36.4	2.9	0.3	91.7
Visual, GLB	1.7	5.9	22.8	2 ms	49.6	0.5	7.2	0.3	88.1
Visual, OBJ	1.7	5.6	23.2	3 ms	48.6	17.8	8.3	0.3	105.5

Board Repo: iorodeo/led-display_g6_hardware_arena Board: arena_10_of_10_v1r1.kicad_pcb Folder arena_10-10 / arena_10-10_v1 / manual_route / v1 / routed Complexity 364 / 1000 (size 254, features 110) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, tracks bare of mask, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 505, 4,090, 677 Triangles, simulation 7,459,160 in 516 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 248 MB 1.9 GB STEP 815 MB 2.4 GB STL 373 MB 1.9 GB OBJ 787 MB 4.7 GB Visual GLB 128 MB 2.3 GB OBJ 413 MB 2.7 GB

1286. arena_10_of_10_v1r1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.2	4.1	21.4	2 ms	19.7	1.0	2.3	0.3	50.0
Simulation, STEP	1.0	4.2	21.8	2 ms	18.8	13.4	2.1	0.3	61.6
Simulation, STL	1.2	4.2	21.4	3 ms	19.6	2.2	2.3	0.3	51.2
Simulation, OBJ	1.1	4.5	20.9	2 ms	20.0	28.7	2.3	0.4	77.9
Visual, GLB	0.9	3.9	20.0	2 ms	45.7	0.5	4.8	0.3	76.1
Visual, OBJ	1.2	3.8	20.6	2 ms	46.4	16.3	5.3	0.3	93.9

Board Repo: iorodeo/led-display_g6_hardware_arena Board: arena_10_of_10_v1r1.kicad_pcb Folder arena_10-10 / arena_10-10_v1 / manual_route / v2 Complexity 387 / 1000 (size 242, features 145) KESE features through vias, blind and buried vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, curved board outline, tracks bare of mask, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 505, 1,744, 405 Triangles, simulation 5,657,426 in 516 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 186 MB 1.5 GB STEP 660 MB 2.0 GB STL 283 MB 1.6 GB OBJ 592 MB 3.6 GB Visual GLB 104 MB 2.0 GB OBJ 327 MB 2.1 GB

1287. arena_10_of_10_v1r1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.6	6.0	23.8	2 ms	24.5	1.1	3.6	0.4	61.0
Simulation, STEP	1.7	5.8	23.3	3 ms	24.6	15.8	3.2	0.4	74.8
Simulation, STL	1.8	5.8	23.1	3 ms	24.9	2.8	3.5	0.4	62.2
Simulation, OBJ	1.8	6.1	23.1	3 ms	25.3	41.0	3.6	0.4	101.3
Visual, GLB	1.9	5.9	22.9	2 ms	50.7	0.5	7.0	0.3	89.2
Visual, OBJ	1.7	5.8	23.3	2 ms	48.8	18.8	6.8	0.3	105.4

Board Repo: iorodeo/led-display_g6_hardware_arena Board: arena_10_of_10_v1r1.kicad_pcb Folder arena_10-10 / arena_10-10_v1 / manual_route / v2 / routed Complexity 363 / 1000 (size 253, features 110) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, tracks bare of mask, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 505, 4,129, 652 Triangles, simulation 7,323,260 in 516 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 244 MB 1.8 GB STEP 805 MB 2.5 GB STL 366 MB 1.9 GB OBJ 772 MB 4.6 GB Visual GLB 126 MB 2.2 GB OBJ 406 MB 2.8 GB

1288. arena_top_10-10

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	1.1	4.0	0.5 ms	2.6	0.1	0.5	0.2	9.2
Simulation, STEP	0.6	1.0	4.1	0.8 ms	2.6	2.6	0.5	0.3	11.6
Simulation, STL	0.6	0.9	3.9	0.5 ms	2.6	0.3	0.5	0.2	9.0
Simulation, OBJ	0.6	1.0	4.0	0.9 ms	2.6	4.8	0.5	0.2	13.7
Visual, GLB	0.6	1.0	4.0	0.5 ms	6.2	89 ms	0.7	0.2	12.8
Visual, OBJ	0.7	1.0	4.0	0.4 ms	6.2	3.1	0.7	0.2	15.8

Board Repo: iorodeo/led-display_g6_hardware_arena Board: arena_top_10-10.kicad_pcb Folder arena_10-10 / arena_top_10-10 Complexity 266 / 1000 (size 136, features 130) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 10 (20260206) Parts, tracks, vias 32, 54, 30 Triangles, simulation 857,574 in 96 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 29 MB 467 MB STEP 116 MB 483 MB STL 43 MB 453 MB OBJ 86 MB 617 MB Visual GLB 19 MB 476 MB OBJ 57 MB 489 MB

1289. arena_10-10_v2r1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.0	5.6	27.2	2 ms	33.6	1.4	3.1	0.4	73.3
Simulation, STEP	2.2	5.7	25.1	2 ms	35.3	18.4	3.2	0.4	90.2
Simulation, STL	2.2	5.3	25.8	1 ms	34.5	2.8	3.1	0.5	74.2
Simulation, OBJ	2.3	5.5	26.7	1 ms	35.1	35.5	2.7	0.4	108.1
Visual, GLB	2.1	5.3	24.4	2 ms	67.9	0.8	8.1	0.3	108.8
Visual, OBJ	2.1	5.7	25.9	1 ms	65.6	23.5	9.0	0.3	132.1

Board Repo: iorodeo/led-display_g6_hardware_arena Board: arena_10-10_v2r1.kicad_pcb Folder arena_10-10 / develop / with_reg / arena_10-10_v2r1 Complexity 403 / 1000 (size 263, features 140) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, tracks bare of mask, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 6 File format KiCad 10 (20260206) Parts, tracks, vias 521, 8,209, 732 Triangles, simulation 7,924,200 in 530 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 261 MB 2.2 GB STEP 1.1 GB 2.8 GB STL 396 MB 2.2 GB OBJ 829 MB 4.9 GB Visual GLB 174 MB 2.8 GB OBJ 559 MB 3.5 GB

1290. arena_10-10_v2r1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.1	6.0	24.6	1 ms	37.1	1.2	2.8	0.3	74.1
Simulation, STEP	2.0	5.5	23.7	1 ms	33.5	18.8	2.9	0.4	86.8
Simulation, STL	2.1	5.5	24.1	2 ms	34.0	2.5	2.9	0.3	71.3
Simulation, OBJ	1.9	5.4	23.5	2 ms	35.5	38.3	2.9	0.4	108.0
Visual, GLB	2.1	5.5	24.3	1 ms	62.1	0.7	9.6	0.3	104.6
Visual, OBJ	2.1	5.3	23.6	2 ms	61.6	22.8	9.9	0.3	125.7

Board Repo: iorodeo/led-display_g6_hardware_arena Board: arena_10-10_v2r1.kicad_pcb Folder arena_10-10 / develop / without_reg / arena_10-10_v2r1 Complexity 388 / 1000 (size 263, features 125) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 6 File format KiCad 10 (20260206) Parts, tracks, vias 543, 8,276, 744 Triangles, simulation 8,057,822 in 539 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 264 MB 2.2 GB STEP 1.1 GB 2.8 GB STL 403 MB 2.3 GB OBJ 840 MB 5.0 GB Visual GLB 176 MB 2.8 GB OBJ 566 MB 3.5 GB

1291. arena_12-18

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	3.3	9.0	41.2	2 ms	37.4	1.9	6.3	0.5	99.6
Simulation, STEP	3.2	9.0	41.5	3 ms	35.9	25.7	6.4	0.5	122.2
Simulation, STL	3.2	9.1	41.0	2 ms	37.9	3.6	6.6	0.5	101.9
Simulation, OBJ	3.2	9.3	42.7	2 ms	37.9	61.5	6.4	0.5	161.6
Visual, GLB	3.1	9.5	41.5	2 ms	114.8	0.7	7.0	0.4	176.9
Visual, OBJ	3.2	9.4	41.7	2 ms	119.0	28.7	7.7	0.4	210.1

Board Repo: iorodeo/led-display_g6_hardware_arena Board: arena_12-18.kicad_pcb Folder arena_12-18 Complexity 381 / 1000 (size 256, features 125) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 6 File format KiCad 10 (20260206) Parts, tracks, vias 604, 3,679, 855 Triangles, simulation 9,784,698 in 604 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 333 MB 2.3 GB STEP 1.3 GB 3.1 GB STL 489 MB 2.3 GB OBJ 1.1 GB 6.2 GB Visual GLB 161 MB 2.8 GB OBJ 516 MB 3.4 GB

1292. arena_12-18

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.9	2.6	11.1	2 ms	10.9	0.4	1.2	0.3	27.3
Simulation, STEP	0.9	2.3	11.2	1 ms	10.6	7.2	1.0	0.3	33.5
Simulation, STL	0.9	2.2	11.5	2 ms	11.5	0.8	1.0	0.2	28.1
Simulation, OBJ	1.0	2.4	11.8	2 ms	11.6	12.9	1.0	0.3	40.9
Visual, GLB	1.0	2.3	11.5	1 ms	26.1	0.3	2.9	0.3	44.4
Visual, OBJ	1.1	2.1	11.4	1 ms	25.3	9.1	3.2	0.3	52.5

Board Repo: iorodeo/led-display_g6_hardware_arena Board: arena_12-18.kicad_pcb Folder arena_12-18 / layout_tool Complexity 94 / 1000 (size 84, features 10) KESE features rounded, trapezoid or chamfered pads Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 495, 0, 0 Triangles, simulation 2,474,306 in 511 parts Note mostly unrouted Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 83 MB 952 MB STEP 344 MB 1.2 GB STL 124 MB 953 MB OBJ 264 MB 1.7 GB Visual GLB 67 MB 1.4 GB OBJ 208 MB 1.4 GB

1293. modified_arena_10_of_10_v1r1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.1	1.6	5.0	1 ms	2.8	0.2	0.4	0.2	11.2
Simulation, STEP	1.1	1.6	5.0	0.8 ms	3.3	3.4	0.4	0.2	14.9
Simulation, STL	1.0	1.6	5.0	0.8 ms	3.3	0.3	0.4	0.2	11.8
Simulation, OBJ	1.0	1.5	5.0	0.9 ms	2.9	5.3	0.4	0.3	16.5
Visual, GLB	1.0	1.6	4.9	0.8 ms	7.4	0.1	0.7	0.2	16.0
Visual, OBJ	1.1	1.5	4.9	0.7 ms	7.5	4.2	0.8	0.2	20.2

Board Repo: iorodeo/led-display_g6_hardware_arena Board: modified_arena_10_of_10_v1r1.kicad_pcb Folder arena_12-18 / layout_tool Complexity 104 / 1000 (size 84, features 20) KESE features rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 495, 0, 0 Triangles, simulation 990,208 in 253 parts Note mostly unrouted Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 34 MB 496 MB STEP 139 MB 550 MB STL 50 MB 489 MB OBJ 102 MB 712 MB Visual GLB 26 MB 737 MB OBJ 79 MB 671 MB

1294. arena_12-18

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.2	4.3	20.1	2 ms	19.9	0.9	2.1	0.3	48.9
Simulation, STEP	1.1	4.2	19.9	3 ms	19.1	13.4	2.0	0.3	60.0
Simulation, STL	1.2	4.1	20.6	2 ms	19.9	1.7	2.0	0.3	49.9
Simulation, OBJ	1.2	4.2	19.6	2 ms	19.5	31.0	2.1	0.3	77.9
Visual, GLB	1.1	4.2	19.7	2 ms	40.2	0.4	4.5	0.3	70.5
Visual, OBJ	1.1	4.2	19.8	2 ms	40.9	16.8	5.1	0.3	88.1

Board Repo: iorodeo/led-display_g6_hardware_arena Board: arena_12-18.kicad_pcb Folder arena_12-18 / manual_route / v1 Complexity 387 / 1000 (size 242, features 145) KESE features through vias, blind and buried vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, curved board outline, tracks bare of mask, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 505, 1,743, 403 Triangles, simulation 5,647,298 in 516 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 186 MB 1.5 GB STEP 659 MB 2.0 GB STL 282 MB 1.5 GB OBJ 591 MB 3.5 GB Visual GLB 103 MB 2.0 GB OBJ 327 MB 2.1 GB

1295. arena_12-18

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.1	6.8	28.2	2 ms	27.3	1.6	3.9	0.4	70.3
Simulation, STEP	2.2	7.1	28.7	2 ms	28.3	19.8	3.8	0.4	90.2
Simulation, STL	2.1	6.9	27.9	3 ms	28.0	3.0	4.0	0.4	72.3
Simulation, OBJ	2.1	6.7	27.2	2 ms	28.6	48.7	4.0	0.5	117.7
Visual, GLB	2.2	7.0	29.9	3 ms	55.7	0.6	6.4	0.4	102.2
Visual, OBJ	2.2	7.2	29.1	3 ms	54.5	24.1	5.7	0.3	123.3

Board Repo: iorodeo/led-display_g6_hardware_arena Board: arena_12-18.kicad_pcb Folder arena_12-18 / manual_route / v1 / routed Complexity 364 / 1000 (size 254, features 110) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, tracks bare of mask, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 505, 4,090, 677 Triangles, simulation 7,459,160 in 516 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 248 MB 1.9 GB STEP 815 MB 2.5 GB STL 373 MB 1.9 GB OBJ 787 MB 4.7 GB Visual GLB 128 MB 2.3 GB OBJ 413 MB 2.7 GB

1296. arena_12-18

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.2	4.4	20.5	2 ms	19.7	0.9	2.1	0.4	49.3
Simulation, STEP	1.1	4.5	20.2	2 ms	20.1	13.6	2.2	0.3	62.1
Simulation, STL	1.2	4.3	20.0	2 ms	20.9	2.2	2.2	0.3	51.1
Simulation, OBJ	1.2	4.4	20.3	2 ms	19.9	27.3	2.3	0.4	75.8
Visual, GLB	1.2	4.2	20.2	2 ms	42.2	0.5	5.4	0.3	74.1
Visual, OBJ	1.0	4.3	20.6	2 ms	42.6	14.9	4.8	0.3	88.4

Board Repo: iorodeo/led-display_g6_hardware_arena Board: arena_12-18.kicad_pcb Folder arena_12-18 / manual_route / v2 Complexity 387 / 1000 (size 242, features 145) KESE features through vias, blind and buried vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, curved board outline, tracks bare of mask, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 505, 1,744, 405 Triangles, simulation 5,657,426 in 516 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 186 MB 1.5 GB STEP 660 MB 2.0 GB STL 283 MB 1.5 GB OBJ 592 MB 3.5 GB Visual GLB 104 MB 1.9 GB OBJ 327 MB 2.1 GB

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