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Corpus Testing 02

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Corpus Page 2

Part 2 of 30 of Corpus Testing: boards 109 to 216, six runs each, one file format a run, as Corpus Testing describes.

109. situacion1

situacion1: stages 4 and 6 take 57% to 84% of a run. Simulation, GLB takes 17 s. Simulation, STEP takes 21 s. Simulation, STL takes 16 s. Simulation, OBJ takes 24 s. Visual, GLB takes 17 s. Visual, OBJ takes 21 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.3 1.4 7.4 0.7 ms 6.3 0.2 0.7 0.3 16.6
Simulation, STEP 0.3 1.4 7.7 0.5 ms 6.7 4.6 0.6 0.3 21.5
Simulation, STL 0.2 1.3 7.4 0.7 ms 6.1 0.5 0.6 0.2 16.3
Simulation, OBJ 0.2 1.4 7.3 0.5 ms 6.4 7.8 0.6 0.2 23.8
Visual, GLB 0.3 1.3 7.4 0.6 ms 6.9 98 ms 0.9 0.2 17.1
Visual, OBJ 0.2 1.4 7.3 0.5 ms 6.9 3.6 1.1 0.2 20.7
Board Repo: alvaroalea/plusD-clone
Board: situacion1.kicad_pcb
Complexity 58 / 1000 (size 58, features 0)
Tested 9th November 2026
Copper layers 2
File format KiCad 5 (20171130)
Parts, tracks, vias 45, 0, 0
Triangles, simulation 1,586,200 in 95 parts
Note mostly unrouted
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 50 MB 550 MB
STEP 231 MB 711 MB
STL 79 MB 526 MB
OBJ 162 MB 1.0 GB
Visual
GLB 24 MB 661 MB
OBJ 71 MB 607 MB

110. SMD500

SMD500: stages 4 and 6 take 57% to 88% of a run. Simulation, GLB takes 4 min. Simulation, STEP takes 5 min. Simulation, STL takes 4 min. Simulation, OBJ takes 5 min. Visual, GLB takes 6 min. Visual, OBJ takes 7 min

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 3.1 22.3 123.4 3 ms 72.6 3.4 12.2 0.7 237.8
Simulation, STEP 3.5 22.7 121.8 2 ms 73.5 52.0 12.2 0.6 286.2
Simulation, STL 3.2 22.8 122.6 2 ms 68.0 6.6 11.3 0.6 235.1
Simulation, OBJ 3.2 22.0 117.1 2 ms 66.3 101.8 11.8 0.6 322.7
Visual, GLB 3.6 23.3 118.4 3 ms 210.5 2.1 17.5 0.5 375.8
Visual, OBJ 3.2 23.3 122.8 2 ms 194.4 66.0 15.9 0.4 426.0
Board Repo: amigalisa/Amiga-SMD-500
Board: SMD500.kicad_pcb
Complexity 342 / 1000 (size 297, features 45)
KESE features through vias, rounded,
trapezoid or chamfered pads,
filled zones
Tested 9th November 2026
Copper layers 2
File format KiCad 5 (20171130)
Parts, tracks, vias 582, 18,007, 1,862
Triangles, simulation 14,372,138 in 534 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 498 MB 3.7 GB
STEP 2.7 GB 5.2 GB
STL 719 MB 3.9 GB
OBJ 1.6 GB 9.3 GB
Visual
GLB 354 MB 5.3 GB
OBJ 1.1 GB 7.0 GB

111. AmigaPCI 68040

AmigaPCI 68040: stages 4 and 6 take 48% to 82% of a run. Simulation, GLB takes 64 s. Simulation, STEP takes 78 s. Simulation, STL takes 63 s. Simulation, OBJ takes 95 s. Visual, GLB takes 93 s. Visual, OBJ takes 2 min

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 1.9 6.7 22.1 1 ms 26.7 1.3 4.4 0.4 63.6
Simulation, STEP 1.9 6.9 21.9 1 ms 26.4 16.6 4.3 0.4 78.4
Simulation, STL 1.9 6.6 20.4 2 ms 25.6 3.1 4.5 0.4 62.5
Simulation, OBJ 1.7 6.7 20.3 1 ms 25.6 36.1 4.4 0.4 95.3
Visual, GLB 1.9 6.3 21.3 1 ms 55.5 0.6 7.5 0.3 93.4
Visual, OBJ 1.8 6.4 21.4 2 ms 55.5 17.8 6.8 0.3 110.1
Board Repo: AmigaPCI/AmigaPCI-LBC040
Board: AmigaPCI 68040.kicad_pcb
Folder KiCAD / AmigaPCI-LBC040-REV60
Complexity 370 / 1000 (size 285, features 85)
KESE features through vias, rounded,
trapezoid or chamfered pads,
filled zones, curved board outline,
stack-up, dielectric εr and tanδ
Tested 9th November 2026
Copper layers 6
File format KiCad 8 (20240108)
Parts, tracks, vias 126, 4,520, 563
Triangles, simulation 7,796,750 in 379 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 263 MB 1.8 GB
STEP 981 MB 2.5 GB
STL 390 MB 1.8 GB
OBJ 835 MB 4.9 GB
Visual
GLB 133 MB 2.4 GB
OBJ 436 MB 2.9 GB

112. AmigaPCI Mainboard

AmigaPCI Mainboard: stages 4 and 6 take 66% to 87% of a run. Simulation, GLB takes 9 min. Simulation, STEP takes 12 min. Simulation, STL takes 10 min. Visual, GLB takes 16 min. Visual, OBJ takes 12 min

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 13.6 50.4 250.1 5 ms 201.3 9.7 37.5 1.7 564.2
Simulation, STEP 14.6 52.2 249.7 5 ms 213.3 127.4 40.4 1.8 699.5
Simulation, STL 13.7 49.8 249.5 8 ms 210.7 21.3 41.2 1.5 587.6
Simulation, OBJ exceeded 11 GB on a 16 GB machine (stopped there, not a KESE failure); it will be run again on a machine with more memory
Visual, GLB 14.1 50.4 252.8 6 ms 561.1 4.7 46.5 1.5 931.2
Visual, OBJ 10.3 38.1 182.7 5 ms 396.4 83.0 27.4 0.9 738.8
Board Repo: AmigaPCI/AmigaPCI-MainBoard
Board: AmigaPCI Mainboard.kicad_pcb
Folder KiCAD / AmigaPCI Mainboard-KiCAD REV 70
Complexity 493 / 1000 (size 343, features 150)
KESE features through vias, slotted holes,
custom pads, rounded,
trapezoid or chamfered pads,
arc tracks, filled zones,
copper drawings, copper text,
stack-up, dielectric εr and tanδ,
copper finish
Tested 9th November 2026 to 10th November 2026
Copper layers 6
File format KiCad 8 (20240108)
Parts, tracks, vias 723, 20,477, 2,447
Triangles, simulation 36,016,370 in 1274 parts
Verifier Simulation, OBJ: exceeded 11 GB on a 16 GB machine (stopped there, not a KESE failure); it will be run again on a machine with more memory
Run again Visual, OBJ: failed in the corpus run, run again with the memory cap raised from 11 GB to 14.5 GB, and passed
File
type
File
size
Peak memory
used
Simulation
GLB 1.2 GB 7.2 GB
STEP 5.6 GB 9.7 GB
STL 1.8 GB 8.0 GB
OBJ – 11 GB
Visual
GLB 644 MB 10 GB
OBJ 2.2 GB 14 GB

113. anavi-light-controller

anavi-light-controller: stages 4 and 6 take 52% to 82% of a run. Simulation, GLB takes 3.6 s. Simulation, STEP takes 5.1 s. Simulation, STL takes 3.8 s. Simulation, OBJ takes 5.4 s. Visual, GLB takes 5.5 s. Visual, OBJ takes 6.9 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.3 1.7 0.2 ms 1.1 55 ms 0.2 0.2 3.6
Simulation, STEP 0.2 0.3 1.7 0.2 ms 1.2 1.3 0.2 0.2 5.1
Simulation, STL 0.2 0.3 1.8 0.2 ms 1.1 74 ms 0.2 0.2 3.8
Simulation, OBJ 0.1 0.3 1.8 0.2 ms 1.1 1.7 0.2 0.2 5.4
Visual, GLB 0.1 0.3 1.7 0.2 ms 2.8 40 ms 0.3 0.2 5.5
Visual, OBJ 0.1 0.3 1.8 0.5 ms 2.7 1.5 0.3 0.2 6.9
Board Repo: AnaviTechnology/anavi-light-controller
Board: anavi-light-controller.kicad_pcb
Complexity 203 / 1000 (size 138, features 65)
KESE features through vias, slotted holes,
drill offsets, filled zones,
curved board outline
Tested 9th November 2026
Copper layers 2
File format KiCad 4 (4)
Parts, tracks, vias 22, 164, 12
Triangles, simulation 355,398 in 30 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 13 MB 267 MB
STEP 67 MB 292 MB
STL 18 MB 267 MB
OBJ 36 MB 270 MB
Visual
GLB 8.9 MB 265 MB
OBJ 26 MB 265 MB

114. Board 2x06 W15.24

Board 2x06 W15.24: stages 4 and 6 take 40% to 67% of a run. Simulation, GLB takes 1.3 s. Simulation, STEP takes 1.9 s. Simulation, STL takes 1.1 s. Simulation, OBJ takes 1.5 s. Visual, GLB takes 1.2 s. Visual, OBJ takes 1.6 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 82 ms 83 ms 0.3 0.1 ms 0.5 12 ms 39 ms 0.2 1.3
Simulation, STEP 70 ms 65 ms 0.3 0.2 ms 0.5 0.8 39 ms 0.2 1.9
Simulation, STL 71 ms 70 ms 0.3 0.1 ms 0.5 16 ms 49 ms 0.2 1.1
Simulation, OBJ 70 ms 62 ms 0.3 0.2 ms 0.6 0.3 43 ms 0.2 1.5
Visual, GLB 68 ms 63 ms 0.3 0.1 ms 0.6 7 ms 48 ms 0.2 1.2
Visual, OBJ 0.1 71 ms 0.3 0.2 ms 0.6 0.2 51 ms 0.2 1.6
Board Repo: andrewpaterson/658-Computer
Board: Board 2x06 W15.24.kicad_pcb
Folder Kicad / Boards / Blank / Board 2x06 W15.24
Complexity 89 / 1000 (size 34, features 55)
KESE features rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 4, 0, 0
Triangles, simulation 62,080 in 24 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 2.1 MB 70 MB
STEP 6.9 MB 171 MB
STL 3.1 MB 72 MB
OBJ 6.0 MB 83 MB
Visual
GLB 1.3 MB 106 MB
OBJ 3.7 MB 107 MB

115. Board 2x06 W22.86

Board 2x06 W22.86: stages 4 and 6 take 40% to 65% of a run. Simulation, GLB takes 1.3 s. Simulation, STEP takes 2.3 s. Simulation, STL takes 1.5 s. Simulation, OBJ takes 2.0 s. Visual, GLB takes 1.6 s. Visual, OBJ takes 1.9 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 88 ms 0.3 0.1 ms 0.5 12 ms 41 ms 0.3 1.3
Simulation, STEP 0.1 88 ms 0.3 0.1 ms 0.6 0.9 60 ms 0.2 2.3
Simulation, STL 0.1 97 ms 0.3 0.1 ms 0.7 22 ms 60 ms 0.2 1.5
Simulation, OBJ 78 ms 76 ms 0.3 0.2 ms 0.7 0.6 45 ms 0.2 2.0
Visual, GLB 0.1 90 ms 0.3 0.4 ms 0.7 8 ms 61 ms 0.3 1.6
Visual, OBJ 0.1 92 ms 0.3 0.2 ms 0.7 0.3 58 ms 0.2 1.9
Board Repo: andrewpaterson/658-Computer
Board: Board 2x06 W22.86.kicad_pcb
Folder Kicad / Boards / Blank / Board 2x06 W22.86
Complexity 89 / 1000 (size 34, features 55)
KESE features rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 4, 0, 0
Triangles, simulation 61,696 in 24 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 2.0 MB 70 MB
STEP 6.6 MB 171 MB
STL 3.1 MB 71 MB
OBJ 5.9 MB 94 MB
Visual
GLB 1.3 MB 105 MB
OBJ 3.7 MB 104 MB

116. Board 2x12 W15.24

Board 2x12 W15.24: stages 4 and 6 take 44% to 76% of a run. Simulation, GLB takes 1.8 s. Simulation, STEP takes 2.6 s. Simulation, STL takes 1.7 s. Simulation, OBJ takes 2.5 s. Visual, GLB takes 2.5 s. Visual, OBJ takes 2.9 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.1 0.6 0.2 ms 0.7 26 ms 93 ms 0.2 1.8
Simulation, STEP 0.1 0.1 0.5 0.2 ms 0.6 0.9 89 ms 0.3 2.6
Simulation, STL 88 ms 0.1 0.6 0.2 ms 0.6 34 ms 78 ms 0.3 1.7
Simulation, OBJ 86 ms 0.1 0.6 0.3 ms 0.6 0.7 90 ms 0.3 2.5
Visual, GLB 93 ms 0.1 0.5 0.2 ms 1.4 12 ms 83 ms 0.3 2.5
Visual, OBJ 0.1 0.2 0.6 0.2 ms 1.4 0.4 74 ms 0.2 2.9
Board Repo: andrewpaterson/658-Computer
Board: Board 2x12 W15.24.kicad_pcb
Folder Kicad / Boards / Blank / Board 2x12 W15.24
Complexity 89 / 1000 (size 34, features 55)
KESE features rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 4, 0, 0
Triangles, simulation 110,320 in 32 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 3.7 MB 178 MB
STEP 12 MB 188 MB
STL 5.5 MB 182 MB
OBJ 11 MB 175 MB
Visual
GLB 2.2 MB 153 MB
OBJ 6.2 MB 153 MB

117. Board 2x12 W22.86

Board 2x12 W22.86: stages 4 and 6 take 46% to 77% of a run. Simulation, GLB takes 1.9 s. Simulation, STEP takes 2.7 s. Simulation, STL takes 1.7 s. Simulation, OBJ takes 2.4 s. Visual, GLB takes 2.4 s. Visual, OBJ takes 2.7 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 86 ms 0.1 0.6 0.2 ms 0.8 24 ms 98 ms 0.2 1.9
Simulation, STEP 94 ms 0.1 0.5 0.2 ms 0.7 0.9 71 ms 0.3 2.7
Simulation, STL 90 ms 0.1 0.5 0.2 ms 0.7 38 ms 75 ms 0.2 1.7
Simulation, OBJ 84 ms 0.1 0.5 0.2 ms 0.7 0.7 78 ms 0.3 2.4
Visual, GLB 87 ms 0.1 0.6 0.2 ms 1.2 15 ms 81 ms 0.3 2.4
Visual, OBJ 89 ms 0.1 0.5 0.2 ms 1.3 0.3 71 ms 0.3 2.7
Board Repo: andrewpaterson/658-Computer
Board: Board 2x12 W22.86.kicad_pcb
Folder Kicad / Boards / Blank / Board 2x12 W22.86
Complexity 89 / 1000 (size 34, features 55)
KESE features rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 4, 0, 0
Triangles, simulation 109,716 in 32 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 3.6 MB 178 MB
STEP 12 MB 186 MB
STL 5.5 MB 175 MB
OBJ 11 MB 178 MB
Visual
GLB 2.2 MB 153 MB
OBJ 6.1 MB 153 MB

118. Board 2x16 W15.24

Board 2x16 W15.24: stages 4 and 6 take 50% to 79% of a run. Simulation, GLB takes 2.1 s. Simulation, STEP takes 2.9 s. Simulation, STL takes 2.1 s. Simulation, OBJ takes 2.6 s. Visual, GLB takes 2.7 s. Visual, OBJ takes 3.4 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 86 ms 0.2 0.7 0.2 ms 0.8 36 ms 94 ms 0.2 2.1
Simulation, STEP 83 ms 0.1 0.7 0.2 ms 0.8 0.9 98 ms 0.2 2.9
Simulation, STL 0.1 0.2 0.6 0.2 ms 0.8 37 ms 84 ms 0.3 2.1
Simulation, OBJ 84 ms 0.1 0.7 0.2 ms 0.7 0.7 98 ms 0.2 2.6
Visual, GLB 92 ms 0.1 0.7 0.2 ms 1.5 18 ms 0.1 0.2 2.7
Visual, OBJ 0.1 0.1 0.8 0.2 ms 1.5 0.5 75 ms 0.2 3.4
Board Repo: andrewpaterson/658-Computer
Board: Board 2x16 W15.24.kicad_pcb
Folder Kicad / Boards / Blank / Board 2x16 W15.24
Complexity 89 / 1000 (size 34, features 55)
KESE features rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 4, 0, 0
Triangles, simulation 143,440 in 40 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 4.7 MB 184 MB
STEP 15 MB 197 MB
STL 7.2 MB 185 MB
OBJ 14 MB 181 MB
Visual
GLB 2.8 MB 155 MB
OBJ 7.8 MB 157 MB

119. Board 2x16 W22.86

Board 2x16 W22.86: stages 4 and 6 take 48% to 79% of a run. Simulation, GLB takes 1.9 s. Simulation, STEP takes 2.8 s. Simulation, STL takes 1.9 s. Simulation, OBJ takes 2.7 s. Visual, GLB takes 2.5 s. Visual, OBJ takes 2.9 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 84 ms 0.1 0.6 0.2 ms 0.8 26 ms 80 ms 0.2 1.9
Simulation, STEP 85 ms 0.1 0.6 0.2 ms 0.7 0.9 95 ms 0.2 2.8
Simulation, STL 84 ms 0.1 0.6 0.2 ms 0.8 36 ms 91 ms 0.2 1.9
Simulation, OBJ 0.1 0.1 0.6 0.2 ms 0.7 0.8 90 ms 0.3 2.7
Visual, GLB 87 ms 0.1 0.6 0.3 ms 1.3 13 ms 83 ms 0.2 2.5
Visual, OBJ 83 ms 0.1 0.6 0.2 ms 1.3 0.5 94 ms 0.2 2.9
Board Repo: andrewpaterson/658-Computer
Board: Board 2x16 W22.86.kicad_pcb
Folder Kicad / Boards / Blank / Board 2x16 W22.86
Complexity 89 / 1000 (size 34, features 55)
KESE features rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 4, 0, 0
Triangles, simulation 142,752 in 40 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 4.6 MB 184 MB
STEP 15 MB 201 MB
STL 7.1 MB 183 MB
OBJ 14 MB 183 MB
Visual
GLB 2.8 MB 157 MB
OBJ 7.8 MB 154 MB

120. Board 2x20 W15.24

Board 2x20 W15.24: stages 4 and 6 take 50% to 81% of a run. Simulation, GLB takes 2.7 s. Simulation, STEP takes 3.7 s. Simulation, STL takes 2.4 s. Simulation, OBJ takes 3.5 s. Visual, GLB takes 3.5 s. Visual, OBJ takes 3.9 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.2 1.0 0.5 ms 0.9 42 ms 0.2 0.3 2.7
Simulation, STEP 97 ms 0.2 1.0 0.2 ms 0.9 1.1 0.1 0.2 3.7
Simulation, STL 93 ms 0.2 0.9 0.2 ms 0.8 54 ms 0.1 0.2 2.4
Simulation, OBJ 0.1 0.2 0.9 0.3 ms 0.9 1.1 0.1 0.2 3.5
Visual, GLB 97 ms 0.2 1.0 0.2 ms 1.8 29 ms 0.1 0.3 3.5
Visual, OBJ 94 ms 0.2 0.9 0.3 ms 1.7 0.6 0.1 0.3 3.9
Board Repo: andrewpaterson/658-Computer
Board: Board 2x20 W15.24.kicad_pcb
Folder Kicad / Boards / Blank / Board 2x20 W15.24
Complexity 89 / 1000 (size 34, features 55)
KESE features rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 4, 0, 0
Triangles, simulation 176,560 in 48 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 5.8 MB 192 MB
STEP 18 MB 213 MB
STL 8.8 MB 194 MB
OBJ 17 MB 194 MB
Visual
GLB 3.4 MB 171 MB
OBJ 9.5 MB 172 MB

121. Board 2x20 W22.86

Board 2x20 W22.86: stages 4 and 6 take 51% to 78% of a run. Simulation, GLB takes 1.9 s. Simulation, STEP takes 2.7 s. Simulation, STL takes 2.0 s. Simulation, OBJ takes 2.6 s. Visual, GLB takes 2.4 s. Visual, OBJ takes 2.8 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 81 ms 0.1 0.7 0.2 ms 0.7 28 ms 86 ms 0.2 1.9
Simulation, STEP 81 ms 0.1 0.7 0.2 ms 0.7 0.9 80 ms 0.2 2.7
Simulation, STL 73 ms 0.1 0.6 0.2 ms 0.8 44 ms 0.1 0.2 2.0
Simulation, OBJ 73 ms 0.1 0.6 0.2 ms 0.8 0.7 84 ms 0.2 2.6
Visual, GLB 78 ms 0.1 0.6 0.2 ms 1.3 15 ms 0.1 0.2 2.4
Visual, OBJ 75 ms 0.1 0.6 0.2 ms 1.3 0.4 94 ms 0.2 2.8
Board Repo: andrewpaterson/658-Computer
Board: Board 2x20 W22.86.kicad_pcb
Folder Kicad / Boards / Blank / Board 2x20 W22.86
Complexity 89 / 1000 (size 34, features 55)
KESE features rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 4, 0, 0
Triangles, simulation 175,844 in 48 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 5.7 MB 190 MB
STEP 18 MB 213 MB
STL 8.8 MB 194 MB
OBJ 17 MB 194 MB
Visual
GLB 3.3 MB 162 MB
OBJ 9.4 MB 171 MB

122. Board 2x22 W15.24

Board 2x22 W15.24: stages 4 and 6 take 49% to 80% of a run. Simulation, GLB takes 2.2 s. Simulation, STEP takes 3.2 s. Simulation, STL takes 2.1 s. Simulation, OBJ takes 2.8 s. Visual, GLB takes 3.1 s. Visual, OBJ takes 3.6 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 83 ms 0.1 0.8 0.2 ms 0.8 37 ms 95 ms 0.2 2.2
Simulation, STEP 88 ms 0.1 0.8 0.3 ms 0.8 1.0 0.1 0.2 3.2
Simulation, STL 84 ms 0.2 0.7 0.2 ms 0.7 54 ms 0.1 0.2 2.1
Simulation, OBJ 85 ms 0.2 0.7 0.2 ms 0.7 0.9 0.1 0.2 2.8
Visual, GLB 87 ms 0.2 0.8 0.2 ms 1.7 15 ms 0.1 0.2 3.1
Visual, OBJ 86 ms 0.2 0.8 0.2 ms 1.7 0.5 0.1 0.3 3.6
Board Repo: andrewpaterson/658-Computer
Board: Board 2x22 W15.24.kicad_pcb
Folder Kicad / Boards / Blank / Board 2x22 W15.24
Complexity 89 / 1000 (size 34, features 55)
KESE features rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 4, 0, 0
Triangles, simulation 193,120 in 52 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 6.3 MB 198 MB
STEP 20 MB 219 MB
STL 9.7 MB 198 MB
OBJ 19 MB 198 MB
Visual
GLB 3.6 MB 181 MB
OBJ 10 MB 177 MB

123. Board 2x24 W15.24

Board 2x24 W15.24: stages 4 and 6 take 50% to 80% of a run. Simulation, GLB takes 2.4 s. Simulation, STEP takes 3.4 s. Simulation, STL takes 2.5 s. Simulation, OBJ takes 3.4 s. Visual, GLB takes 3.4 s. Visual, OBJ takes 3.8 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 84 ms 0.2 0.9 0.2 ms 0.8 46 ms 0.1 0.2 2.4
Simulation, STEP 93 ms 0.2 0.9 0.2 ms 0.8 1.1 0.1 0.2 3.4
Simulation, STL 87 ms 0.2 1.0 0.2 ms 0.8 54 ms 0.1 0.2 2.5
Simulation, OBJ 82 ms 0.2 0.9 0.2 ms 0.8 1.1 0.1 0.2 3.4
Visual, GLB 91 ms 0.2 1.0 0.2 ms 1.8 20 ms 0.1 0.2 3.4
Visual, OBJ 91 ms 0.2 0.9 0.2 ms 1.8 0.6 0.1 0.2 3.8
Board Repo: andrewpaterson/658-Computer
Board: Board 2x24 W15.24.kicad_pcb
Folder Kicad / Boards / Blank / Board 2x24 W15.24
Complexity 89 / 1000 (size 34, features 55)
KESE features rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 4, 0, 0
Triangles, simulation 209,680 in 56 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 6.9 MB 203 MB
STEP 22 MB 224 MB
STL 10 MB 200 MB
OBJ 21 MB 202 MB
Visual
GLB 3.9 MB 190 MB
OBJ 11 MB 190 MB

124. Board 2x24 W22.86

Board 2x24 W22.86: stages 4 and 6 take 50% to 81% of a run. Simulation, GLB takes 2.7 s. Simulation, STEP takes 3.3 s. Simulation, STL takes 2.5 s. Simulation, OBJ takes 3.2 s. Visual, GLB takes 3.2 s. Visual, OBJ takes 3.7 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.2 1.0 0.2 ms 0.9 48 ms 0.1 0.3 2.7
Simulation, STEP 83 ms 0.2 0.9 0.2 ms 0.8 1.0 0.1 0.2 3.3
Simulation, STL 93 ms 0.3 0.9 0.2 ms 0.8 51 ms 0.1 0.2 2.5
Simulation, OBJ 78 ms 0.2 0.7 0.2 ms 1.0 0.9 0.1 0.2 3.2
Visual, GLB 84 ms 0.2 0.8 0.4 ms 1.8 19 ms 0.1 0.2 3.2
Visual, OBJ 69 ms 0.2 0.8 0.2 ms 1.8 0.5 0.1 0.2 3.7
Board Repo: andrewpaterson/658-Computer
Board: Board 2x24 W22.86.kicad_pcb
Folder Kicad / Boards / Blank / Board 2x24 W22.86
Complexity 89 / 1000 (size 34, features 55)
KESE features rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 4, 0, 0
Triangles, simulation 209,084 in 56 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 6.7 MB 203 MB
STEP 21 MB 223 MB
STL 10 MB 201 MB
OBJ 21 MB 202 MB
Visual
GLB 3.9 MB 189 MB
OBJ 11 MB 191 MB

125. Board 2x28 W15.24

Board 2x28 W15.24: stages 4 and 6 take 53% to 83% of a run. Simulation, GLB takes 2.8 s. Simulation, STEP takes 3.9 s. Simulation, STL takes 2.8 s. Simulation, OBJ takes 4.1 s. Visual, GLB takes 3.9 s. Visual, OBJ takes 4.5 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 98 ms 0.2 1.2 0.2 ms 0.9 47 ms 0.1 0.2 2.8
Simulation, STEP 93 ms 0.2 1.2 0.3 ms 0.9 1.1 0.2 0.2 3.9
Simulation, STL 89 ms 0.2 1.2 0.3 ms 0.9 69 ms 0.1 0.2 2.8
Simulation, OBJ 91 ms 0.2 1.2 0.2 ms 1.0 1.3 0.1 0.2 4.1
Visual, GLB 97 ms 0.2 1.1 0.2 ms 2.1 22 ms 0.1 0.2 3.9
Visual, OBJ 90 ms 0.2 1.1 0.2 ms 2.0 0.7 0.1 0.2 4.5
Board Repo: andrewpaterson/658-Computer
Board: Board 2x28 W15.24.kicad_pcb
Folder Kicad / Boards / Blank / Board 2x28 W15.24
Complexity 89 / 1000 (size 34, features 55)
KESE features rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 4, 0, 0
Triangles, simulation 242,800 in 64 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 7.9 MB 212 MB
STEP 25 MB 237 MB
STL 12 MB 212 MB
OBJ 24 MB 212 MB
Visual
GLB 4.5 MB 214 MB
OBJ 13 MB 211 MB

126. Board 2x28 W22.86

Board 2x28 W22.86: stages 4 and 6 take 51% to 82% of a run. Simulation, GLB takes 2.8 s. Simulation, STEP takes 3.9 s. Simulation, STL takes 2.9 s. Simulation, OBJ takes 4.3 s. Visual, GLB takes 3.6 s. Visual, OBJ takes 4.5 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 94 ms 0.3 1.1 0.5 ms 1.0 39 ms 0.1 0.2 2.8
Simulation, STEP 0.1 0.2 1.1 0.2 ms 1.0 1.1 0.1 0.2 3.9
Simulation, STL 0.1 0.2 1.1 0.3 ms 1.1 61 ms 0.1 0.2 2.9
Simulation, OBJ 0.1 0.2 1.1 0.3 ms 1.1 1.4 0.2 0.2 4.3
Visual, GLB 94 ms 0.2 1.0 0.3 ms 2.0 18 ms 0.1 0.2 3.6
Visual, OBJ 0.1 0.2 1.1 0.2 ms 2.0 0.7 0.1 0.2 4.5
Board Repo: andrewpaterson/658-Computer
Board: Board 2x28 W22.86.kicad_pcb
Folder Kicad / Boards / Blank / Board 2x28 W22.86
Complexity 89 / 1000 (size 34, features 55)
KESE features rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 4, 0, 0
Triangles, simulation 242,128 in 64 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 7.7 MB 211 MB
STEP 25 MB 236 MB
STL 12 MB 211 MB
OBJ 24 MB 217 MB
Visual
GLB 4.5 MB 211 MB
OBJ 13 MB 210 MB

127. Board 2x32 W15.24

Board 2x32 W15.24: stages 4 and 6 take 52% to 84% of a run. Simulation, GLB takes 3.6 s. Simulation, STEP takes 4.7 s. Simulation, STL takes 3.7 s. Simulation, OBJ takes 5.0 s. Visual, GLB takes 4.8 s. Visual, OBJ takes 5.6 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.3 1.4 0.3 ms 1.4 65 ms 0.2 0.3 3.6
Simulation, STEP 0.1 0.3 1.3 0.3 ms 1.3 1.3 0.2 0.2 4.7
Simulation, STL 0.1 0.2 1.4 0.3 ms 1.4 75 ms 0.2 0.2 3.7
Simulation, OBJ 94 ms 0.2 1.3 0.6 ms 1.3 1.6 0.2 0.2 5.0
Visual, GLB 0.1 0.3 1.5 0.2 ms 2.6 26 ms 0.2 0.2 4.8
Visual, OBJ 0.1 0.3 1.4 0.2 ms 2.5 0.9 0.2 0.3 5.6
Board Repo: andrewpaterson/658-Computer
Board: Board 2x32 W15.24.kicad_pcb
Folder Kicad / Boards / Blank / Board 2x32 W15.24
Complexity 89 / 1000 (size 34, features 55)
KESE features rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 4, 0, 0
Triangles, simulation 275,432 in 72 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 8.6 MB 221 MB
STEP 28 MB 248 MB
STL 14 MB 220 MB
OBJ 27 MB 241 MB
Visual
GLB 5.1 MB 229 MB
OBJ 15 MB 233 MB

128. Board 2x32 W22.86

Board 2x32 W22.86: stages 4 and 6 take 56% to 81% of a run. Simulation, GLB takes 3.2 s. Simulation, STEP takes 4.4 s. Simulation, STL takes 3.3 s. Simulation, OBJ takes 4.4 s. Visual, GLB takes 4.1 s. Visual, OBJ takes 5.2 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.2 1.2 0.3 ms 1.3 52 ms 0.2 0.2 3.2
Simulation, STEP 88 ms 0.2 1.2 0.3 ms 1.3 1.2 0.2 0.3 4.4
Simulation, STL 97 ms 0.2 1.2 0.3 ms 1.3 86 ms 0.2 0.2 3.3
Simulation, OBJ 91 ms 0.2 1.2 0.3 ms 1.2 1.3 0.2 0.2 4.4
Visual, GLB 98 ms 0.2 1.2 0.5 ms 2.2 25 ms 0.2 0.2 4.1
Visual, OBJ 96 ms 0.3 1.4 0.3 ms 2.4 0.7 0.2 0.2 5.2
Board Repo: andrewpaterson/658-Computer
Board: Board 2x32 W22.86.kicad_pcb
Folder Kicad / Boards / Blank / Board 2x32 W22.86
Complexity 89 / 1000 (size 34, features 55)
KESE features rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 4, 0, 0
Triangles, simulation 275,332 in 72 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 8.8 MB 217 MB
STEP 28 MB 248 MB
STL 14 MB 217 MB
OBJ 27 MB 236 MB
Visual
GLB 5.1 MB 225 MB
OBJ 15 MB 222 MB

129. Board 2x36 W22.86

Board 2x36 W22.86: stages 4 and 6 take 55% to 81% of a run. Simulation, GLB takes 4.0 s. Simulation, STEP takes 5.5 s. Simulation, STL takes 3.9 s. Simulation, OBJ takes 5.6 s. Visual, GLB takes 4.8 s. Visual, OBJ takes 5.6 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.3 1.6 0.4 ms 1.6 65 ms 0.2 0.2 4.0
Simulation, STEP 99 ms 0.3 1.6 0.5 ms 1.5 1.6 0.2 0.2 5.5
Simulation, STL 0.1 0.3 1.6 0.3 ms 1.5 0.1 0.2 0.2 3.9
Simulation, OBJ 99 ms 0.3 1.6 0.3 ms 1.5 1.6 0.2 0.3 5.6
Visual, GLB 0.1 0.3 1.5 0.5 ms 2.4 28 ms 0.2 0.3 4.8
Visual, OBJ 0.1 0.3 1.6 0.6 ms 2.4 0.9 0.2 0.2 5.6
Board Repo: andrewpaterson/658-Computer
Board: Board 2x36 W22.86.kicad_pcb
Folder Kicad / Boards / Blank / Board 2x36 W22.86
Complexity 89 / 1000 (size 34, features 55)
KESE features rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 4, 0, 0
Triangles, simulation 308,308 in 80 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 9.8 MB 228 MB
STEP 31 MB 260 MB
STL 15 MB 228 MB
OBJ 31 MB 235 MB
Visual
GLB 5.7 MB 243 MB
OBJ 16 MB 247 MB

130. Board 2x06 W15.24

Board 2x06 W15.24: reading, start-up and exit take 77% to 89% of a run. Simulation, GLB takes 0.3 s. Simulation, STEP takes 0.3 s. Simulation, STL takes 0.2 s. Simulation, OBJ takes 0.2 s. Visual, GLB takes 0.3 s. Visual, OBJ takes 0.3 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 2 ms 12 ms 6 ms 0.0 ms 8 ms 0.9 ms 3 ms 0.2 0.3
Simulation, STEP 3 ms 18 ms 4 ms 0.1 ms 12 ms 9 ms 2 ms 0.2 0.3
Simulation, STL 2 ms 13 ms 6 ms 0.0 ms 9 ms 0.9 ms 2 ms 0.2 0.2
Simulation, OBJ 2 ms 12 ms 8 ms 0.1 ms 13 ms 2 ms 2 ms 0.2 0.2
Visual, GLB 2 ms 11 ms 14 ms 0.0 ms 28 ms 1 ms 8 ms 0.2 0.3
Visual, OBJ 2 ms 10 ms 14 ms 0.0 ms 26 ms 1 ms 9 ms 0.2 0.3
Board Repo: andrewpaterson/658-Computer
Board: Board 2x06 W15.24.kicad_pcb
Folder Kicad / Boards / Pins / Board 2x06 W15.24
Complexity 47 / 1000 (size 17, features 30)
KESE features stack-up, dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 0, 0, 0
Triangles, simulation 72 in 3 parts
Note no components
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 6.3 kB 37 MB
STEP 30 kB 37 MB
STL 3.9 kB 35 MB
OBJ 10 kB 37 MB
Visual
GLB 7.7 kB 41 MB
OBJ 10 kB 41 MB

131. Board 2x06 W22.86

Board 2x06 W22.86: reading, start-up and exit take 76% to 88% of a run. Simulation, GLB takes 0.3 s. Simulation, STEP takes 0.3 s. Simulation, STL takes 0.3 s. Simulation, OBJ takes 0.3 s. Visual, GLB takes 0.3 s. Visual, OBJ takes 0.3 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 3 ms 14 ms 6 ms 0.0 ms 9 ms 1 ms 2 ms 0.2 0.3
Simulation, STEP 3 ms 17 ms 4 ms 0.0 ms 14 ms 14 ms 3 ms 0.2 0.3
Simulation, STL 3 ms 15 ms 4 ms 0.1 ms 13 ms 1 ms 2 ms 0.2 0.3
Simulation, OBJ 3 ms 17 ms 4 ms 0.1 ms 11 ms 2 ms 2 ms 0.2 0.3
Visual, GLB 4 ms 23 ms 8 ms 0.1 ms 29 ms 2 ms 15 ms 0.2 0.3
Visual, OBJ 2 ms 13 ms 2 ms 0.0 ms 23 ms 2 ms 10 ms 0.2 0.3
Board Repo: andrewpaterson/658-Computer
Board: Board 2x06 W22.86.kicad_pcb
Folder Kicad / Boards / Pins / Board 2x06 W22.86
Complexity 47 / 1000 (size 17, features 30)
KESE features stack-up, dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 0, 0, 0
Triangles, simulation 72 in 3 parts
Note no components
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 6.3 kB 37 MB
STEP 30 kB 37 MB
STL 3.9 kB 36 MB
OBJ 10 kB 36 MB
Visual
GLB 7.7 kB 37 MB
OBJ 10 kB 42 MB

132. Board 2x12 W15.24

Board 2x12 W15.24: reading, start-up and exit take 79% to 89% of a run. Simulation, GLB takes 0.2 s. Simulation, STEP takes 0.2 s. Simulation, STL takes 0.3 s. Simulation, OBJ takes 0.3 s. Visual, GLB takes 0.3 s. Visual, OBJ takes 0.3 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 2 ms 13 ms 9 ms 0.0 ms 9 ms 2 ms 2 ms 0.2 0.2
Simulation, STEP 2 ms 14 ms 6 ms 0.1 ms 10 ms 7 ms 1 ms 0.2 0.2
Simulation, STL 2 ms 11 ms 8 ms 0.0 ms 9 ms 1 ms 2 ms 0.2 0.3
Simulation, OBJ 2 ms 15 ms 3 ms 0.1 ms 9 ms 2 ms 3 ms 0.2 0.3
Visual, GLB 2 ms 12 ms 5 ms 0.1 ms 25 ms 2 ms 10 ms 0.3 0.3
Visual, OBJ 2 ms 14 ms 10 ms 0.0 ms 22 ms 2 ms 9 ms 0.2 0.3
Board Repo: andrewpaterson/658-Computer
Board: Board 2x12 W15.24.kicad_pcb
Folder Kicad / Boards / Pins / Board 2x12 W15.24
Complexity 47 / 1000 (size 17, features 30)
KESE features stack-up, dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 0, 0, 0
Triangles, simulation 72 in 3 parts
Note no components
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 6.3 kB 37 MB
STEP 29 kB 37 MB
STL 3.9 kB 37 MB
OBJ 10 kB 37 MB
Visual
GLB 7.7 kB 41 MB
OBJ 10 kB 41 MB

133. Board 2x12 W22.86

Board 2x12 W22.86: reading, start-up and exit take 73% to 87% of a run. Simulation, GLB takes 0.3 s. Simulation, STEP takes 0.3 s. Simulation, STL takes 0.3 s. Simulation, OBJ takes 0.2 s. Visual, GLB takes 0.3 s. Visual, OBJ takes 0.3 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 2 ms 14 ms 14 ms 0.0 ms 9 ms 1 ms 2 ms 0.2 0.3
Simulation, STEP 2 ms 11 ms 5 ms 0.0 ms 9 ms 7 ms 2 ms 0.2 0.3
Simulation, STL 3 ms 17 ms 4 ms 0.1 ms 15 ms 2 ms 3 ms 0.2 0.3
Simulation, OBJ 2 ms 15 ms 10 ms 0.1 ms 10 ms 1 ms 2 ms 0.2 0.2
Visual, GLB 3 ms 15 ms 4 ms 0.1 ms 25 ms 1 ms 9 ms 0.3 0.3
Visual, OBJ 2 ms 20 ms 6 ms 0.1 ms 31 ms 2 ms 12 ms 0.2 0.3
Board Repo: andrewpaterson/658-Computer
Board: Board 2x12 W22.86.kicad_pcb
Folder Kicad / Boards / Pins / Board 2x12 W22.86
Complexity 47 / 1000 (size 17, features 30)
KESE features stack-up, dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 0, 0, 0
Triangles, simulation 72 in 3 parts
Note no components
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 6.3 kB 35 MB
STEP 29 kB 37 MB
STL 3.9 kB 37 MB
OBJ 10 kB 35 MB
Visual
GLB 7.7 kB 42 MB
OBJ 10 kB 38 MB

134. Board 2x16 W15.24

Board 2x16 W15.24: reading, start-up and exit take 76% to 89% of a run. Simulation, GLB takes 0.2 s. Simulation, STEP takes 0.2 s. Simulation, STL takes 0.3 s. Simulation, OBJ takes 0.2 s. Visual, GLB takes 0.2 s. Visual, OBJ takes 0.3 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 2 ms 10 ms 3 ms 0.0 ms 8 ms 1.0 ms 6 ms 0.2 0.2
Simulation, STEP 2 ms 11 ms 7 ms 0.0 ms 8 ms 6 ms 3 ms 0.2 0.2
Simulation, STL 2 ms 12 ms 6 ms 0.0 ms 9 ms 1 ms 3 ms 0.2 0.3
Simulation, OBJ 2 ms 14 ms 10 ms 0.1 ms 9 ms 1 ms 2 ms 0.2 0.2
Visual, GLB 2 ms 13 ms 15 ms 0.0 ms 15 ms 1 ms 9 ms 0.2 0.2
Visual, OBJ 2 ms 15 ms 6 ms 0.0 ms 25 ms 1 ms 8 ms 0.2 0.3
Board Repo: andrewpaterson/658-Computer
Board: Board 2x16 W15.24.kicad_pcb
Folder Kicad / Boards / Pins / Board 2x16 W15.24
Complexity 47 / 1000 (size 17, features 30)
KESE features stack-up, dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 0, 0, 0
Triangles, simulation 72 in 3 parts
Note no components
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 6.3 kB 37 MB
STEP 29 kB 37 MB
STL 3.9 kB 37 MB
OBJ 10 kB 35 MB
Visual
GLB 7.7 kB 36 MB
OBJ 10 kB 41 MB

135. Board 2x16 W22.86

Board 2x16 W22.86: reading, start-up and exit take 79% to 85% of a run. Simulation, GLB takes 0.3 s. Simulation, STEP takes 0.2 s. Simulation, STL takes 0.2 s. Simulation, OBJ takes 0.2 s. Visual, GLB takes 0.3 s. Visual, OBJ takes 0.3 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 2 ms 21 ms 8 ms 0.0 ms 9 ms 1 ms 2 ms 0.2 0.3
Simulation, STEP 2 ms 13 ms 7 ms 0.0 ms 9 ms 6 ms 6 ms 0.2 0.2
Simulation, STL 2 ms 12 ms 11 ms 0.0 ms 13 ms 1.0 ms 2 ms 0.2 0.2
Simulation, OBJ 2 ms 11 ms 14 ms 0.0 ms 8 ms 2 ms 2 ms 0.2 0.2
Visual, GLB 4 ms 13 ms 4 ms 0.0 ms 25 ms 1 ms 9 ms 0.2 0.3
Visual, OBJ 2 ms 16 ms 10 ms 0.1 ms 23 ms 1 ms 7 ms 0.2 0.3
Board Repo: andrewpaterson/658-Computer
Board: Board 2x16 W22.86.kicad_pcb
Folder Kicad / Boards / Pins / Board 2x16 W22.86
Complexity 47 / 1000 (size 17, features 30)
KESE features stack-up, dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 0, 0, 0
Triangles, simulation 72 in 3 parts
Note no components
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 6.3 kB 37 MB
STEP 29 kB 37 MB
STL 3.9 kB 35 MB
OBJ 10 kB 35 MB
Visual
GLB 7.7 kB 36 MB
OBJ 10 kB 41 MB

136. Board 2x20 W15.24

Board 2x20 W15.24: reading, start-up and exit take 76% to 87% of a run. Simulation, GLB takes 0.2 s. Simulation, STEP takes 0.2 s. Simulation, STL takes 0.2 s. Simulation, OBJ takes 0.2 s. Visual, GLB takes 0.2 s. Visual, OBJ takes 0.2 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 2 ms 10 ms 7 ms 0.0 ms 7 ms 1 ms 4 ms 0.2 0.2
Simulation, STEP 2 ms 12 ms 7 ms 0.0 ms 7 ms 5 ms 4 ms 0.2 0.2
Simulation, STL 2 ms 9 ms 7 ms 0.0 ms 7 ms 1 ms 4 ms 0.2 0.2
Simulation, OBJ 2 ms 10 ms 19 ms 0.1 ms 12 ms 1 ms 1 ms 0.2 0.2
Visual, GLB 2 ms 11 ms 6 ms 0.0 ms 24 ms 1 ms 8 ms 0.2 0.2
Visual, OBJ 2 ms 13 ms 11 ms 0.0 ms 20 ms 1 ms 7 ms 0.2 0.2
Board Repo: andrewpaterson/658-Computer
Board: Board 2x20 W15.24.kicad_pcb
Folder Kicad / Boards / Pins / Board 2x20 W15.24
Complexity 47 / 1000 (size 17, features 30)
KESE features stack-up, dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 0, 0, 0
Triangles, simulation 72 in 3 parts
Note no components
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 6.3 kB 37 MB
STEP 29 kB 37 MB
STL 3.9 kB 37 MB
OBJ 10 kB 37 MB
Visual
GLB 7.7 kB 41 MB
OBJ 10 kB 36 MB

137. Board 2x20 W22.86

Board 2x20 W22.86: reading, start-up and exit take 73% to 86% of a run. Simulation, GLB takes 0.2 s. Simulation, STEP takes 0.3 s. Simulation, STL takes 0.3 s. Simulation, OBJ takes 0.2 s. Visual, GLB takes 0.3 s. Visual, OBJ takes 0.2 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 2 ms 14 ms 12 ms 0.1 ms 11 ms 1.0 ms 2 ms 0.2 0.2
Simulation, STEP 2 ms 15 ms 7 ms 0.0 ms 9 ms 6 ms 2 ms 0.2 0.3
Simulation, STL 3 ms 19 ms 7 ms 0.1 ms 13 ms 1 ms 3 ms 0.2 0.3
Simulation, OBJ 2 ms 18 ms 3 ms 0.0 ms 13 ms 1 ms 2 ms 0.2 0.2
Visual, GLB 2 ms 11 ms 13 ms 0.1 ms 22 ms 1.0 ms 10 ms 0.2 0.3
Visual, OBJ 2 ms 10 ms 10 ms 0.0 ms 29 ms 1 ms 7 ms 0.2 0.2
Board Repo: andrewpaterson/658-Computer
Board: Board 2x20 W22.86.kicad_pcb
Folder Kicad / Boards / Pins / Board 2x20 W22.86
Complexity 47 / 1000 (size 17, features 30)
KESE features stack-up, dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 0, 0, 0
Triangles, simulation 72 in 3 parts
Note no components
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 6.3 kB 35 MB
STEP 29 kB 37 MB
STL 3.9 kB 37 MB
OBJ 10 kB 36 MB
Visual
GLB 7.7 kB 41 MB
OBJ 10 kB 36 MB

138. Board 2x22 W15.24

Board 2x22 W15.24: reading, start-up and exit take 78% to 88% of a run. Simulation, GLB takes 0.3 s. Simulation, STEP takes 0.3 s. Simulation, STL takes 0.3 s. Simulation, OBJ takes 0.3 s. Visual, GLB takes 0.3 s. Visual, OBJ takes 0.3 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 2 ms 15 ms 7 ms 0.0 ms 9 ms 1 ms 4 ms 0.2 0.3
Simulation, STEP 2 ms 18 ms 6 ms 0.0 ms 18 ms 8 ms 2 ms 0.2 0.3
Simulation, STL 2 ms 14 ms 7 ms 0.0 ms 9 ms 1.0 ms 2 ms 0.2 0.3
Simulation, OBJ 2 ms 15 ms 6 ms 0.0 ms 10 ms 2 ms 2 ms 0.2 0.3
Visual, GLB 3 ms 13 ms 9 ms 0.1 ms 30 ms 1 ms 17 ms 0.2 0.3
Visual, OBJ 2 ms 13 ms 5 ms 0.0 ms 30 ms 1 ms 10 ms 0.3 0.3
Board Repo: andrewpaterson/658-Computer
Board: Board 2x22 W15.24.kicad_pcb
Folder Kicad / Boards / Pins / Board 2x22 W15.24
Complexity 47 / 1000 (size 17, features 30)
KESE features stack-up, dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 0, 0, 0
Triangles, simulation 72 in 3 parts
Note no components
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 6.3 kB 36 MB
STEP 29 kB 37 MB
STL 3.9 kB 36 MB
OBJ 10 kB 36 MB
Visual
GLB 7.7 kB 40 MB
OBJ 10 kB 41 MB

139. Board 2x24 W15.24

Board 2x24 W15.24: reading, start-up and exit take 78% to 89% of a run. Simulation, GLB takes 0.3 s. Simulation, STEP takes 0.3 s. Simulation, STL takes 0.2 s. Simulation, OBJ takes 0.3 s. Visual, GLB takes 0.3 s. Visual, OBJ takes 0.3 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 3 ms 16 ms 4 ms 0.1 ms 14 ms 1 ms 3 ms 0.3 0.3
Simulation, STEP 3 ms 15 ms 5 ms 0.1 ms 14 ms 10 ms 2 ms 0.2 0.3
Simulation, STL 2 ms 11 ms 10 ms 0.0 ms 9 ms 0.9 ms 2 ms 0.2 0.2
Simulation, OBJ 3 ms 13 ms 4 ms 0.1 ms 9 ms 2 ms 2 ms 0.2 0.3
Visual, GLB 2 ms 15 ms 6 ms 0.0 ms 26 ms 1 ms 10 ms 0.2 0.3
Visual, OBJ 3 ms 17 ms 4 ms 0.1 ms 25 ms 2 ms 12 ms 0.3 0.3
Board Repo: andrewpaterson/658-Computer
Board: Board 2x24 W15.24.kicad_pcb
Folder Kicad / Boards / Pins / Board 2x24 W15.24
Complexity 47 / 1000 (size 17, features 30)
KESE features stack-up, dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 0, 0, 0
Triangles, simulation 72 in 3 parts
Note no components
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 6.3 kB 37 MB
STEP 29 kB 37 MB
STL 3.9 kB 35 MB
OBJ 10 kB 37 MB
Visual
GLB 7.7 kB 41 MB
OBJ 10 kB 41 MB

140. Board 2x24 W22.86

Board 2x24 W22.86: reading, start-up and exit take 78% to 88% of a run. Simulation, GLB takes 0.3 s. Simulation, STEP takes 0.3 s. Simulation, STL takes 0.3 s. Simulation, OBJ takes 0.3 s. Visual, GLB takes 0.3 s. Visual, OBJ takes 0.3 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 3 ms 15 ms 5 ms 0.1 ms 13 ms 2 ms 3 ms 0.3 0.3
Simulation, STEP 2 ms 22 ms 4 ms 0.1 ms 13 ms 11 ms 2 ms 0.3 0.3
Simulation, STL 2 ms 13 ms 11 ms 0.0 ms 9 ms 1 ms 2 ms 0.2 0.3
Simulation, OBJ 3 ms 15 ms 4 ms 0.1 ms 15 ms 2 ms 2 ms 0.3 0.3
Visual, GLB 2 ms 16 ms 7 ms 0.1 ms 26 ms 1 ms 9 ms 0.2 0.3
Visual, OBJ 2 ms 13 ms 5 ms 0.0 ms 23 ms 2 ms 10 ms 0.2 0.3
Board Repo: andrewpaterson/658-Computer
Board: Board 2x24 W22.86.kicad_pcb
Folder Kicad / Boards / Pins / Board 2x24 W22.86
Complexity 47 / 1000 (size 17, features 30)
KESE features stack-up, dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 0, 0, 0
Triangles, simulation 72 in 3 parts
Note no components
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 6.3 kB 37 MB
STEP 29 kB 37 MB
STL 3.9 kB 37 MB
OBJ 10 kB 37 MB
Visual
GLB 7.7 kB 38 MB
OBJ 10 kB 41 MB

141. Board 2x28 W15.24

Board 2x28 W15.24: reading, start-up and exit take 76% to 87% of a run. Simulation, GLB takes 0.2 s. Simulation, STEP takes 0.2 s. Simulation, STL takes 0.2 s. Simulation, OBJ takes 0.2 s. Visual, GLB takes 0.2 s. Visual, OBJ takes 0.2 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 2 ms 11 ms 7 ms 0.0 ms 9 ms 1 ms 2 ms 0.2 0.2
Simulation, STEP 2 ms 10 ms 11 ms 0.1 ms 13 ms 7 ms 2 ms 0.2 0.2
Simulation, STL 2 ms 13 ms 6 ms 0.0 ms 9 ms 1 ms 2 ms 0.2 0.2
Simulation, OBJ 2 ms 14 ms 3 ms 0.0 ms 8 ms 1 ms 2 ms 0.2 0.2
Visual, GLB 2 ms 10 ms 8 ms 0.0 ms 24 ms 1 ms 8 ms 0.2 0.2
Visual, OBJ 2 ms 10 ms 13 ms 0.0 ms 20 ms 2 ms 9 ms 0.2 0.2
Board Repo: andrewpaterson/658-Computer
Board: Board 2x28 W15.24.kicad_pcb
Folder Kicad / Boards / Pins / Board 2x28 W15.24
Complexity 47 / 1000 (size 17, features 30)
KESE features stack-up, dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 0, 0, 0
Triangles, simulation 72 in 3 parts
Note no components
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 6.3 kB 35 MB
STEP 30 kB 36 MB
STL 3.9 kB 37 MB
OBJ 10 kB 37 MB
Visual
GLB 7.7 kB 36 MB
OBJ 10 kB 41 MB

142. Board 2x28 W22.86

Board 2x28 W22.86: reading, start-up and exit take 78% to 88% of a run. Simulation, GLB takes 0.2 s. Simulation, STEP takes 0.3 s. Simulation, STL takes 0.2 s. Simulation, OBJ takes 0.3 s. Visual, GLB takes 0.3 s. Visual, OBJ takes 0.3 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 2 ms 10 ms 7 ms 0.0 ms 8 ms 1 ms 3 ms 0.2 0.2
Simulation, STEP 2 ms 15 ms 3 ms 0.0 ms 7 ms 5 ms 2 ms 0.2 0.3
Simulation, STL 2 ms 11 ms 6 ms 0.1 ms 9 ms 1 ms 2 ms 0.2 0.2
Simulation, OBJ 2 ms 14 ms 10 ms 0.1 ms 8 ms 1 ms 3 ms 0.2 0.3
Visual, GLB 2 ms 15 ms 5 ms 0.0 ms 26 ms 2 ms 12 ms 0.2 0.3
Visual, OBJ 2 ms 12 ms 7 ms 0.0 ms 23 ms 2 ms 9 ms 0.2 0.3
Board Repo: andrewpaterson/658-Computer
Board: Board 2x28 W22.86.kicad_pcb
Folder Kicad / Boards / Pins / Board 2x28 W22.86
Complexity 47 / 1000 (size 17, features 30)
KESE features stack-up, dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 0, 0, 0
Triangles, simulation 72 in 3 parts
Note no components
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 6.3 kB 37 MB
STEP 30 kB 37 MB
STL 3.9 kB 36 MB
OBJ 10 kB 37 MB
Visual
GLB 7.7 kB 38 MB
OBJ 10 kB 41 MB

143. Board 2x32 W15.24

Board 2x32 W15.24: reading, start-up and exit take 78% to 87% of a run. Simulation, GLB takes 0.3 s. Simulation, STEP takes 0.3 s. Simulation, STL takes 0.3 s. Simulation, OBJ takes 0.3 s. Visual, GLB takes 0.3 s. Visual, OBJ takes 0.3 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 2 ms 14 ms 5 ms 0.1 ms 16 ms 2 ms 3 ms 0.2 0.3
Simulation, STEP 2 ms 13 ms 9 ms 0.1 ms 12 ms 9 ms 3 ms 0.2 0.3
Simulation, STL 3 ms 17 ms 7 ms 0.1 ms 14 ms 2 ms 3 ms 0.2 0.3
Simulation, OBJ 2 ms 12 ms 10 ms 0.1 ms 8 ms 1 ms 2 ms 0.2 0.3
Visual, GLB 3 ms 17 ms 6 ms 0.1 ms 28 ms 2 ms 13 ms 0.3 0.3
Visual, OBJ 3 ms 12 ms 7 ms 0.0 ms 27 ms 1 ms 10 ms 0.2 0.3
Board Repo: andrewpaterson/658-Computer
Board: Board 2x32 W15.24.kicad_pcb
Folder Kicad / Boards / Pins / Board 2x32 W15.24
Complexity 47 / 1000 (size 17, features 30)
KESE features stack-up, dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 0, 0, 0
Triangles, simulation 72 in 3 parts
Note no components
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 6.3 kB 37 MB
STEP 29 kB 37 MB
STL 3.9 kB 37 MB
OBJ 10 kB 37 MB
Visual
GLB 7.7 kB 40 MB
OBJ 10 kB 41 MB

144. Board 2x32 W22.86

Board 2x32 W22.86: reading, start-up and exit take 79% to 87% of a run. Simulation, GLB takes 0.3 s. Simulation, STEP takes 0.3 s. Simulation, STL takes 0.3 s. Simulation, OBJ takes 0.3 s. Visual, GLB takes 0.3 s. Visual, OBJ takes 0.3 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 3 ms 14 ms 4 ms 0.1 ms 14 ms 1 ms 3 ms 0.2 0.3
Simulation, STEP 2 ms 12 ms 9 ms 0.0 ms 10 ms 7 ms 2 ms 0.2 0.3
Simulation, STL 3 ms 20 ms 7 ms 0.0 ms 9 ms 0.9 ms 2 ms 0.2 0.3
Simulation, OBJ 2 ms 14 ms 7 ms 0.1 ms 15 ms 2 ms 2 ms 0.2 0.3
Visual, GLB 3 ms 14 ms 5 ms 0.0 ms 21 ms 1 ms 10 ms 0.2 0.3
Visual, OBJ 2 ms 14 ms 7 ms 0.0 ms 23 ms 1 ms 9 ms 0.2 0.3
Board Repo: andrewpaterson/658-Computer
Board: Board 2x32 W22.86.kicad_pcb
Folder Kicad / Boards / Pins / Board 2x32 W22.86
Complexity 47 / 1000 (size 17, features 30)
KESE features stack-up, dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 0, 0, 0
Triangles, simulation 72 in 3 parts
Note no components
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 6.3 kB 37 MB
STEP 29 kB 37 MB
STL 3.9 kB 37 MB
OBJ 10 kB 37 MB
Visual
GLB 7.7 kB 38 MB
OBJ 10 kB 37 MB

145. Board 2x36 W22.86

Board 2x36 W22.86: reading, start-up and exit take 75% to 87% of a run. Simulation, GLB takes 0.2 s. Simulation, STEP takes 0.2 s. Simulation, STL takes 0.2 s. Simulation, OBJ takes 0.2 s. Visual, GLB takes 0.2 s. Visual, OBJ takes 0.2 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 2 ms 14 ms 8 ms 0.0 ms 8 ms 1 ms 2 ms 0.2 0.2
Simulation, STEP 2 ms 9 ms 5 ms 0.0 ms 7 ms 5 ms 8 ms 0.2 0.2
Simulation, STL 2 ms 16 ms 4 ms 0.0 ms 7 ms 0.7 ms 7 ms 0.2 0.2
Simulation, OBJ 2 ms 11 ms 3 ms 0.0 ms 6 ms 1.0 ms 8 ms 0.2 0.2
Visual, GLB 2 ms 8 ms 8 ms 0.0 ms 28 ms 1 ms 10 ms 0.2 0.2
Visual, OBJ 2 ms 11 ms 7 ms 0.0 ms 24 ms 1 ms 9 ms 0.2 0.2
Board Repo: andrewpaterson/658-Computer
Board: Board 2x36 W22.86.kicad_pcb
Folder Kicad / Boards / Pins / Board 2x36 W22.86
Complexity 47 / 1000 (size 17, features 30)
KESE features stack-up, dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 0, 0, 0
Triangles, simulation 72 in 3 parts
Note no components
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 6.3 kB 37 MB
STEP 29 kB 37 MB
STL 3.9 kB 37 MB
OBJ 10 kB 37 MB
Visual
GLB 7.7 kB 40 MB
OBJ 10 kB 38 MB

146. Audio Address Decode

Audio Address Decode: stages 4 and 6 take 49% to 80% of a run. Simulation, GLB takes 2.5 s. Simulation, STEP takes 3.5 s. Simulation, STL takes 2.5 s. Simulation, OBJ takes 3.7 s. Visual, GLB takes 3.5 s. Visual, OBJ takes 4.5 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.2 1.0 0.2 ms 0.8 37 ms 0.1 0.2 2.5
Simulation, STEP 0.1 0.2 1.0 0.2 ms 0.8 1.0 0.1 0.2 3.5
Simulation, STL 0.1 0.2 1.0 0.2 ms 0.8 52 ms 0.1 0.2 2.5
Simulation, OBJ 0.1 0.2 0.9 0.2 ms 0.9 1.2 0.1 0.2 3.7
Visual, GLB 0.1 0.2 0.9 0.2 ms 1.8 28 ms 0.2 0.2 3.5
Visual, OBJ 0.1 0.2 1.0 0.2 ms 1.8 0.9 0.2 0.2 4.5
Board Repo: andrewpaterson/658-Computer
Board: Audio Address Decode.kicad_pcb
Folder Kicad / Computer / Audio / Audio Address Decode
Complexity 205 / 1000 (size 135, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 8, 237, 28
Triangles, simulation 236,188 in 37 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 8.2 MB 219 MB
STEP 37 MB 245 MB
STL 12 MB 216 MB
OBJ 24 MB 214 MB
Visual
GLB 6.1 MB 211 MB
OBJ 18 MB 216 MB

147. Audio Board

Audio Board: stages 4 and 6 take 53% to 86% of a run. Simulation, GLB takes 35 s. Simulation, STEP takes 43 s. Simulation, STL takes 35 s. Simulation, OBJ takes 53 s. Visual, GLB takes 54 s. Visual, OBJ takes 65 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.5 2.9 16.3 0.8 ms 12.6 0.6 1.8 0.3 34.9
Simulation, STEP 0.5 2.9 16.1 0.9 ms 12.8 8.9 1.7 0.3 43.2
Simulation, STL 0.5 2.8 15.7 0.9 ms 13.0 1.0 1.8 0.3 35.0
Simulation, OBJ 0.4 2.8 16.1 0.9 ms 12.2 19.5 1.9 0.3 53.3
Visual, GLB 0.4 2.8 16.5 1 ms 30.1 0.3 3.9 0.2 54.3
Visual, OBJ 0.5 2.8 16.0 0.9 ms 28.7 12.6 3.9 0.3 64.8
Board Repo: andrewpaterson/658-Computer
Board: Audio Board.kicad_pcb
Folder Kicad / Computer / Audio / Audio Board
Complexity 263 / 1000 (size 183, features 80)
KESE features through vias, rounded,
trapezoid or chamfered pads,
curved board outline,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 23, 2,507, 229
Triangles, simulation 3,598,500 in 299 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 120 MB 1.2 GB
STEP 501 MB 1.4 GB
STL 180 MB 1.1 GB
OBJ 377 MB 2.3 GB
Visual
GLB 78 MB 1.6 GB
OBJ 248 MB 1.7 GB

148. Audio Clock

Audio Clock: stages 4 and 6 take 49% to 78% of a run. Simulation, GLB takes 5.4 s. Simulation, STEP takes 6.1 s. Simulation, STL takes 4.4 s. Simulation, OBJ takes 6.8 s. Visual, GLB takes 7.4 s. Visual, OBJ takes 9.0 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.5 1.7 0.4 ms 2.3 72 ms 0.3 0.3 5.4
Simulation, STEP 0.2 0.5 1.6 0.5 ms 1.7 1.5 0.3 0.3 6.1
Simulation, STL 0.1 0.4 1.6 0.3 ms 1.6 0.1 0.3 0.2 4.4
Simulation, OBJ 0.3 0.5 1.6 0.5 ms 1.7 2.2 0.3 0.3 6.8
Visual, GLB 0.2 0.4 1.7 0.4 ms 4.1 67 ms 0.7 0.3 7.4
Visual, OBJ 0.2 0.5 1.4 0.3 ms 4.1 1.9 0.7 0.3 9.0
Board Repo: andrewpaterson/658-Computer
Board: Audio Clock.kicad_pcb
Folder Kicad / Computer / Audio / Audio Clock
Complexity 227 / 1000 (size 157, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 23, 449, 67
Triangles, simulation 413,586 in 67 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 14 MB 268 MB
STEP 62 MB 323 MB
STL 21 MB 269 MB
OBJ 42 MB 330 MB
Visual
GLB 11 MB 343 MB
OBJ 34 MB 329 MB

149. Blitter Board

Blitter Board: stages 4 and 6 take 51% to 85% of a run. Simulation, GLB takes 35 s. Simulation, STEP takes 43 s. Simulation, STL takes 35 s. Simulation, OBJ takes 58 s. Visual, GLB takes 57 s. Visual, OBJ takes 72 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.5 3.1 16.5 1 ms 11.8 0.6 1.8 0.3 34.5
Simulation, STEP 0.5 3.0 16.5 1 ms 11.8 9.2 1.7 0.3 42.9
Simulation, STL 0.5 3.1 16.1 1 ms 11.4 1.4 1.8 0.3 34.6
Simulation, OBJ 0.5 3.0 18.0 1 ms 11.6 22.7 1.9 0.3 57.9
Visual, GLB 0.5 3.4 16.4 1 ms 32.0 0.4 3.8 0.2 56.9
Visual, OBJ 0.5 3.1 16.4 1 ms 33.9 13.8 4.1 0.3 72.1
Board Repo: andrewpaterson/658-Computer
Board: Blitter Board.kicad_pcb
Folder Kicad / Computer / Blitter / Blitter Board
Complexity 264 / 1000 (size 184, features 80)
KESE features through vias, rounded,
trapezoid or chamfered pads,
curved board outline,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 22, 2,712, 230
Triangles, simulation 3,921,994 in 339 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 131 MB 1.3 GB
STEP 550 MB 1.5 GB
STL 196 MB 1.3 GB
OBJ 412 MB 2.5 GB
Visual
GLB 86 MB 1.5 GB
OBJ 272 MB 1.8 GB

150. Added 8bit

Added 8bit: stages 4 and 6 take 48% to 81% of a run. Simulation, GLB takes 3.0 s. Simulation, STEP takes 4.3 s. Simulation, STL takes 3.3 s. Simulation, OBJ takes 4.7 s. Visual, GLB takes 4.3 s. Visual, OBJ takes 5.6 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.3 1.2 0.1 ms 1.1 47 ms 0.2 0.2 3.0
Simulation, STEP 0.1 0.3 1.3 0.2 ms 1.0 1.2 0.2 0.2 4.3
Simulation, STL 0.1 0.3 1.2 0.2 ms 1.1 67 ms 0.2 0.2 3.3
Simulation, OBJ 0.1 0.3 1.2 0.1 ms 1.1 1.7 0.2 0.2 4.7
Visual, GLB 0.1 0.3 1.1 0.2 ms 2.4 33 ms 0.2 0.2 4.3
Visual, OBJ 0.1 0.3 1.1 0.2 ms 2.4 1.3 0.3 0.2 5.6
Board Repo: andrewpaterson/658-Computer
Board: Added 8bit.kicad_pcb
Folder Kicad / Computer / Component Boards / Added 8bit
Complexity 206 / 1000 (size 136, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 7, 238, 43
Triangles, simulation 301,014 in 39 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 10 MB 245 MB
STEP 46 MB 265 MB
STL 15 MB 245 MB
OBJ 30 MB 245 MB
Visual
GLB 7.3 MB 245 MB
OBJ 22 MB 251 MB

151. Adder 16bit

Adder 16bit: stages 4 and 6 take 50% to 83% of a run. Simulation, GLB takes 6.3 s. Simulation, STEP takes 8.6 s. Simulation, STL takes 6.9 s. Simulation, OBJ takes 8.8 s. Visual, GLB takes 10 s. Visual, OBJ takes 12 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.5 2.4 0.5 ms 2.3 0.1 0.5 0.3 6.3
Simulation, STEP 0.2 0.5 2.5 0.7 ms 2.4 2.3 0.5 0.3 8.6
Simulation, STL 0.2 0.7 2.8 0.4 ms 2.5 0.2 0.3 0.2 6.9
Simulation, OBJ 0.2 0.6 2.3 0.3 ms 2.1 3.0 0.4 0.2 8.8
Visual, GLB 0.2 0.6 2.6 0.7 ms 5.7 67 ms 0.6 0.2 10.0
Visual, OBJ 0.1 0.5 2.5 0.3 ms 5.9 2.1 0.6 0.2 12.0
Board Repo: andrewpaterson/658-Computer
Board: Adder 16bit.kicad_pcb
Folder Kicad / Computer / Component Boards / Adder 16bit
Complexity 225 / 1000 (size 155, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 11, 627, 83
Triangles, simulation 565,568 in 65 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 20 MB 343 MB
STEP 90 MB 369 MB
STL 28 MB 335 MB
OBJ 57 MB 418 MB
Visual
GLB 14 MB 388 MB
OBJ 42 MB 391 MB

152. Address Buffer 16bit

Address Buffer 16bit: stages 4 and 6 take 50% to 81% of a run. Simulation, GLB takes 4.9 s. Simulation, STEP takes 6.4 s. Simulation, STL takes 4.9 s. Simulation, OBJ takes 7.3 s. Visual, GLB takes 7.7 s. Visual, OBJ takes 9.9 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.5 2.0 0.2 ms 1.7 0.1 0.3 0.2 4.9
Simulation, STEP 0.2 0.5 1.9 0.3 ms 1.6 1.8 0.3 0.2 6.4
Simulation, STL 0.2 0.5 2.0 0.2 ms 1.7 0.1 0.3 0.2 4.9
Simulation, OBJ 0.2 0.5 2.0 0.3 ms 1.7 2.4 0.3 0.2 7.3
Visual, GLB 0.2 0.5 2.0 0.4 ms 4.2 61 ms 0.5 0.2 7.7
Visual, OBJ 0.2 0.5 2.0 0.3 ms 4.1 2.2 0.7 0.2 9.9
Board Repo: andrewpaterson/658-Computer
Board: Address Buffer 16bit.kicad_pcb
Folder Kicad / Computer / Component Boards / Address Buffer 16bit
Complexity 231 / 1000 (size 161, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 20, 636, 77
Triangles, simulation 484,576 in 63 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 17 MB 284 MB
STEP 80 MB 352 MB
STL 24 MB 287 MB
OBJ 49 MB 378 MB
Visual
GLB 13 MB 367 MB
OBJ 39 MB 376 MB

153. Address Buffer 24bit

Address Buffer 24bit: stages 4 and 6 take 50% to 83% of a run. Simulation, GLB takes 8.4 s. Simulation, STEP takes 10 s. Simulation, STL takes 8.2 s. Simulation, OBJ takes 12 s. Visual, GLB takes 12 s. Visual, OBJ takes 15 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.9 3.3 0.4 ms 3.2 0.1 0.5 0.2 8.4
Simulation, STEP 0.3 0.8 3.3 0.3 ms 2.9 2.4 0.5 0.2 10.3
Simulation, STL 0.3 0.8 3.2 0.4 ms 3.0 0.2 0.4 0.3 8.2
Simulation, OBJ 0.2 0.8 3.3 0.5 ms 2.9 4.3 0.6 0.3 12.4
Visual, GLB 0.3 0.9 3.4 0.4 ms 6.3 99 ms 0.5 0.3 11.8
Visual, OBJ 0.2 0.8 3.5 0.4 ms 6.3 3.4 0.5 0.2 15.1
Board Repo: andrewpaterson/658-Computer
Board: Address Buffer 24bit.kicad_pcb
Folder Kicad / Computer / Component Boards / Address Buffer 24bit
Complexity 239 / 1000 (size 169, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 28, 857, 114
Triangles, simulation 684,690 in 87 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 24 MB 344 MB
STEP 112 MB 427 MB
STL 34 MB 357 MB
OBJ 70 MB 510 MB
Visual
GLB 18 MB 503 MB
OBJ 55 MB 495 MB

154. Audio DAC

Audio DAC: stages 4 and 6 take 49% to 81% of a run. Simulation, GLB takes 4.5 s. Simulation, STEP takes 6.4 s. Simulation, STL takes 4.6 s. Simulation, OBJ takes 6.8 s. Visual, GLB takes 7.1 s. Visual, OBJ takes 8.9 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.5 1.7 0.3 ms 1.6 83 ms 0.3 0.2 4.5
Simulation, STEP 0.2 0.5 1.9 0.3 ms 1.8 1.6 0.3 0.3 6.4
Simulation, STL 0.2 0.4 1.8 0.3 ms 1.6 0.1 0.3 0.2 4.6
Simulation, OBJ 0.2 0.5 1.8 0.2 ms 1.5 2.3 0.3 0.2 6.8
Visual, GLB 0.2 0.4 1.8 0.5 ms 4.0 59 ms 0.5 0.2 7.1
Visual, OBJ 0.2 0.5 1.9 0.5 ms 4.0 1.6 0.5 0.3 8.9
Board Repo: andrewpaterson/658-Computer
Board: Audio DAC.kicad_pcb
Folder Kicad / Computer / Component Boards / Audio DAC
Complexity 228 / 1000 (size 158, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 30, 396, 54
Triangles, simulation 450,154 in 60 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 15 MB 287 MB
STEP 68 MB 336 MB
STL 23 MB 290 MB
OBJ 45 MB 353 MB
Visual
GLB 12 MB 349 MB
OBJ 35 MB 343 MB

155. Big Board

Big Board: stages 4 and 6 take 50% to 83% of a run. Simulation, GLB takes 3.8 s. Simulation, STEP takes 5.0 s. Simulation, STL takes 3.8 s. Simulation, OBJ takes 5.8 s. Visual, GLB takes 5.4 s. Visual, OBJ takes 6.4 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.3 1.6 0.3 ms 1.2 61 ms 0.2 0.2 3.8
Simulation, STEP 0.1 0.3 1.6 0.3 ms 1.2 1.3 0.2 0.2 5.0
Simulation, STL 0.1 0.3 1.6 0.2 ms 1.2 0.1 0.3 0.2 3.8
Simulation, OBJ 0.1 0.3 1.7 0.4 ms 1.2 2.0 0.3 0.2 5.8
Visual, GLB 0.1 0.3 1.7 0.5 ms 2.8 37 ms 0.3 0.2 5.4
Visual, OBJ 0.1 0.3 1.6 0.3 ms 2.8 1.2 0.2 0.2 6.4
Board Repo: andrewpaterson/658-Computer
Board: Big Board.kicad_pcb
Folder Kicad / Computer / Component Boards / Big Board
Complexity 163 / 1000 (size 88, features 75)
KESE features through vias, rounded,
trapezoid or chamfered pads,
filled zones, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 4, 23, 1
Triangles, simulation 402,342 in 72 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 13 MB 264 MB
STEP 46 MB 295 MB
STL 20 MB 272 MB
OBJ 40 MB 275 MB
Visual
GLB 8.1 MB 273 MB
OBJ 24 MB 277 MB

156. Clock Doubler

Clock Doubler: stages 4 and 6 take 51% to 80% of a run. Simulation, GLB takes 2.5 s. Simulation, STEP takes 3.5 s. Simulation, STL takes 2.4 s. Simulation, OBJ takes 3.5 s. Visual, GLB takes 3.7 s. Visual, OBJ takes 4.5 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.2 0.9 0.2 ms 0.8 36 ms 0.1 0.2 2.5
Simulation, STEP 0.1 0.2 1.0 0.2 ms 0.8 1.1 0.1 0.2 3.5
Simulation, STL 0.1 0.2 0.9 0.2 ms 0.8 53 ms 0.1 0.2 2.4
Simulation, OBJ 0.1 0.2 1.0 0.1 ms 0.8 1.1 0.1 0.2 3.5
Visual, GLB 0.1 0.2 0.9 0.2 ms 2.0 29 ms 0.2 0.2 3.7
Visual, OBJ 0.1 0.3 0.9 0.2 ms 1.9 0.9 0.2 0.2 4.5
Board Repo: andrewpaterson/658-Computer
Board: Clock Doubler.kicad_pcb
Folder Kicad / Computer / Component Boards / Clock Doubler
Complexity 207 / 1000 (size 137, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 15, 178, 23
Triangles, simulation 220,574 in 38 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 7.5 MB 214 MB
STEP 32 MB 235 MB
STL 11 MB 212 MB
OBJ 22 MB 218 MB
Visual
GLB 5.5 MB 218 MB
OBJ 16 MB 214 MB

157. Clock Hold Select

Clock Hold Select: stages 4 and 6 take 54% to 83% of a run. Simulation, GLB takes 6.0 s. Simulation, STEP takes 7.8 s. Simulation, STL takes 6.0 s. Simulation, OBJ takes 8.3 s. Visual, GLB takes 9.3 s. Visual, OBJ takes 12 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.5 2.4 0.6 ms 2.2 87 ms 0.3 0.2 6.0
Simulation, STEP 0.2 0.6 2.5 0.4 ms 2.1 1.9 0.3 0.2 7.8
Simulation, STL 0.2 0.5 2.4 0.4 ms 2.1 0.2 0.3 0.2 6.0
Simulation, OBJ 0.2 0.5 2.5 0.4 ms 2.0 2.6 0.3 0.2 8.3
Visual, GLB 0.2 0.5 2.5 0.4 ms 5.2 74 ms 0.5 0.2 9.3
Visual, OBJ 0.2 0.6 2.4 0.6 ms 5.3 2.3 0.6 0.3 11.8
Board Repo: andrewpaterson/658-Computer
Board: Clock Hold Select.kicad_pcb
Folder Kicad / Computer / Component Boards / Clock Hold Select
Complexity 233 / 1000 (size 163, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 23, 645, 84
Triangles, simulation 536,128 in 92 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 18 MB 313 MB
STEP 86 MB 379 MB
STL 27 MB 310 MB
OBJ 55 MB 415 MB
Visual
GLB 15 MB 440 MB
OBJ 46 MB 404 MB

158. Clock Hold Standard

Clock Hold Standard: stages 4 and 6 take 50% to 82% of a run. Simulation, GLB takes 3.7 s. Simulation, STEP takes 5.2 s. Simulation, STL takes 4.0 s. Simulation, OBJ takes 5.8 s. Visual, GLB takes 5.6 s. Visual, OBJ takes 7.3 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.3 1.5 0.4 ms 1.3 67 ms 0.2 0.2 3.7
Simulation, STEP 0.1 0.3 1.5 0.2 ms 1.4 1.4 0.2 0.2 5.2
Simulation, STL 0.2 0.3 1.5 0.2 ms 1.4 82 ms 0.2 0.2 4.0
Simulation, OBJ 0.2 0.3 1.6 0.2 ms 1.3 1.9 0.2 0.3 5.8
Visual, GLB 0.1 0.3 1.5 0.2 ms 3.1 46 ms 0.3 0.2 5.6
Visual, OBJ 0.1 0.3 1.5 3 ms 3.3 1.5 0.3 0.2 7.3
Board Repo: andrewpaterson/658-Computer
Board: Clock Hold Standard.kicad_pcb
Folder Kicad / Computer / Component Boards / Clock Hold Standard
Complexity 219 / 1000 (size 149, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 12, 434, 55
Triangles, simulation 321,760 in 47 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 11 MB 242 MB
STEP 52 MB 286 MB
STL 16 MB 243 MB
OBJ 33 MB 262 MB
Visual
GLB 9.0 MB 280 MB
OBJ 26 MB 282 MB

159. Clock Transition

Clock Transition: stages 4 and 6 take 49% to 79% of a run. Simulation, GLB takes 2.6 s. Simulation, STEP takes 3.5 s. Simulation, STL takes 2.6 s. Simulation, OBJ takes 3.8 s. Visual, GLB takes 3.6 s. Visual, OBJ takes 4.8 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.2 0.9 0.2 ms 1.0 38 ms 0.1 0.2 2.6
Simulation, STEP 0.1 0.2 0.9 0.1 ms 0.9 1.0 0.1 0.2 3.5
Simulation, STL 0.1 0.2 0.9 0.1 ms 0.9 53 ms 0.1 0.2 2.6
Simulation, OBJ 0.1 0.3 0.9 0.2 ms 1.0 1.2 0.1 0.2 3.8
Visual, GLB 0.1 0.2 0.9 0.2 ms 1.9 32 ms 0.2 0.2 3.6
Visual, OBJ 0.1 0.2 0.9 0.2 ms 2.0 1.1 0.2 0.2 4.8
Board Repo: andrewpaterson/658-Computer
Board: Clock Transition.kicad_pcb
Folder Kicad / Computer / Component Boards / Clock Transition
Complexity 216 / 1000 (size 146, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 14, 298, 49
Triangles, simulation 238,130 in 35 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 8.2 MB 220 MB
STEP 37 MB 251 MB
STL 12 MB 220 MB
OBJ 24 MB 225 MB
Visual
GLB 7.0 MB 233 MB
OBJ 20 MB 234 MB

160. Comparator 10bit

Comparator 10bit: stages 4 and 6 take 51% to 81% of a run. Simulation, GLB takes 3.4 s. Simulation, STEP takes 4.7 s. Simulation, STL takes 3.6 s. Simulation, OBJ takes 5.1 s. Visual, GLB takes 5.7 s. Visual, OBJ takes 6.8 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.3 1.4 0.2 ms 1.2 58 ms 0.2 0.2 3.4
Simulation, STEP 0.1 0.3 1.4 0.3 ms 1.3 1.2 0.2 0.2 4.7
Simulation, STL 0.1 0.4 1.4 0.2 ms 1.2 0.1 0.2 0.2 3.6
Simulation, OBJ 0.1 0.3 1.5 0.2 ms 1.1 1.6 0.2 0.2 5.1
Visual, GLB 0.1 0.3 1.4 0.3 ms 3.3 47 ms 0.4 0.2 5.7
Visual, OBJ 0.1 0.3 1.3 0.3 ms 3.2 1.2 0.3 0.2 6.8
Board Repo: andrewpaterson/658-Computer
Board: Comparator 10bit.kicad_pcb
Folder Kicad / Computer / Component Boards / Comparator 10bit
Complexity 223 / 1000 (size 153, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 14, 485, 62
Triangles, simulation 393,638 in 59 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 14 MB 265 MB
STEP 64 MB 309 MB
STL 20 MB 266 MB
OBJ 40 MB 320 MB
Visual
GLB 10 MB 322 MB
OBJ 31 MB 316 MB

161. Comparator 16bit

Comparator 16bit: stages 4 and 6 take 51% to 82% of a run. Simulation, GLB takes 5.4 s. Simulation, STEP takes 7.2 s. Simulation, STL takes 5.7 s. Simulation, OBJ takes 8.5 s. Visual, GLB takes 7.9 s. Visual, OBJ takes 10 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.5 2.2 0.3 ms 1.9 74 ms 0.3 0.2 5.4
Simulation, STEP 0.1 0.5 2.1 0.2 ms 2.1 1.8 0.3 0.2 7.2
Simulation, STL 0.2 0.5 2.3 0.4 ms 2.0 0.2 0.3 0.2 5.7
Simulation, OBJ 0.2 0.6 2.2 0.2 ms 2.2 2.9 0.3 0.2 8.5
Visual, GLB 0.2 0.5 2.1 0.4 ms 4.4 78 ms 0.5 0.2 7.9
Visual, OBJ 0.2 0.5 2.2 0.2 ms 4.4 2.1 0.5 0.3 10.1
Board Repo: andrewpaterson/658-Computer
Board: Comparator 16bit.kicad_pcb
Folder Kicad / Computer / Component Boards / Comparator 16bit
Complexity 230 / 1000 (size 160, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 13, 798, 90
Triangles, simulation 523,882 in 64 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 18 MB 319 MB
STEP 87 MB 363 MB
STL 26 MB 308 MB
OBJ 53 MB 403 MB
Visual
GLB 14 MB 380 MB
OBJ 42 MB 382 MB

162. Counter 16bit with IO

Counter 16bit with IO: stages 4 and 6 take 54% to 81% of a run. Simulation, GLB takes 7.2 s. Simulation, STEP takes 9.4 s. Simulation, STL takes 7.3 s. Simulation, OBJ takes 11 s. Visual, GLB takes 11 s. Visual, OBJ takes 14 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.7 2.6 0.6 ms 3.0 0.1 0.4 0.2 7.2
Simulation, STEP 0.2 0.7 2.8 0.5 ms 2.8 2.2 0.5 0.2 9.4
Simulation, STL 0.2 0.7 2.6 0.4 ms 3.0 0.2 0.4 0.2 7.3
Simulation, OBJ 0.2 0.7 2.7 0.5 ms 3.0 3.3 0.4 0.2 10.5
Visual, GLB 0.2 0.8 2.8 0.3 ms 6.2 0.1 0.8 0.2 11.1
Visual, OBJ 0.2 0.7 2.7 0.6 ms 6.4 3.1 0.9 0.2 14.1
Board Repo: andrewpaterson/658-Computer
Board: Counter 16bit with IO.kicad_pcb
Folder Kicad / Computer / Component Boards / Counter 16bit with IO
Complexity 246 / 1000 (size 176, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 24, 1,368, 199
Triangles, simulation 864,154 in 70 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 30 MB 436 MB
STEP 142 MB 501 MB
STL 43 MB 454 MB
OBJ 88 MB 623 MB
Visual
GLB 25 MB 616 MB
OBJ 77 MB 649 MB

163. Counter 16bit

Counter 16bit: stages 4 and 6 take 52% to 80% of a run. Simulation, GLB takes 5.3 s. Simulation, STEP takes 6.8 s. Simulation, STL takes 5.1 s. Simulation, OBJ takes 7.3 s. Visual, GLB takes 8.3 s. Visual, OBJ takes 10 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.5 2.1 0.4 ms 1.9 77 ms 0.3 0.2 5.3
Simulation, STEP 0.2 0.5 2.0 0.4 ms 1.9 1.7 0.3 0.2 6.8
Simulation, STL 0.2 0.5 2.0 0.3 ms 1.8 0.1 0.3 0.2 5.1
Simulation, OBJ 0.2 0.5 1.9 0.3 ms 1.8 2.3 0.3 0.2 7.3
Visual, GLB 0.2 0.5 2.0 0.3 ms 4.6 76 ms 0.7 0.3 8.3
Visual, OBJ 0.2 0.5 2.0 0.4 ms 4.5 1.9 0.7 0.3 10.0
Board Repo: andrewpaterson/658-Computer
Board: Counter 16bit.kicad_pcb
Folder Kicad / Computer / Component Boards / Counter 16bit
Complexity 224 / 1000 (size 154, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 14, 508, 78
Triangles, simulation 468,570 in 52 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 16 MB 294 MB
STEP 74 MB 347 MB
STL 23 MB 308 MB
OBJ 47 MB 366 MB
Visual
GLB 12 MB 353 MB
OBJ 37 MB 356 MB

164. Counter 24bit with IO

Counter 24bit with IO: stages 4 and 6 take 56% to 83% of a run. Simulation, GLB takes 13 s. Simulation, STEP takes 15 s. Simulation, STL takes 13 s. Simulation, OBJ takes 17 s. Visual, GLB takes 19 s. Visual, OBJ takes 23 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.3 1.2 5.1 0.6 ms 5.2 0.2 0.6 0.3 12.8
Simulation, STEP 0.2 1.0 4.8 0.7 ms 4.6 3.5 0.6 0.2 15.1
Simulation, STL 0.3 1.2 5.0 0.7 ms 5.0 0.4 0.6 0.3 12.8
Simulation, OBJ 0.3 1.2 4.8 0.7 ms 4.8 5.3 0.6 0.2 17.3
Visual, GLB 0.3 1.1 4.8 0.7 ms 10.8 0.2 1.4 0.2 18.7
Visual, OBJ 0.3 1.0 4.6 0.6 ms 10.5 4.8 1.6 0.2 23.0
Board Repo: andrewpaterson/658-Computer
Board: Counter 24bit with IO.kicad_pcb
Folder Kicad / Computer / Component Boards / Counter 24bit with IO
Complexity 256 / 1000 (size 186, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 32, 2,287, 246
Triangles, simulation 1,167,700 in 106 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 40 MB 551 MB
STEP 192 MB 635 MB
STL 58 MB 555 MB
OBJ 119 MB 824 MB
Visual
GLB 34 MB 693 MB
OBJ 102 MB 771 MB

165. Counter 24bit

Counter 24bit: stages 4 and 6 take 52% to 84% of a run. Simulation, GLB takes 6.5 s. Simulation, STEP takes 8.5 s. Simulation, STL takes 6.8 s. Simulation, OBJ takes 9.6 s. Visual, GLB takes 10 s. Visual, OBJ takes 12 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.6 2.6 0.5 ms 2.4 0.1 0.3 0.2 6.5
Simulation, STEP 0.2 0.7 2.8 0.3 ms 2.2 2.0 0.4 0.2 8.5
Simulation, STL 0.2 0.6 2.6 0.4 ms 2.5 0.2 0.4 0.2 6.8
Simulation, OBJ 0.2 0.7 2.6 0.3 ms 2.4 3.1 0.4 0.2 9.6
Visual, GLB 0.2 0.7 2.7 0.5 ms 5.9 71 ms 0.5 0.2 10.3
Visual, OBJ 0.2 0.5 2.6 0.4 ms 5.6 2.4 0.7 0.2 12.3
Board Repo: andrewpaterson/658-Computer
Board: Counter 24bit.kicad_pcb
Folder Kicad / Computer / Component Boards / Counter 24bit
Complexity 234 / 1000 (size 164, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 18, 816, 114
Triangles, simulation 673,350 in 71 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 23 MB 375 MB
STEP 108 MB 421 MB
STL 34 MB 361 MB
OBJ 68 MB 496 MB
Visual
GLB 18 MB 481 MB
OBJ 53 MB 466 MB

166. D Flip Flop 16bit

D Flip Flop 16bit: stages 4 and 6 take 51% to 82% of a run. Simulation, GLB takes 4.9 s. Simulation, STEP takes 6.6 s. Simulation, STL takes 4.9 s. Simulation, OBJ takes 6.4 s. Visual, GLB takes 6.8 s. Visual, OBJ takes 9.2 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.5 1.9 0.3 ms 1.7 89 ms 0.3 0.3 4.9
Simulation, STEP 0.2 0.4 2.0 0.2 ms 1.6 1.8 0.3 0.2 6.6
Simulation, STL 0.2 0.4 1.9 0.2 ms 1.6 0.1 0.3 0.3 4.9
Simulation, OBJ 0.2 0.4 1.8 0.3 ms 1.5 1.9 0.3 0.3 6.4
Visual, GLB 0.2 0.4 2.0 0.3 ms 3.6 48 ms 0.3 0.3 6.8
Visual, OBJ 0.2 0.4 1.9 0.2 ms 4.3 1.8 0.3 0.3 9.2
Board Repo: andrewpaterson/658-Computer
Board: D Flip Flop 16bit.kicad_pcb
Folder Kicad / Computer / Component Boards / D Flip Flop 16bit
Complexity 211 / 1000 (size 141, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 8, 360, 31
Triangles, simulation 343,422 in 48 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 12 MB 238 MB
STEP 56 MB 283 MB
STL 17 MB 250 MB
OBJ 35 MB 273 MB
Visual
GLB 8.5 MB 273 MB
OBJ 25 MB 276 MB

167. D Flip Flop 24bit

D Flip Flop 24bit: stages 4 and 6 take 52% to 82% of a run. Simulation, GLB takes 4.7 s. Simulation, STEP takes 6.1 s. Simulation, STL takes 4.9 s. Simulation, OBJ takes 6.9 s. Visual, GLB takes 7.4 s. Visual, OBJ takes 8.6 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.4 2.0 0.4 ms 1.6 76 ms 0.3 0.2 4.7
Simulation, STEP 0.1 0.4 1.8 0.2 ms 1.5 1.6 0.3 0.2 6.1
Simulation, STL 0.1 0.5 1.9 0.3 ms 1.5 0.1 0.4 0.3 4.9
Simulation, OBJ 0.2 0.5 2.1 0.2 ms 1.5 2.2 0.3 0.2 6.9
Visual, GLB 0.1 0.4 2.0 0.2 ms 4.1 53 ms 0.5 0.3 7.4
Visual, OBJ 0.2 0.5 2.0 0.3 ms 3.8 1.4 0.4 0.3 8.6
Board Repo: andrewpaterson/658-Computer
Board: D Flip Flop 24bit.kicad_pcb
Folder Kicad / Computer / Component Boards / D Flip Flop 24bit
Complexity 215 / 1000 (size 145, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 10, 400, 39
Triangles, simulation 463,344 in 64 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 16 MB 277 MB
STEP 75 MB 334 MB
STL 23 MB 286 MB
OBJ 47 MB 361 MB
Visual
GLB 11 MB 342 MB
OBJ 34 MB 348 MB

168. Data and Signal Buffer

Data and Signal Buffer: stages 4 and 6 take 52% to 81% of a run. Simulation, GLB takes 5.5 s. Simulation, STEP takes 6.6 s. Simulation, STL takes 5.2 s. Simulation, OBJ takes 7.2 s. Visual, GLB takes 8.3 s. Visual, OBJ takes 9.8 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.6 2.2 0.3 ms 1.9 97 ms 0.3 0.2 5.5
Simulation, STEP 0.2 0.5 1.9 0.3 ms 1.8 1.7 0.3 0.2 6.6
Simulation, STL 0.2 0.5 2.1 0.4 ms 1.8 0.1 0.3 0.2 5.2
Simulation, OBJ 0.2 0.5 2.0 0.5 ms 1.8 2.3 0.3 0.2 7.2
Visual, GLB 0.2 0.6 2.1 0.4 ms 4.5 73 ms 0.4 0.3 8.3
Visual, OBJ 0.2 0.5 2.2 0.3 ms 4.5 1.7 0.4 0.2 9.8
Board Repo: andrewpaterson/658-Computer
Board: Data and Signal Buffer.kicad_pcb
Folder Kicad / Computer / Component Boards / Data and Signal Buffer
Complexity 229 / 1000 (size 159, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 20, 584, 75
Triangles, simulation 478,376 in 64 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 17 MB 288 MB
STEP 78 MB 345 MB
STL 24 MB 286 MB
OBJ 49 MB 378 MB
Visual
GLB 13 MB 365 MB
OBJ 38 MB 363 MB

169. Device Buffer

Device Buffer: stages 4 and 6 take 52% to 83% of a run. Simulation, GLB takes 6.1 s. Simulation, STEP takes 7.9 s. Simulation, STL takes 5.9 s. Simulation, OBJ takes 9.1 s. Visual, GLB takes 9.2 s. Visual, OBJ takes 11 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.5 2.7 0.6 ms 2.0 85 ms 0.3 0.2 6.1
Simulation, STEP 0.2 0.6 2.7 0.2 ms 2.0 1.9 0.3 0.2 7.9
Simulation, STL 0.2 0.6 2.7 0.3 ms 1.9 0.1 0.3 0.2 5.9
Simulation, OBJ 0.2 0.6 2.7 0.3 ms 2.1 3.1 0.3 0.2 9.1
Visual, GLB 0.2 0.6 2.8 0.4 ms 4.8 60 ms 0.5 0.2 9.2
Visual, OBJ 0.2 0.5 2.8 0.3 ms 4.5 2.2 0.7 0.2 11.2
Board Repo: andrewpaterson/658-Computer
Board: Device Buffer.kicad_pcb
Folder Kicad / Computer / Component Boards / Device Buffer
Complexity 226 / 1000 (size 156, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 18, 571, 40
Triangles, simulation 557,548 in 75 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 19 MB 316 MB
STEP 98 MB 367 MB
STL 28 MB 310 MB
OBJ 57 MB 420 MB
Visual
GLB 14 MB 412 MB
OBJ 41 MB 380 MB

170. Device Decode stage A

Device Decode stage A: stages 4 and 6 take 49% to 81% of a run. Simulation, GLB takes 4.0 s. Simulation, STEP takes 5.4 s. Simulation, STL takes 4.0 s. Simulation, OBJ takes 6.0 s. Visual, GLB takes 5.8 s. Visual, OBJ takes 7.6 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.3 1.7 0.3 ms 1.4 80 ms 0.3 0.2 4.0
Simulation, STEP 0.1 0.4 1.6 0.2 ms 1.5 1.4 0.2 0.2 5.4
Simulation, STL 0.1 0.4 1.6 0.2 ms 1.4 0.1 0.2 0.2 4.0
Simulation, OBJ 0.2 0.4 1.5 0.2 ms 1.4 2.0 0.2 0.2 6.0
Visual, GLB 0.1 0.4 1.7 0.3 ms 3.0 46 ms 0.3 0.2 5.8
Visual, OBJ 0.1 0.4 1.6 0.2 ms 3.3 1.6 0.4 0.2 7.6
Board Repo: andrewpaterson/658-Computer
Board: Device Decode stage A.kicad_pcb
Folder Kicad / Computer / Component Boards / Device Decode stage A
Complexity 223 / 1000 (size 153, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 16, 442, 62
Triangles, simulation 391,752 in 57 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 14 MB 259 MB
STEP 63 MB 313 MB
STL 20 MB 260 MB
OBJ 40 MB 317 MB
Visual
GLB 11 MB 317 MB
OBJ 31 MB 326 MB

171. Device Decode stage B

Device Decode stage B: stages 4 and 6 take 50% to 82% of a run. Simulation, GLB takes 4.7 s. Simulation, STEP takes 6.1 s. Simulation, STL takes 4.6 s. Simulation, OBJ takes 7.2 s. Visual, GLB takes 6.9 s. Visual, OBJ takes 9.1 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.4 1.9 0.2 ms 1.6 93 ms 0.3 0.2 4.7
Simulation, STEP 0.1 0.4 1.9 0.2 ms 1.7 1.5 0.3 0.2 6.1
Simulation, STL 0.2 0.5 1.8 0.2 ms 1.7 95 ms 0.2 0.2 4.6
Simulation, OBJ 0.1 0.4 1.9 0.2 ms 1.7 2.5 0.3 0.2 7.2
Visual, GLB 0.2 0.4 2.0 0.2 ms 3.7 56 ms 0.4 0.2 6.9
Visual, OBJ 0.2 0.4 2.0 0.2 ms 3.9 1.9 0.4 0.3 9.1
Board Repo: andrewpaterson/658-Computer
Board: Device Decode stage B.kicad_pcb
Folder Kicad / Computer / Component Boards / Device Decode stage B
Complexity 227 / 1000 (size 157, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 16, 572, 78
Triangles, simulation 451,576 in 50 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 16 MB 318 MB
STEP 75 MB 334 MB
STL 23 MB 289 MB
OBJ 46 MB 311 MB
Visual
GLB 13 MB 358 MB
OBJ 37 MB 359 MB

172. Dual Comparator 8bit

Dual Comparator 8bit: stages 4 and 6 take 51% to 83% of a run. Simulation, GLB takes 5.7 s. Simulation, STEP takes 7.2 s. Simulation, STL takes 5.5 s. Simulation, OBJ takes 8.0 s. Visual, GLB takes 8.3 s. Visual, OBJ takes 11 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.5 2.3 0.3 ms 2.0 83 ms 0.3 0.3 5.7
Simulation, STEP 0.2 0.5 2.0 0.3 ms 2.2 1.7 0.3 0.2 7.2
Simulation, STL 0.2 0.5 2.1 0.4 ms 1.9 0.2 0.4 0.2 5.5
Simulation, OBJ 0.1 0.5 2.1 0.2 ms 2.0 2.6 0.3 0.2 8.0
Visual, GLB 0.2 0.5 2.2 0.3 ms 4.7 65 ms 0.5 0.2 8.3
Visual, OBJ 0.2 0.5 2.2 0.3 ms 4.7 2.4 0.4 0.2 10.7
Board Repo: andrewpaterson/658-Computer
Board: Dual Comparator 8bit.kicad_pcb
Folder Kicad / Computer / Component Boards / Dual Comparator 8bit
Complexity 227 / 1000 (size 157, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 11, 728, 91
Triangles, simulation 503,120 in 64 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 17 MB 323 MB
STEP 80 MB 354 MB
STL 25 MB 291 MB
OBJ 51 MB 389 MB
Visual
GLB 13 MB 363 MB
OBJ 40 MB 370 MB

173. Flags Enable Interrupt

Flags Enable Interrupt: stages 4 and 6 take 53% to 83% of a run. Simulation, GLB takes 5.3 s. Simulation, STEP takes 7.2 s. Simulation, STL takes 5.7 s. Simulation, OBJ takes 8.3 s. Visual, GLB takes 8.3 s. Visual, OBJ takes 9.7 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.5 2.3 0.5 ms 1.8 96 ms 0.3 0.3 5.3
Simulation, STEP 0.2 0.5 2.1 0.4 ms 2.0 1.9 0.4 0.2 7.2
Simulation, STL 0.2 0.5 2.4 0.6 ms 1.9 0.2 0.3 0.3 5.7
Simulation, OBJ 0.2 0.5 2.2 0.3 ms 2.2 2.7 0.3 0.2 8.3
Visual, GLB 0.1 0.5 2.1 0.3 ms 4.7 70 ms 0.5 0.2 8.3
Visual, OBJ 0.2 0.5 2.0 0.3 ms 4.4 1.9 0.4 0.2 9.7
Board Repo: andrewpaterson/658-Computer
Board: Flags Enable Interrupt.kicad_pcb
Folder Kicad / Computer / Component Boards / Flags Enable Interrupt
Complexity 230 / 1000 (size 160, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 17, 674, 88
Triangles, simulation 478,496 in 56 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 17 MB 317 MB
STEP 80 MB 353 MB
STL 24 MB 319 MB
OBJ 49 MB 376 MB
Visual
GLB 13 MB 379 MB
OBJ 40 MB 370 MB

174. GPIO 16bit

GPIO 16bit: stages 4 and 6 take 57% to 81% of a run. Simulation, GLB takes 12 s. Simulation, STEP takes 15 s. Simulation, STL takes 11 s. Simulation, OBJ takes 16 s. Visual, GLB takes 19 s. Visual, OBJ takes 21 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.3 1.1 4.7 0.3 ms 4.8 0.2 0.6 0.2 11.8
Simulation, STEP 0.3 1.1 4.8 0.3 ms 4.3 3.3 0.5 0.2 14.6
Simulation, STL 0.3 1.2 4.5 0.3 ms 4.4 0.3 0.5 0.2 11.4
Simulation, OBJ 0.3 1.1 4.6 0.8 ms 4.2 4.7 0.5 0.2 15.6
Visual, GLB 0.3 1.1 4.5 0.3 ms 10.5 0.1 1.8 0.2 18.6
Visual, OBJ 0.3 1.1 4.7 0.4 ms 9.0 4.3 1.2 0.2 20.8
Board Repo: andrewpaterson/658-Computer
Board: GPIO 16bit.kicad_pcb
Folder Kicad / Computer / Component Boards / GPIO 16bit
Complexity 268 / 1000 (size 188, features 80)
KESE features through vias, rounded,
trapezoid or chamfered pads,
curved board outline,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 10 (20260206)
Parts, tracks, vias 43, 2,026, 281
Triangles, simulation 1,188,690 in 130 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 41 MB 528 MB
STEP 200 MB 651 MB
STL 59 MB 514 MB
OBJ 122 MB 810 MB
Visual
GLB 37 MB 831 MB
OBJ 111 MB 845 MB

175. GPIO 4bit

GPIO 4bit: stages 4 and 6 take 52% to 82% of a run. Simulation, GLB takes 4.8 s. Simulation, STEP takes 5.9 s. Simulation, STL takes 4.4 s. Simulation, OBJ takes 6.5 s. Visual, GLB takes 7.0 s. Visual, OBJ takes 8.5 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.4 1.8 0.3 ms 1.8 69 ms 0.3 0.2 4.8
Simulation, STEP 0.1 0.4 1.9 0.3 ms 1.5 1.4 0.3 0.2 5.9
Simulation, STL 0.1 0.4 1.7 0.3 ms 1.6 0.1 0.2 0.2 4.4
Simulation, OBJ 0.2 0.4 1.7 0.2 ms 1.7 2.1 0.3 0.3 6.5
Visual, GLB 0.1 0.4 1.8 0.2 ms 4.0 58 ms 0.4 0.2 7.0
Visual, OBJ 0.1 0.4 1.7 0.3 ms 4.0 1.6 0.4 0.3 8.5
Board Repo: andrewpaterson/658-Computer
Board: GPIO 4bit.kicad_pcb
Folder Kicad / Computer / Component Boards / GPIO 4bit
Complexity 225 / 1000 (size 155, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 14, 560, 67
Triangles, simulation 412,782 in 54 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 14 MB 272 MB
STEP 68 MB 320 MB
STL 21 MB 265 MB
OBJ 42 MB 330 MB
Visual
GLB 11 MB 330 MB
OBJ 33 MB 336 MB

176. Main Address Buffer

Main Address Buffer: stages 4 and 6 take 52% to 83% of a run. Simulation, GLB takes 4.5 s. Simulation, STEP takes 5.9 s. Simulation, STL takes 4.6 s. Simulation, OBJ takes 6.4 s. Visual, GLB takes 6.6 s. Visual, OBJ takes 8.8 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.4 2.0 0.5 ms 1.4 73 ms 0.3 0.2 4.5
Simulation, STEP 0.1 0.4 2.1 0.3 ms 1.4 1.4 0.3 0.3 5.9
Simulation, STL 0.1 0.4 2.0 0.2 ms 1.4 0.1 0.3 0.3 4.6
Simulation, OBJ 0.1 0.4 1.9 0.3 ms 1.4 2.1 0.3 0.2 6.4
Visual, GLB 0.2 0.4 2.0 0.3 ms 3.5 44 ms 0.3 0.2 6.6
Visual, OBJ 0.2 0.5 2.1 0.6 ms 3.9 1.7 0.3 0.3 8.8
Board Repo: andrewpaterson/658-Computer
Board: Main Address Buffer.kicad_pcb
Folder Kicad / Computer / Component Boards / Main Address Buffer
Complexity 209 / 1000 (size 139, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 10, 290, 20
Triangles, simulation 411,660 in 64 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 14 MB 268 MB
STEP 67 MB 308 MB
STL 21 MB 268 MB
OBJ 42 MB 326 MB
Visual
GLB 9.8 MB 318 MB
OBJ 29 MB 317 MB

177. Main Data Buffer

Main Data Buffer: stages 4 and 6 take 45% to 81% of a run. Simulation, GLB takes 3.0 s. Simulation, STEP takes 4.2 s. Simulation, STL takes 2.9 s. Simulation, OBJ takes 4.3 s. Visual, GLB takes 4.5 s. Visual, OBJ takes 5.5 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 94 ms 0.2 1.2 0.3 ms 1.0 43 ms 0.2 0.2 3.0
Simulation, STEP 0.1 0.3 1.3 0.3 ms 1.0 1.1 0.1 0.3 4.2
Simulation, STL 0.1 0.2 1.1 0.2 ms 1.0 55 ms 0.1 0.2 2.9
Simulation, OBJ 0.1 0.3 1.0 0.3 ms 0.9 1.5 0.2 0.3 4.3
Visual, GLB 93 ms 0.3 1.2 0.2 ms 2.5 25 ms 0.2 0.2 4.5
Visual, OBJ 0.1 0.3 1.1 0.2 ms 2.5 0.9 0.3 0.3 5.5
Board Repo: andrewpaterson/658-Computer
Board: Main Data Buffer.kicad_pcb
Folder Kicad / Computer / Component Boards / Main Data Buffer
Complexity 198 / 1000 (size 128, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 8, 155, 19
Triangles, simulation 251,780 in 40 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 8.7 MB 222 MB
STEP 38 MB 246 MB
STL 13 MB 247 MB
OBJ 25 MB 234 MB
Visual
GLB 6.1 MB 218 MB
OBJ 18 MB 219 MB

178. Memory 32KB with Output

Memory 32KB with Output: stages 4 and 6 take 49% to 82% of a run. Simulation, GLB takes 4.8 s. Simulation, STEP takes 6.1 s. Simulation, STL takes 4.9 s. Simulation, OBJ takes 7.1 s. Visual, GLB takes 6.9 s. Visual, OBJ takes 8.6 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.5 1.8 0.3 ms 1.7 85 ms 0.3 0.2 4.8
Simulation, STEP 0.1 0.4 1.9 0.4 ms 1.6 1.6 0.3 0.2 6.1
Simulation, STL 0.1 0.5 1.9 0.2 ms 1.8 0.2 0.3 0.2 4.9
Simulation, OBJ 0.1 0.5 1.8 0.2 ms 1.7 2.5 0.3 0.2 7.1
Visual, GLB 0.1 0.4 1.8 0.4 ms 3.9 52 ms 0.4 0.2 6.9
Visual, OBJ 0.2 0.5 1.9 0.3 ms 3.7 1.7 0.4 0.2 8.6
Board Repo: andrewpaterson/658-Computer
Board: Memory 32KB with Output.kicad_pcb
Folder Kicad / Computer / Component Boards / Memory 32KB with Output
Complexity 220 / 1000 (size 150, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 10, 502, 62
Triangles, simulation 431,984 in 59 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 15 MB 279 MB
STEP 70 MB 326 MB
STL 22 MB 277 MB
OBJ 44 MB 347 MB
Visual
GLB 11 MB 336 MB
OBJ 34 MB 341 MB

179. Register 24bit with IO

Register 24bit with IO: stages 4 and 6 take 51% to 84% of a run. Simulation, GLB takes 7.1 s. Simulation, STEP takes 9.8 s. Simulation, STL takes 7.4 s. Simulation, OBJ takes 10 s. Visual, GLB takes 11 s. Visual, OBJ takes 13 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.6 2.9 0.2 ms 2.6 0.1 0.5 0.2 7.1
Simulation, STEP 0.3 0.7 3.2 0.3 ms 2.7 2.2 0.4 0.2 9.8
Simulation, STL 0.2 0.7 3.0 0.2 ms 2.7 0.2 0.4 0.2 7.4
Simulation, OBJ 0.2 0.6 2.8 0.3 ms 2.4 3.7 0.4 0.2 10.3
Visual, GLB 0.2 0.6 2.7 0.3 ms 6.1 86 ms 0.6 0.2 10.5
Visual, OBJ 0.2 0.6 2.9 0.2 ms 5.9 2.8 0.8 0.2 13.4
Board Repo: andrewpaterson/658-Computer
Board: Register 24bit with IO.kicad_pcb
Folder Kicad / Computer / Component Boards / Register 24bit with IO
Complexity 235 / 1000 (size 165, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 18, 903, 99
Triangles, simulation 668,102 in 67 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 23 MB 349 MB
STEP 113 MB 426 MB
STL 33 MB 342 MB
OBJ 68 MB 484 MB
Visual
GLB 18 MB 497 MB
OBJ 54 MB 503 MB

180. Register 8bit with IO

Register 8bit with IO: stages 4 and 6 take 52% to 81% of a run. Simulation, GLB takes 3.5 s. Simulation, STEP takes 5.0 s. Simulation, STL takes 3.7 s. Simulation, OBJ takes 5.6 s. Visual, GLB takes 5.6 s. Visual, OBJ takes 5.8 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.3 1.3 0.2 ms 1.2 59 ms 0.2 0.2 3.5
Simulation, STEP 0.1 0.3 1.2 0.2 ms 1.4 1.4 0.2 0.3 5.0
Simulation, STL 0.2 0.3 1.3 0.3 ms 1.4 0.1 0.2 0.3 3.7
Simulation, OBJ 0.2 0.3 1.6 0.1 ms 1.3 1.7 0.2 0.2 5.6
Visual, GLB 0.1 0.3 1.2 0.3 ms 3.3 38 ms 0.3 0.3 5.6
Visual, OBJ 0.1 0.3 1.1 0.2 ms 2.8 0.9 0.2 0.3 5.8
Board Repo: andrewpaterson/658-Computer
Board: Register 8bit with IO.kicad_pcb
Folder Kicad / Computer / Component Boards / Register 8bit with IO
Complexity 210 / 1000 (size 140, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 10, 289, 30
Triangles, simulation 290,342 in 42 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 10 MB 241 MB
STEP 46 MB 265 MB
STL 15 MB 228 MB
OBJ 29 MB 251 MB
Visual
GLB 7.3 MB 251 MB
OBJ 21 MB 249 MB

181. Selector 1-of-4 4bit with Input

Stages 4 and 6 take 50% to 82% of a run. Simulation, GLB takes 3.6 s. Simulation, STEP takes 4.9 s. Simulation, STL takes 3.6 s. Simulation, OBJ takes 5.2 s. Visual, GLB takes 5.3 s. Visual, OBJ takes 6.4 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.3 1.4 0.3 ms 1.2 55 ms 0.2 0.2 3.6
Simulation, STEP 0.1 0.4 1.4 0.4 ms 1.2 1.3 0.2 0.2 4.9
Simulation, STL 0.1 0.3 1.4 0.3 ms 1.2 89 ms 0.2 0.3 3.6
Simulation, OBJ 0.1 0.3 1.4 0.3 ms 1.2 1.7 0.2 0.2 5.2
Visual, GLB 0.1 0.3 1.4 0.3 ms 3.0 39 ms 0.3 0.2 5.3
Visual, OBJ 0.1 0.3 1.4 0.2 ms 2.8 1.3 0.3 0.2 6.4
Board Repo: andrewpaterson/658-Computer
Board: Selector 1-of-4 4bit with Input.kicad_pcb
Folder Kicad / Computer / Component Boards / Selector 1-of-4 4bit with Input
Complexity 210 / 1000 (size 140, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 7, 321, 49
Triangles, simulation 367,886 in 54 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 13 MB 273 MB
STEP 56 MB 289 MB
STL 18 MB 270 MB
OBJ 37 MB 282 MB
Visual
GLB 9.0 MB 283 MB
OBJ 27 MB 290 MB

182. Selector 1-of-4 4bit

Selector 1-of-4 4bit: stages 4 and 6 take 49% to 79% of a run. Simulation, GLB takes 3.8 s. Simulation, STEP takes 4.8 s. Simulation, STL takes 3.3 s. Simulation, OBJ takes 4.7 s. Visual, GLB takes 4.9 s. Visual, OBJ takes 6.1 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.3 1.5 0.2 ms 1.3 78 ms 0.2 0.3 3.8
Simulation, STEP 0.1 0.3 1.2 0.4 ms 1.3 1.4 0.2 0.3 4.8
Simulation, STL 0.1 0.3 1.2 0.2 ms 1.2 67 ms 0.2 0.2 3.3
Simulation, OBJ 0.1 0.3 1.1 0.2 ms 1.2 1.6 0.2 0.2 4.7
Visual, GLB 0.1 0.3 1.2 0.2 ms 2.7 48 ms 0.3 0.3 4.9
Visual, OBJ 0.1 0.3 1.3 0.2 ms 2.7 1.1 0.2 0.3 6.1
Board Repo: andrewpaterson/658-Computer
Board: Selector 1-of-4 4bit.kicad_pcb
Folder Kicad / Computer / Component Boards / Selector 1-of-4 4bit
Complexity 202 / 1000 (size 132, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 5, 253, 30
Triangles, simulation 267,396 in 38 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 9.2 MB 226 MB
STEP 41 MB 251 MB
STL 13 MB 227 MB
OBJ 27 MB 237 MB
Visual
GLB 6.4 MB 223 MB
OBJ 19 MB 222 MB

183. Selector 12bit

Selector 12bit: stages 4 and 6 take 50% to 83% of a run. Simulation, GLB takes 5.8 s. Simulation, STEP takes 7.2 s. Simulation, STL takes 6.2 s. Simulation, OBJ takes 8.3 s. Visual, GLB takes 8.5 s. Visual, OBJ takes 11 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.6 2.3 0.4 ms 2.1 0.1 0.3 0.2 5.8
Simulation, STEP 0.2 0.5 2.2 0.3 ms 1.9 1.8 0.3 0.3 7.2
Simulation, STL 0.2 0.5 2.7 0.3 ms 2.0 0.2 0.4 0.2 6.2
Simulation, OBJ 0.2 0.5 2.2 0.5 ms 1.9 2.9 0.3 0.3 8.3
Visual, GLB 0.2 0.5 2.3 0.5 ms 4.8 75 ms 0.5 0.2 8.5
Visual, OBJ 0.2 0.5 2.4 0.3 ms 4.6 2.5 0.6 0.2 11.0
Board Repo: andrewpaterson/658-Computer
Board: Selector 12bit.kicad_pcb
Folder Kicad / Computer / Component Boards / Selector 12bit
Complexity 221 / 1000 (size 151, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 10, 499, 83
Triangles, simulation 474,738 in 52 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 16 MB 281 MB
STEP 75 MB 343 MB
STL 24 MB 283 MB
OBJ 48 MB 369 MB
Visual
GLB 12 MB 356 MB
OBJ 37 MB 356 MB

184. Selector 18bit

Selector 18bit: stages 4 and 6 take 52% to 84% of a run. Simulation, GLB takes 7.1 s. Simulation, STEP takes 8.5 s. Simulation, STL takes 7.0 s. Simulation, OBJ takes 10 s. Visual, GLB takes 11 s. Visual, OBJ takes 14 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.6 2.8 0.3 ms 2.6 0.1 0.5 0.3 7.1
Simulation, STEP 0.2 0.7 2.6 0.3 ms 2.3 2.0 0.4 0.2 8.5
Simulation, STL 0.2 0.6 2.8 0.3 ms 2.7 0.2 0.4 0.2 7.0
Simulation, OBJ 0.2 0.5 2.6 0.7 ms 2.6 3.6 0.4 0.2 10.2
Visual, GLB 0.2 0.6 2.9 0.3 ms 6.0 87 ms 0.7 0.2 10.6
Visual, OBJ 0.2 0.6 2.7 0.6 ms 6.1 2.9 1.1 0.2 13.8
Board Repo: andrewpaterson/658-Computer
Board: Selector 18bit.kicad_pcb
Folder Kicad / Computer / Component Boards / Selector 18bit
Complexity 232 / 1000 (size 162, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 14, 849, 115
Triangles, simulation 720,584 in 74 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 25 MB 390 MB
STEP 119 MB 444 MB
STL 36 MB 402 MB
OBJ 74 MB 530 MB
Visual
GLB 18 MB 439 MB
OBJ 55 MB 484 MB

185. State Reader 16bit

State Reader 16bit: stages 4 and 6 take 51% to 80% of a run. Simulation, GLB takes 3.6 s. Simulation, STEP takes 4.6 s. Simulation, STL takes 3.8 s. Simulation, OBJ takes 5.1 s. Visual, GLB takes 5.5 s. Visual, OBJ takes 6.7 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.3 1.4 0.3 ms 1.3 50 ms 0.2 0.2 3.6
Simulation, STEP 0.1 0.3 1.4 0.1 ms 1.1 1.3 0.2 0.2 4.6
Simulation, STL 0.2 0.3 1.5 0.2 ms 1.3 91 ms 0.2 0.2 3.8
Simulation, OBJ 0.2 0.3 1.5 0.2 ms 1.2 1.6 0.2 0.2 5.1
Visual, GLB 0.1 0.3 1.5 0.2 ms 3.0 39 ms 0.4 0.3 5.5
Visual, OBJ 0.1 0.3 1.5 0.2 ms 3.0 1.3 0.3 0.2 6.7
Board Repo: andrewpaterson/658-Computer
Board: State Reader 16bit.kicad_pcb
Folder Kicad / Computer / Component Boards / State Reader 16bit
Complexity 212 / 1000 (size 142, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 10, 350, 26
Triangles, simulation 298,626 in 42 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 10 MB 236 MB
STEP 50 MB 270 MB
STL 15 MB 230 MB
OBJ 30 MB 235 MB
Visual
GLB 7.7 MB 255 MB
OBJ 22 MB 256 MB

186. State Reader 8bit

State Reader 8bit: stages 4 and 6 take 50% to 77% of a run. Simulation, GLB takes 2.2 s. Simulation, STEP takes 3.0 s. Simulation, STL takes 2.2 s. Simulation, OBJ takes 2.9 s. Visual, GLB takes 3.3 s. Visual, OBJ takes 3.6 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.2 0.8 0.2 ms 0.8 30 ms 0.1 0.2 2.2
Simulation, STEP 94 ms 0.2 0.7 0.2 ms 0.8 0.9 98 ms 0.2 3.0
Simulation, STL 85 ms 0.2 0.8 0.2 ms 0.8 49 ms 0.1 0.2 2.2
Simulation, OBJ 0.1 0.2 0.8 0.3 ms 0.8 0.8 96 ms 0.2 2.9
Visual, GLB 0.1 0.2 0.8 0.2 ms 1.8 24 ms 0.2 0.2 3.3
Visual, OBJ 0.1 0.2 0.8 0.2 ms 1.6 0.6 0.1 0.2 3.6
Board Repo: andrewpaterson/658-Computer
Board: State Reader 8bit.kicad_pcb
Folder Kicad / Computer / Component Boards / State Reader 8bit
Complexity 196 / 1000 (size 126, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 8, 147, 11
Triangles, simulation 187,430 in 35 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 6.5 MB 203 MB
STEP 30 MB 220 MB
STL 9.4 MB 205 MB
OBJ 19 MB 199 MB
Visual
GLB 4.5 MB 193 MB
OBJ 13 MB 195 MB

187. Coprocessor Board - Additional

Stages 4 and 6 take 52% to 86% of a run. Simulation, GLB takes 36 s. Simulation, STEP takes 45 s. Simulation, STL takes 36 s. Simulation, OBJ takes 56 s. Visual, GLB takes 53 s. Visual, OBJ takes 66 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.5 3.3 17.1 0.8 ms 12.0 0.6 1.8 0.3 35.8
Simulation, STEP 0.5 3.2 17.1 0.8 ms 12.0 9.9 2.0 0.3 44.8
Simulation, STL 0.5 3.3 17.0 0.8 ms 12.0 1.2 1.9 0.3 36.2
Simulation, OBJ 0.5 3.3 17.3 3 ms 11.8 21.0 1.9 0.3 56.1
Visual, GLB 0.6 3.2 17.2 0.7 ms 28.4 0.4 2.8 0.3 52.8
Visual, OBJ 0.5 3.4 16.7 0.8 ms 28.5 13.3 3.0 0.3 65.6
Board Repo: andrewpaterson/658-Computer
Board: Coprocessor Board - Additional.kicad_pcb
Folder Kicad / Computer / Coprocessor / Coprocessor Board - Additional
Complexity 264 / 1000 (size 184, features 80)
KESE features through vias, rounded,
trapezoid or chamfered pads,
curved board outline,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 27, 2,198, 268
Triangles, simulation 3,637,522 in 233 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 124 MB 1.3 GB
STEP 583 MB 1.4 GB
STL 182 MB 1.3 GB
OBJ 388 MB 2.3 GB
Visual
GLB 79 MB 1.5 GB
OBJ 249 MB 1.8 GB

188. Coprocessor Board - Main

Coprocessor Board - Main: stages 4 and 6 take 55% to 85% of a run. Simulation, GLB takes 51 s. Simulation, STEP takes 63 s. Simulation, STL takes 53 s. Simulation, OBJ takes 74 s. Visual, GLB takes 96 s. Visual, OBJ takes 2 min

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.6 4.6 24.1 2 ms 18.2 0.8 2.5 0.3 51.2
Simulation, STEP 0.6 4.5 24.5 2 ms 18.3 12.3 2.6 0.3 62.9
Simulation, STL 0.6 4.8 24.0 2 ms 18.4 2.2 2.4 0.3 52.7
Simulation, OBJ 0.6 4.6 22.4 2 ms 18.6 24.8 2.7 0.3 74.0
Visual, GLB 0.7 5.2 24.2 2 ms 58.0 0.7 7.2 0.3 96.4
Visual, OBJ 0.6 5.3 24.0 1 ms 60.3 17.5 6.4 0.3 114.4
Board Repo: andrewpaterson/658-Computer
Board: Coprocessor Board - Main.kicad_pcb
Folder Kicad / Computer / Coprocessor / Coprocessor Board - Main
Complexity 279 / 1000 (size 199, features 80)
KESE features through vias, rounded,
trapezoid or chamfered pads,
curved board outline,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 42, 3,940, 516
Triangles, simulation 5,772,242 in 394 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 194 MB 1.8 GB
STEP 831 MB 2.2 GB
STL 289 MB 1.7 GB
OBJ 610 MB 3.6 GB
Visual
GLB 132 MB 2.1 GB
OBJ 425 MB 2.7 GB

189. Coprocessor Clock

Coprocessor Clock: stages 4 and 6 take 49% to 79% of a run. Simulation, GLB takes 2.6 s. Simulation, STEP takes 3.6 s. Simulation, STL takes 2.6 s. Simulation, OBJ takes 3.5 s. Visual, GLB takes 3.6 s. Visual, OBJ takes 4.3 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.2 0.9 0.2 ms 0.9 35 ms 0.1 0.3 2.6
Simulation, STEP 0.1 0.2 0.9 0.2 ms 0.9 1.1 0.1 0.2 3.6
Simulation, STL 0.1 0.2 0.9 0.2 ms 0.9 57 ms 0.1 0.2 2.6
Simulation, OBJ 0.1 0.2 0.9 0.2 ms 0.8 1.2 0.1 0.2 3.5
Visual, GLB 0.1 0.2 0.9 0.2 ms 2.0 32 ms 0.2 0.2 3.6
Visual, OBJ 0.1 0.2 0.9 0.2 ms 1.9 0.8 0.2 0.2 4.3
Board Repo: andrewpaterson/658-Computer
Board: Coprocessor Clock.kicad_pcb
Folder Kicad / Computer / Coprocessor / Coprocessor Clock
Complexity 202 / 1000 (size 132, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 12, 170, 12
Triangles, simulation 199,224 in 41 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 6.9 MB 207 MB
STEP 30 MB 230 MB
STL 10.0 MB 206 MB
OBJ 20 MB 209 MB
Visual
GLB 4.9 MB 200 MB
OBJ 14 MB 204 MB

190. Coprocessor Memory Select

Coprocessor Memory Select: stages 4 and 6 take 52% to 80% of a run. Simulation, GLB takes 3.2 s. Simulation, STEP takes 4.4 s. Simulation, STL takes 3.3 s. Simulation, OBJ takes 4.7 s. Visual, GLB takes 5.4 s. Visual, OBJ takes 6.5 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.3 1.2 0.3 ms 1.1 51 ms 0.2 0.2 3.2
Simulation, STEP 0.1 0.3 1.2 0.3 ms 1.2 1.2 0.2 0.2 4.4
Simulation, STL 0.1 0.3 1.2 0.2 ms 1.2 87 ms 0.2 0.2 3.3
Simulation, OBJ 0.1 0.3 1.2 0.5 ms 1.2 1.4 0.2 0.2 4.7
Visual, GLB 0.1 0.3 1.3 0.2 ms 3.0 37 ms 0.3 0.3 5.4
Visual, OBJ 0.1 0.4 1.4 0.2 ms 3.1 1.1 0.3 0.2 6.5
Board Repo: andrewpaterson/658-Computer
Board: Coprocessor Memory Select.kicad_pcb
Folder Kicad / Computer / Coprocessor / Coprocessor Memory Select
Complexity 217 / 1000 (size 147, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 16, 304, 44
Triangles, simulation 348,694 in 53 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 12 MB 284 MB
STEP 52 MB 288 MB
STL 17 MB 278 MB
OBJ 35 MB 272 MB
Visual
GLB 9.4 MB 296 MB
OBJ 28 MB 292 MB

191. Coprocessor Support

Coprocessor Support: stages 4 and 6 take 52% to 81% of a run. Simulation, GLB takes 3.6 s. Simulation, STEP takes 4.9 s. Simulation, STL takes 3.7 s. Simulation, OBJ takes 5.4 s. Visual, GLB takes 5.6 s. Visual, OBJ takes 6.9 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.3 1.3 0.3 ms 1.3 63 ms 0.2 0.2 3.6
Simulation, STEP 0.1 0.3 1.4 0.4 ms 1.4 1.3 0.2 0.2 4.9
Simulation, STL 0.1 0.3 1.3 0.2 ms 1.4 91 ms 0.2 0.2 3.7
Simulation, OBJ 0.1 0.4 1.5 0.3 ms 1.3 1.7 0.2 0.2 5.4
Visual, GLB 0.1 0.3 1.4 0.2 ms 3.1 57 ms 0.4 0.2 5.6
Visual, OBJ 0.1 0.4 1.3 0.2 ms 3.1 1.5 0.4 0.2 6.9
Board Repo: andrewpaterson/658-Computer
Board: Coprocessor Support.kicad_pcb
Folder Kicad / Computer / Coprocessor / Coprocessor Support
Complexity 225 / 1000 (size 155, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 18, 447, 74
Triangles, simulation 417,018 in 65 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 14 MB 267 MB
STEP 62 MB 322 MB
STL 21 MB 267 MB
OBJ 42 MB 332 MB
Visual
GLB 11 MB 332 MB
OBJ 34 MB 324 MB

192. Coprocessor Transceiver

Coprocessor Transceiver: stages 4 and 6 take 50% to 83% of a run. Simulation, GLB takes 3.2 s. Simulation, STEP takes 4.1 s. Simulation, STL takes 3.2 s. Simulation, OBJ takes 4.6 s. Visual, GLB takes 4.8 s. Visual, OBJ takes 5.4 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.3 1.2 0.4 ms 1.2 48 ms 0.2 0.2 3.2
Simulation, STEP 0.1 0.3 1.0 0.2 ms 1.1 1.2 0.2 0.2 4.1
Simulation, STL 0.1 0.3 1.2 0.2 ms 1.1 0.1 0.2 0.2 3.2
Simulation, OBJ 0.1 0.3 1.1 0.3 ms 1.2 1.5 0.2 0.2 4.6
Visual, GLB 83 ms 0.3 1.3 0.2 ms 2.7 35 ms 0.2 0.2 4.8
Visual, OBJ 96 ms 0.3 1.1 0.3 ms 2.5 1.0 0.2 0.2 5.4
Board Repo: andrewpaterson/658-Computer
Board: Coprocessor Transceiver.kicad_pcb
Folder Kicad / Computer / Coprocessor / Coprocessor Transceiver
Complexity 208 / 1000 (size 138, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 6, 284, 52
Triangles, simulation 315,966 in 38 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 11 MB 235 MB
STEP 48 MB 273 MB
STL 16 MB 241 MB
OBJ 32 MB 265 MB
Visual
GLB 7.8 MB 254 MB
OBJ 23 MB 256 MB

193. Graphics Board

Graphics Board: stages 4 and 6 take 55% to 85% of a run. Simulation, GLB takes 47 s. Simulation, STEP takes 58 s. Simulation, STL takes 48 s. Simulation, OBJ takes 72 s. Visual, GLB takes 76 s. Visual, OBJ takes 95 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.5 4.1 21.8 2 ms 17.4 0.9 2.4 0.3 47.3
Simulation, STEP 0.6 4.2 21.5 1 ms 17.3 12.0 2.3 0.3 58.2
Simulation, STL 0.6 4.2 21.8 2 ms 17.1 1.8 2.4 0.4 48.3
Simulation, OBJ 0.6 4.3 22.0 2 ms 17.1 24.8 2.4 0.3 71.6
Visual, GLB 0.5 4.0 22.0 2 ms 43.0 0.5 6.0 0.2 76.4
Visual, OBJ 0.6 4.2 22.1 2 ms 44.3 16.5 6.7 0.2 94.6
Board Repo: andrewpaterson/658-Computer
Board: Graphics Board.kicad_pcb
Folder Kicad / Computer / Graphics / Graphics Board
Complexity 274 / 1000 (size 194, features 80)
KESE features through vias, rounded,
trapezoid or chamfered pads,
curved board outline,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 10 (20260206)
Parts, tracks, vias 28, 4,219, 433
Triangles, simulation 5,741,322 in 422 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 189 MB 1.7 GB
STEP 816 MB 2.1 GB
STL 287 MB 1.7 GB
OBJ 606 MB 3.6 GB
Visual
GLB 127 MB 2.1 GB
OBJ 409 MB 2.7 GB

194. Graphics Main Data

Graphics Main Data: stages 4 and 6 take 49% to 81% of a run. Simulation, GLB takes 2.7 s. Simulation, STEP takes 3.7 s. Simulation, STL takes 2.7 s. Simulation, OBJ takes 3.9 s. Visual, GLB takes 4.2 s. Visual, OBJ takes 4.9 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.2 1.0 0.2 ms 0.9 50 ms 0.2 0.3 2.7
Simulation, STEP 0.1 0.2 1.0 0.2 ms 0.9 1.1 0.1 0.2 3.7
Simulation, STL 99 ms 0.2 1.1 0.2 ms 0.9 65 ms 0.1 0.2 2.7
Simulation, OBJ 0.1 0.2 0.9 0.2 ms 1.0 1.3 0.2 0.2 3.9
Visual, GLB 0.1 0.2 1.1 0.2 ms 2.4 29 ms 0.2 0.2 4.2
Visual, OBJ 0.1 0.2 1.1 0.2 ms 2.3 0.8 0.2 0.2 4.9
Board Repo: andrewpaterson/658-Computer
Board: Graphics Main Data.kicad_pcb
Folder Kicad / Computer / Graphics / Graphics Main Data
Complexity 203 / 1000 (size 133, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 8, 227, 20
Triangles, simulation 254,212 in 44 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 8.7 MB 238 MB
STEP 39 MB 249 MB
STL 13 MB 229 MB
OBJ 25 MB 233 MB
Visual
GLB 6.2 MB 223 MB
OBJ 18 MB 216 MB

195. Graphics Signals

Graphics Signals: stages 4 and 6 take 50% to 81% of a run. Simulation, GLB takes 5.3 s. Simulation, STEP takes 6.7 s. Simulation, STL takes 5.0 s. Simulation, OBJ takes 7.1 s. Visual, GLB takes 7.9 s. Visual, OBJ takes 9.6 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.5 2.1 0.5 ms 1.8 83 ms 0.3 0.2 5.3
Simulation, STEP 0.2 0.5 2.0 0.4 ms 1.8 1.7 0.3 0.2 6.7
Simulation, STL 0.2 0.5 1.9 0.3 ms 1.8 0.1 0.3 0.2 5.0
Simulation, OBJ 0.1 0.4 1.9 0.3 ms 1.7 2.5 0.3 0.2 7.1
Visual, GLB 0.2 0.5 2.0 0.3 ms 4.5 74 ms 0.6 0.2 7.9
Visual, OBJ 0.2 0.5 1.9 0.2 ms 4.0 2.0 0.7 0.2 9.6
Board Repo: andrewpaterson/658-Computer
Board: Graphics Signals.kicad_pcb
Folder Kicad / Computer / Graphics / Graphics Signals
Complexity 234 / 1000 (size 164, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 28, 597, 84
Triangles, simulation 491,460 in 57 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 17 MB 320 MB
STEP 78 MB 358 MB
STL 25 MB 297 MB
OBJ 50 MB 377 MB
Visual
GLB 14 MB 381 MB
OBJ 41 MB 409 MB

196. Graphics Transparency

Graphics Transparency: stages 4 and 6 take 47% to 83% of a run. Simulation, GLB takes 5.4 s. Simulation, STEP takes 7.2 s. Simulation, STL takes 5.6 s. Simulation, OBJ takes 8.6 s. Visual, GLB takes 8.6 s. Visual, OBJ takes 11 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.6 2.1 0.2 ms 1.9 95 ms 0.3 0.3 5.4
Simulation, STEP 0.2 0.5 2.0 0.3 ms 2.0 1.9 0.4 0.2 7.2
Simulation, STL 0.2 0.6 2.2 0.7 ms 2.1 0.1 0.3 0.2 5.6
Simulation, OBJ 0.2 0.5 2.1 0.3 ms 1.9 3.3 0.3 0.2 8.6
Visual, GLB 0.2 0.6 2.3 0.5 ms 4.8 67 ms 0.4 0.2 8.6
Visual, OBJ 0.2 0.6 2.1 0.3 ms 4.6 2.3 0.5 0.2 10.5
Board Repo: andrewpaterson/658-Computer
Board: Graphics Transparency.kicad_pcb
Folder Kicad / Computer / Graphics / Graphics Transparency
Complexity 227 / 1000 (size 157, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 16, 545, 89
Triangles, simulation 469,960 in 55 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 16 MB 283 MB
STEP 73 MB 348 MB
STL 24 MB 293 MB
OBJ 47 MB 353 MB
Visual
GLB 13 MB 373 MB
OBJ 39 MB 367 MB

197. LCD Board

LCD Board: stages 4 and 6 take 54% to 85% of a run. Simulation, GLB takes 17 s. Simulation, STEP takes 21 s. Simulation, STL takes 17 s. Simulation, OBJ takes 25 s. Visual, GLB takes 26 s. Visual, OBJ takes 31 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.3 1.5 8.1 0.7 ms 5.7 0.3 0.9 0.2 16.9
Simulation, STEP 0.3 1.5 7.8 0.7 ms 5.9 4.4 0.9 0.3 21.0
Simulation, STL 0.3 1.4 7.8 0.7 ms 5.9 0.5 0.8 0.2 17.0
Simulation, OBJ 0.3 1.4 7.9 1 ms 5.7 8.8 0.8 0.2 25.2
Visual, GLB 0.3 1.5 7.9 0.7 ms 14.0 0.2 1.5 0.2 25.8
Visual, OBJ 0.3 1.5 7.8 0.6 ms 13.9 6.0 1.4 0.2 31.0
Board Repo: andrewpaterson/658-Computer
Board: LCD Board.kicad_pcb
Folder Kicad / Computer / LCD / LCD Board
Complexity 248 / 1000 (size 168, features 80)
KESE features through vias, rounded,
trapezoid or chamfered pads,
curved board outline,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 17, 1,151, 117
Triangles, simulation 1,760,916 in 194 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 59 MB 680 MB
STEP 246 MB 795 MB
STL 88 MB 628 MB
OBJ 181 MB 1.2 GB
Visual
GLB 39 MB 891 MB
OBJ 120 MB 923 MB

198. LCD Display

LCD Display: stages 4 and 6 take 53% to 82% of a run. Simulation, GLB takes 7.5 s. Simulation, STEP takes 9.2 s. Simulation, STL takes 7.4 s. Simulation, OBJ takes 11 s. Visual, GLB takes 11 s. Visual, OBJ takes 14 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.3 0.7 3.0 0.4 ms 2.7 0.1 0.4 0.3 7.5
Simulation, STEP 0.2 0.6 3.0 0.4 ms 2.4 2.3 0.4 0.2 9.2
Simulation, STL 0.3 0.6 2.9 0.4 ms 2.8 0.2 0.4 0.2 7.4
Simulation, OBJ 0.2 0.7 3.0 0.5 ms 2.8 3.5 0.4 0.2 10.9
Visual, GLB 0.2 0.7 2.8 0.4 ms 6.4 88 ms 0.7 0.2 11.2
Visual, OBJ 0.2 0.6 3.2 0.5 ms 6.2 2.8 0.8 0.2 14.0
Board Repo: andrewpaterson/658-Computer
Board: LCD Display.kicad_pcb
Folder Kicad / Computer / LCD / LCD Display
Complexity 246 / 1000 (size 166, features 80)
KESE features through vias, rounded,
trapezoid or chamfered pads,
curved board outline,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 20, 878, 107
Triangles, simulation 720,300 in 101 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 25 MB 348 MB
STEP 111 MB 442 MB
STL 36 MB 358 MB
OBJ 73 MB 527 MB
Visual
GLB 19 MB 510 MB
OBJ 57 MB 514 MB

199. Clock Device

Clock Device: stages 4 and 6 take 51% to 81% of a run. Simulation, GLB takes 4.9 s. Simulation, STEP takes 6.2 s. Simulation, STL takes 4.8 s. Simulation, OBJ takes 7.2 s. Visual, GLB takes 7.2 s. Visual, OBJ takes 9.1 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.5 2.0 0.4 ms 1.7 87 ms 0.3 0.2 4.9
Simulation, STEP 0.2 0.5 1.9 0.5 ms 1.5 1.5 0.3 0.2 6.2
Simulation, STL 0.2 0.5 1.9 0.3 ms 1.5 0.2 0.3 0.2 4.8
Simulation, OBJ 0.2 0.5 2.0 0.3 ms 1.6 2.4 0.3 0.2 7.2
Visual, GLB 0.2 0.5 2.0 0.3 ms 3.9 57 ms 0.4 0.2 7.2
Visual, OBJ 0.2 0.5 1.9 0.2 ms 3.9 2.0 0.4 0.3 9.1
Board Repo: andrewpaterson/658-Computer
Board: Clock Device.kicad_pcb
Folder Kicad / Computer / Main / Clock Device
Complexity 236 / 1000 (size 156, features 80)
KESE features through vias, rounded,
trapezoid or chamfered pads,
curved board outline,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 18, 446, 79
Triangles, simulation 474,398 in 72 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 16 MB 280 MB
STEP 73 MB 346 MB
STL 24 MB 278 MB
OBJ 48 MB 369 MB
Visual
GLB 12 MB 351 MB
OBJ 37 MB 342 MB

200. Clock LTC6903

Clock LTC6903: stages 4 and 6 take 40% to 69% of a run. Simulation, GLB takes 1.4 s. Simulation, STEP takes 2.2 s. Simulation, STL takes 1.5 s. Simulation, OBJ takes 1.7 s. Visual, GLB takes 1.4 s. Visual, OBJ takes 1.7 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.1 0.3 0.2 ms 0.5 14 ms 47 ms 0.2 1.4
Simulation, STEP 97 ms 0.1 0.3 0.1 ms 0.5 0.8 43 ms 0.2 2.2
Simulation, STL 0.1 89 ms 0.3 0.2 ms 0.6 23 ms 54 ms 0.3 1.5
Simulation, OBJ 0.1 98 ms 0.3 0.1 ms 0.5 0.3 53 ms 0.3 1.7
Visual, GLB 94 ms 85 ms 0.3 0.1 ms 0.7 8 ms 54 ms 0.2 1.4
Visual, OBJ 97 ms 77 ms 0.3 0.1 ms 0.7 0.2 53 ms 0.2 1.7
Board Repo: andrewpaterson/658-Computer
Board: Clock LTC6903.kicad_pcb
Folder Kicad / Computer / Main / Clock LTC6903
Complexity 156 / 1000 (size 86, features 70)
KESE features rounded,
trapezoid or chamfered pads,
filled zones, curved board outline,
stack-up, dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 5, 20, 0
Triangles, simulation 54,786 in 21 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 1.9 MB 70 MB
STEP 7.5 MB 174 MB
STL 2.7 MB 71 MB
OBJ 5.3 MB 82 MB
Visual
GLB 1.3 MB 103 MB
OBJ 3.7 MB 104 MB

201. Clock Oscillator

Clock Oscillator: stages 4 and 6 take 48% to 62% of a run. Simulation, GLB takes 0.9 s. Simulation, STEP takes 1.4 s. Simulation, STL takes 1.0 s. Simulation, OBJ takes 1.2 s. Visual, GLB takes 1.1 s. Visual, OBJ takes 1.5 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 82 ms 58 ms 0.2 0.1 ms 0.3 8 ms 28 ms 0.2 0.9
Simulation, STEP 0.1 68 ms 0.2 0.1 ms 0.4 0.3 36 ms 0.3 1.4
Simulation, STL 94 ms 58 ms 0.2 0.1 ms 0.4 11 ms 29 ms 0.2 1.0
Simulation, OBJ 81 ms 56 ms 0.2 0.2 ms 0.4 0.2 45 ms 0.3 1.2
Visual, GLB 82 ms 59 ms 0.2 0.1 ms 0.5 7 ms 50 ms 0.2 1.1
Visual, OBJ 77 ms 57 ms 0.2 0.1 ms 0.6 0.2 52 ms 0.3 1.5
Board Repo: andrewpaterson/658-Computer
Board: Clock Oscillator.kicad_pcb
Folder Kicad / Computer / Main / Clock Oscillator
Complexity 122 / 1000 (size 72, features 50)
KESE features rounded,
trapezoid or chamfered pads,
curved board outline, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 4, 9, 0
Triangles, simulation 39,040 in 20 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 1.4 MB 66 MB
STEP 4.9 MB 71 MB
STL 2.0 MB 68 MB
OBJ 3.7 MB 74 MB
Visual
GLB 977 kB 98 MB
OBJ 2.7 MB 98 MB

202. Clock Push Button

Clock Push Button: stages 4 and 6 take 39% to 71% of a run. Simulation, GLB takes 1.2 s. Simulation, STEP takes 2.0 s. Simulation, STL takes 1.2 s. Simulation, OBJ takes 1.5 s. Visual, GLB takes 1.7 s. Visual, OBJ takes 2.0 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 87 ms 0.3 0.1 ms 0.5 15 ms 45 ms 0.2 1.2
Simulation, STEP 0.1 87 ms 0.3 0.1 ms 0.5 0.8 43 ms 0.2 2.0
Simulation, STL 80 ms 72 ms 0.3 0.1 ms 0.4 18 ms 63 ms 0.3 1.2
Simulation, OBJ 91 ms 0.1 0.3 0.2 ms 0.5 0.3 48 ms 0.2 1.5
Visual, GLB 95 ms 80 ms 0.3 0.1 ms 0.9 10 ms 69 ms 0.2 1.7
Visual, OBJ 88 ms 84 ms 0.3 0.1 ms 1.0 0.2 71 ms 0.2 2.0
Board Repo: andrewpaterson/658-Computer
Board: Clock Push Button.kicad_pcb
Folder Kicad / Computer / Main / Clock Push Button
Complexity 159 / 1000 (size 109, features 50)
KESE features rounded,
trapezoid or chamfered pads,
curved board outline, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 7, 69, 0
Triangles, simulation 68,818 in 22 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 2.4 MB 170 MB
STEP 9.7 MB 177 MB
STL 3.4 MB 168 MB
OBJ 6.7 MB 174 MB
Visual
GLB 1.8 MB 151 MB
OBJ 5.0 MB 151 MB

203. Default Board

Default Board: stages 4 and 6 take 53% to 79% of a run. Simulation, GLB takes 7.4 s. Simulation, STEP takes 9.2 s. Simulation, STL takes 7.6 s. Simulation, OBJ takes 11 s. Visual, GLB takes 11 s. Visual, OBJ takes 13 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 1.0 3.4 0.7 ms 2.1 97 ms 0.4 0.3 7.4
Simulation, STEP 0.2 1.0 3.5 0.6 ms 2.0 2.0 0.4 0.2 9.2
Simulation, STL 0.2 1.0 3.4 0.8 ms 2.1 0.2 0.4 0.2 7.6
Simulation, OBJ 0.2 1.0 3.5 0.9 ms 2.1 3.4 0.4 0.2 10.8
Visual, GLB 0.2 1.0 3.5 1 ms 5.0 65 ms 0.7 0.2 10.8
Visual, OBJ 0.2 0.9 3.4 0.9 ms 5.1 1.9 0.7 0.2 12.5
Board Repo: andrewpaterson/658-Computer
Board: Default Board.kicad_pcb
Folder Kicad / Computer / Main / Default Board
Complexity 167 / 1000 (size 82, features 85)
KESE features rounded,
trapezoid or chamfered pads,
filled zones, curved board outline,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 10, 10, 0
Triangles, simulation 768,296 in 146 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 25 MB 349 MB
STEP 82 MB 406 MB
STL 38 MB 357 MB
OBJ 78 MB 545 MB
Visual
GLB 14 MB 433 MB
OBJ 42 MB 421 MB

204. Main Memory Channel

Main Memory Channel: stages 4 and 6 take 51% to 82% of a run. Simulation, GLB takes 5.1 s. Simulation, STEP takes 6.6 s. Simulation, STL takes 5.2 s. Simulation, OBJ takes 7.3 s. Visual, GLB takes 7.4 s. Visual, OBJ takes 9.1 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.5 2.0 0.2 ms 1.9 83 ms 0.3 0.2 5.1
Simulation, STEP 0.2 0.5 2.0 0.2 ms 1.8 1.7 0.3 0.2 6.6
Simulation, STL 0.2 0.5 2.1 1 ms 1.9 0.1 0.3 0.2 5.2
Simulation, OBJ 0.2 0.5 1.9 0.3 ms 1.8 2.4 0.3 0.2 7.3
Visual, GLB 0.2 0.5 2.1 0.2 ms 4.0 74 ms 0.4 0.2 7.4
Visual, OBJ 0.2 0.5 2.0 0.3 ms 3.8 2.0 0.4 0.2 9.1
Board Repo: andrewpaterson/658-Computer
Board: Main Memory Channel.kicad_pcb
Folder Kicad / Computer / Main / Main Memory Channel
Complexity 225 / 1000 (size 155, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 14, 541, 71
Triangles, simulation 461,016 in 65 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 16 MB 275 MB
STEP 75 MB 337 MB
STL 23 MB 289 MB
OBJ 47 MB 336 MB
Visual
GLB 12 MB 339 MB
OBJ 36 MB 348 MB

205. Main Memory Full Abort

Main Memory Full Abort: stages 4 and 6 take 51% to 83% of a run. Simulation, GLB takes 7.4 s. Simulation, STEP takes 9.4 s. Simulation, STL takes 7.2 s. Simulation, OBJ takes 11 s. Visual, GLB takes 11 s. Visual, OBJ takes 14 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.7 2.9 0.4 ms 2.7 98 ms 0.5 0.2 7.4
Simulation, STEP 0.2 0.6 3.0 0.4 ms 2.7 2.2 0.4 0.2 9.4
Simulation, STL 0.2 0.7 2.9 0.5 ms 2.6 0.2 0.4 0.2 7.2
Simulation, OBJ 0.2 0.7 2.9 0.4 ms 2.6 3.7 0.4 0.2 10.7
Visual, GLB 0.2 0.6 2.9 0.3 ms 6.0 90 ms 0.7 0.2 10.7
Visual, OBJ 0.2 0.7 2.8 0.6 ms 6.3 3.4 0.9 0.3 14.4
Board Repo: andrewpaterson/658-Computer
Board: Main Memory Full Abort.kicad_pcb
Folder Kicad / Computer / Main / Main Memory Full Abort
Complexity 254 / 1000 (size 174, features 80)
KESE features through vias, rounded,
trapezoid or chamfered pads,
curved board outline,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 31, 1,062, 127
Triangles, simulation 649,398 in 97 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 22 MB 344 MB
STEP 107 MB 436 MB
STL 32 MB 345 MB
OBJ 66 MB 488 MB
Visual
GLB 19 MB 533 MB
OBJ 58 MB 530 MB

206. Main Memory Full Enable

Main Memory Full Enable: stages 4 and 6 take 51% to 82% of a run. Simulation, GLB takes 4.9 s. Simulation, STEP takes 6.4 s. Simulation, STL takes 5.0 s. Simulation, OBJ takes 7.6 s. Visual, GLB takes 7.0 s. Visual, OBJ takes 9.3 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.5 2.0 0.3 ms 1.7 72 ms 0.3 0.2 4.9
Simulation, STEP 0.2 0.5 2.0 0.3 ms 1.7 1.6 0.2 0.2 6.4
Simulation, STL 0.2 0.5 2.0 0.3 ms 1.7 0.1 0.3 0.2 5.0
Simulation, OBJ 0.2 0.6 2.1 0.2 ms 1.8 2.4 0.3 0.3 7.6
Visual, GLB 0.2 0.5 2.0 0.3 ms 3.7 58 ms 0.4 0.2 7.0
Visual, OBJ 0.2 0.5 1.9 0.5 ms 4.0 2.0 0.4 0.3 9.3
Board Repo: andrewpaterson/658-Computer
Board: Main Memory Full Enable.kicad_pcb
Folder Kicad / Computer / Main / Main Memory Full Enable
Complexity 224 / 1000 (size 154, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 18, 405, 67
Triangles, simulation 415,572 in 54 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 14 MB 279 MB
STEP 63 MB 325 MB
STL 21 MB 275 MB
OBJ 42 MB 298 MB
Visual
GLB 12 MB 343 MB
OBJ 35 MB 348 MB

207. Main Memory Select

Main Memory Select: stages 4 and 6 take 52% to 83% of a run. Simulation, GLB takes 7.0 s. Simulation, STEP takes 10 s. Simulation, STL takes 7.2 s. Simulation, OBJ takes 10 s. Visual, GLB takes 10 s. Visual, OBJ takes 14 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.7 2.8 0.4 ms 2.6 0.1 0.4 0.3 7.0
Simulation, STEP 0.2 0.6 3.2 0.6 ms 2.9 2.5 0.4 0.3 10.1
Simulation, STL 0.2 0.6 2.7 0.3 ms 2.7 0.2 0.5 0.3 7.2
Simulation, OBJ 0.3 0.8 2.9 0.5 ms 2.5 3.4 0.4 0.2 10.4
Visual, GLB 0.2 0.6 2.8 0.6 ms 5.8 84 ms 0.7 0.2 10.4
Visual, OBJ 0.2 0.6 2.8 0.5 ms 6.1 2.7 0.8 0.3 13.5
Board Repo: andrewpaterson/658-Computer
Board: Main Memory Select.kicad_pcb
Folder Kicad / Computer / Main / Main Memory Select
Complexity 230 / 1000 (size 160, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 16, 668, 91
Triangles, simulation 588,794 in 96 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 20 MB 311 MB
STEP 89 MB 390 MB
STL 29 MB 316 MB
OBJ 60 MB 433 MB
Visual
GLB 15 MB 440 MB
OBJ 45 MB 430 MB

208. Main Memory Small Abort

Main Memory Small Abort: stages 4 and 6 take 50% to 81% of a run. Simulation, GLB takes 3.8 s. Simulation, STEP takes 5.0 s. Simulation, STL takes 3.7 s. Simulation, OBJ takes 5.8 s. Visual, GLB takes 5.7 s. Visual, OBJ takes 7.0 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.4 1.5 0.3 ms 1.3 60 ms 0.2 0.2 3.8
Simulation, STEP 0.1 0.4 1.5 0.3 ms 1.3 1.3 0.2 0.2 5.0
Simulation, STL 0.1 0.4 1.5 0.2 ms 1.3 89 ms 0.2 0.2 3.7
Simulation, OBJ 0.2 0.4 1.5 0.3 ms 1.4 2.0 0.2 0.2 5.8
Visual, GLB 0.2 0.4 1.5 0.3 ms 3.1 54 ms 0.3 0.2 5.7
Visual, OBJ 0.1 0.4 1.5 0.3 ms 3.0 1.5 0.3 0.2 7.0
Board Repo: andrewpaterson/658-Computer
Board: Main Memory Small Abort.kicad_pcb
Folder Kicad / Computer / Main / Main Memory Small Abort
Complexity 219 / 1000 (size 149, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 16, 339, 49
Triangles, simulation 348,420 in 61 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 12 MB 247 MB
STEP 51 MB 290 MB
STL 17 MB 245 MB
OBJ 35 MB 289 MB
Visual
GLB 9.3 MB 290 MB
OBJ 27 MB 292 MB

209. Main Memory Small Enable

Main Memory Small Enable: stages 4 and 6 take 48% to 81% of a run. Simulation, GLB takes 3.8 s. Simulation, STEP takes 5.2 s. Simulation, STL takes 3.7 s. Simulation, OBJ takes 5.4 s. Visual, GLB takes 5.5 s. Visual, OBJ takes 6.8 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.4 1.5 0.4 ms 1.2 54 ms 0.2 0.2 3.8
Simulation, STEP 0.2 0.4 1.6 0.3 ms 1.3 1.4 0.2 0.2 5.2
Simulation, STL 0.1 0.3 1.5 0.2 ms 1.2 76 ms 0.2 0.2 3.7
Simulation, OBJ 0.2 0.3 1.4 0.4 ms 1.2 1.9 0.2 0.2 5.4
Visual, GLB 0.1 0.3 1.6 0.2 ms 2.9 41 ms 0.3 0.2 5.5
Visual, OBJ 0.1 0.3 1.5 0.4 ms 2.9 1.4 0.3 0.3 6.8
Board Repo: andrewpaterson/658-Computer
Board: Main Memory Small Enable.kicad_pcb
Folder Kicad / Computer / Main / Main Memory Small Enable
Complexity 216 / 1000 (size 146, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 14, 330, 35
Triangles, simulation 314,936 in 51 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 11 MB 240 MB
STEP 49 MB 280 MB
STL 16 MB 246 MB
OBJ 32 MB 258 MB
Visual
GLB 8.2 MB 271 MB
OBJ 24 MB 263 MB

210. Mainboard Full

Mainboard Full: stages 4 and 6 take 53% to 87% of a run. Simulation, GLB takes 2 min. Simulation, STEP takes 3 min. Simulation, STL takes 3 min. Simulation, OBJ takes 4 min. Visual, GLB takes 4 min. Visual, OBJ takes 4 min

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 1.3 10.3 63.9 5 ms 58.8 2.4 6.6 0.5 143.9
Simulation, STEP 1.4 10.6 63.2 4 ms 57.5 35.2 6.8 0.5 175.1
Simulation, STL 1.5 10.8 65.0 6 ms 58.8 6.6 7.1 0.5 150.3
Simulation, OBJ 1.4 11.1 65.6 3 ms 59.4 87.8 7.9 0.7 233.8
Visual, GLB 1.4 11.6 66.9 3 ms 131.4 1.3 14.1 0.6 227.3
Visual, OBJ 1.4 11.5 66.1 4 ms 130.4 44.6 12.7 0.4 267.0
Board Repo: andrewpaterson/658-Computer
Board: Mainboard Full.kicad_pcb
Folder Kicad / Computer / Main / Mainboard Full
Complexity 298 / 1000 (size 218, features 80)
KESE features through vias, rounded,
trapezoid or chamfered pads,
curved board outline,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 87, 9,120, 576
Triangles, simulation 12,987,450 in 878 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 429 MB 3.2 GB
STEP 1.8 GB 4.5 GB
STL 649 MB 3.3 GB
OBJ 1.4 GB 8.0 GB
Visual
GLB 245 MB 3.8 GB
OBJ 795 MB 4.9 GB

211. Mainboard Small

Mainboard Small: stages 4 and 6 take 55% to 86% of a run. Simulation, GLB takes 76 s. Simulation, STEP takes 92 s. Simulation, STL takes 77 s. Simulation, OBJ takes 2 min. Visual, GLB takes 2 min. Visual, OBJ takes 2 min

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.8 5.8 34.4 2 ms 29.9 1.4 3.8 0.4 76.5
Simulation, STEP 0.8 5.8 34.4 2 ms 28.2 18.8 3.5 0.3 92.0
Simulation, STL 0.8 5.8 34.4 3 ms 29.0 2.7 3.7 0.4 76.7
Simulation, OBJ 0.8 5.7 34.8 3 ms 29.8 42.1 3.5 0.4 117.1
Visual, GLB 0.9 5.7 34.0 2 ms 59.8 0.7 7.2 0.3 108.5
Visual, OBJ 0.8 6.0 34.3 3 ms 61.6 22.8 7.5 0.3 133.3
Board Repo: andrewpaterson/658-Computer
Board: Mainboard Small.kicad_pcb
Folder Kicad / Computer / Main / Mainboard Small
Complexity 281 / 1000 (size 201, features 80)
KESE features through vias, rounded,
trapezoid or chamfered pads,
curved board outline,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 51, 4,728, 253
Triangles, simulation 6,784,078 in 504 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 224 MB 1.9 GB
STEP 930 MB 2.5 GB
STL 339 MB 1.9 GB
OBJ 714 MB 4.2 GB
Visual
GLB 128 MB 2.1 GB
OBJ 409 MB 2.7 GB

212. Processor Full Device

Processor Full Device: stages 4 and 6 take 54% to 84% of a run. Simulation, GLB takes 7.2 s. Simulation, STEP takes 8.9 s. Simulation, STL takes 7.3 s. Simulation, OBJ takes 10 s. Visual, GLB takes 13 s. Visual, OBJ takes 15 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.7 2.9 0.5 ms 2.7 0.1 0.3 0.2 7.2
Simulation, STEP 0.2 0.7 2.9 0.3 ms 2.5 2.1 0.3 0.2 8.9
Simulation, STL 0.2 0.7 2.8 0.7 ms 2.8 0.3 0.3 0.2 7.3
Simulation, OBJ 0.2 0.7 2.9 0.5 ms 2.8 3.3 0.3 0.2 10.4
Visual, GLB 0.2 0.7 2.9 0.5 ms 7.6 96 ms 0.7 0.2 12.5
Visual, OBJ 0.2 0.7 3.0 0.5 ms 7.5 2.8 0.8 0.2 15.3
Board Repo: andrewpaterson/658-Computer
Board: Processor Full Device.kicad_pcb
Folder Kicad / Computer / Main / Processor Full Device
Complexity 247 / 1000 (size 177, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 34, 1,154, 160
Triangles, simulation 802,414 in 111 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 28 MB 428 MB
STEP 132 MB 509 MB
STL 40 MB 433 MB
OBJ 82 MB 568 MB
Visual
GLB 24 MB 612 MB
OBJ 74 MB 609 MB

213. Processor Reset Device

Processor Reset Device: stages 4 and 6 take 50% to 80% of a run. Simulation, GLB takes 2.7 s. Simulation, STEP takes 3.7 s. Simulation, STL takes 2.5 s. Simulation, OBJ takes 3.8 s. Visual, GLB takes 3.9 s. Visual, OBJ takes 4.7 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.2 1.0 0.2 ms 0.9 44 ms 0.1 0.2 2.7
Simulation, STEP 0.1 0.2 1.0 0.2 ms 1.0 1.0 0.1 0.2 3.7
Simulation, STL 0.1 0.2 0.9 0.3 ms 0.9 60 ms 0.1 0.2 2.5
Simulation, OBJ 0.1 0.2 0.9 0.2 ms 1.0 1.2 0.1 0.3 3.8
Visual, GLB 0.1 0.2 0.9 0.2 ms 2.2 33 ms 0.2 0.2 3.9
Visual, OBJ 0.1 0.2 0.9 0.2 ms 2.0 0.9 0.3 0.2 4.7
Board Repo: andrewpaterson/658-Computer
Board: Processor Reset Device.kicad_pcb
Folder Kicad / Computer / Main / Processor Reset Device
Complexity 216 / 1000 (size 146, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 18, 265, 37
Triangles, simulation 284,136 in 52 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 9.6 MB 234 MB
STEP 43 MB 266 MB
STL 14 MB 230 MB
OBJ 28 MB 238 MB
Visual
GLB 7.9 MB 261 MB
OBJ 23 MB 258 MB

214. Processor Small Device

Processor Small Device: stages 4 and 6 take 50% to 82% of a run. Simulation, GLB takes 3.7 s. Simulation, STEP takes 4.9 s. Simulation, STL takes 3.7 s. Simulation, OBJ takes 5.5 s. Visual, GLB takes 5.6 s. Visual, OBJ takes 7.1 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.3 1.6 0.3 ms 1.2 59 ms 0.2 0.2 3.7
Simulation, STEP 0.1 0.3 1.4 0.2 ms 1.3 1.3 0.2 0.2 4.9
Simulation, STL 0.1 0.3 1.5 0.4 ms 1.2 81 ms 0.3 0.2 3.7
Simulation, OBJ 0.2 0.4 1.5 0.4 ms 1.3 1.8 0.2 0.2 5.5
Visual, GLB 0.1 0.3 1.5 0.3 ms 3.1 42 ms 0.3 0.2 5.6
Visual, OBJ 0.1 0.4 1.4 0.3 ms 3.3 1.4 0.3 0.2 7.1
Board Repo: andrewpaterson/658-Computer
Board: Processor Small Device.kicad_pcb
Folder Kicad / Computer / Main / Processor Small Device
Complexity 217 / 1000 (size 147, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 14, 339, 42
Triangles, simulation 342,214 in 59 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 12 MB 254 MB
STEP 55 MB 279 MB
STL 17 MB 266 MB
OBJ 35 MB 281 MB
Visual
GLB 9.3 MB 288 MB
OBJ 27 MB 284 MB

215. Status Device

Status Device: stages 4 and 6 take 53% to 82% of a run. Simulation, GLB takes 8.6 s. Simulation, STEP takes 12 s. Simulation, STL takes 9.2 s. Simulation, OBJ takes 13 s. Visual, GLB takes 13 s. Visual, OBJ takes 17 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 0.9 3.2 0.5 ms 3.5 0.1 0.5 0.2 8.6
Simulation, STEP 0.2 1.0 3.3 0.5 ms 3.6 2.7 0.6 0.3 11.6
Simulation, STL 0.2 1.0 3.4 0.5 ms 3.6 0.3 0.4 0.2 9.2
Simulation, OBJ 0.2 0.9 3.4 0.7 ms 3.6 4.3 0.5 0.2 13.1
Visual, GLB 0.2 0.9 3.4 0.9 ms 7.5 0.1 0.8 0.2 13.3
Visual, OBJ 0.2 0.9 3.2 1.0 ms 7.4 3.8 1.1 0.3 16.9
Board Repo: andrewpaterson/658-Computer
Board: Status Device.kicad_pcb
Folder Kicad / Computer / Main / Status Device
Complexity 258 / 1000 (size 178, features 80)
KESE features through vias, rounded,
trapezoid or chamfered pads,
curved board outline,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 33, 1,184, 228
Triangles, simulation 895,756 in 115 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 31 MB 416 MB
STEP 138 MB 539 MB
STL 45 MB 416 MB
OBJ 91 MB 783 MB
Visual
GLB 26 MB 656 MB
OBJ 80 MB 705 MB

216. Triple MPU Clock Generator

Triple MPU Clock Generator: stages 4 and 6 take 52% to 83% of a run. Simulation, GLB takes 13 s. Simulation, STEP takes 15 s. Simulation, STL takes 12 s. Simulation, OBJ takes 19 s. Visual, GLB takes 19 s. Visual, OBJ takes 24 s

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.4 1.4 5.3 0.6 ms 4.8 0.2 0.7 0.3 13.2
Simulation, STEP 0.3 1.2 4.9 0.8 ms 4.3 3.6 0.6 0.3 15.3
Simulation, STL 0.3 1.1 4.7 0.6 ms 4.3 0.4 0.5 0.3 11.7
Simulation, OBJ 0.3 1.3 5.3 0.6 ms 4.5 6.5 0.6 0.3 18.9
Visual, GLB 0.3 1.3 4.9 7 ms 11.0 0.1 1.3 0.3 19.4
Visual, OBJ 0.3 1.1 5.0 0.5 ms 10.7 5.3 1.3 0.3 23.9
Board Repo: andrewpaterson/658-Computer
Board: Triple MPU Clock Generator.kicad_pcb
Folder Kicad / Computer / Main / Triple MPU Clock Generator
Complexity 251 / 1000 (size 181, features 70)
KESE features through vias, rounded,
trapezoid or chamfered pads,
knockout text, stack-up,
dielectric εr and tanδ
Tested 9th November 2026
Copper layers 2
File format KiCad 9 (20241229)
Parts, tracks, vias 46, 1,232, 186
Triangles, simulation 947,040 in 148 parts
Verifier PASS in all six runs
File
type
File
size
Peak memory
used
Simulation
GLB 32 MB 409 MB
STEP 147 MB 541 MB
STL 47 MB 414 MB
OBJ 96 MB 676 MB
Visual
GLB 26 MB 597 MB
OBJ 80 MB 640 MB
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