Corpus Testing 18

Corpus Page 18

Part 18 of 30 of Corpus Testing: boards 1,837 to 1,944, six runs each, one file format a run, as Corpus Testing describes.

1837. ESP32-EVB_Rev_D

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	2.4	12.4	1 ms	9.6	0.4	1.3	0.3	26.9
Simulation, STEP	0.5	2.2	12.1	1.0 ms	9.5	6.3	1.3	0.3	32.2
Simulation, STL	0.7	2.4	12.6	0.8 ms	10.0	0.9	1.4	0.3	28.1
Simulation, OBJ	0.6	2.4	12.3	1.0 ms	9.7	11.1	1.4	0.3	37.8
Visual, GLB	0.6	2.4	12.5	1 ms	23.9	0.3	3.6	0.3	43.5
Visual, OBJ	0.7	2.4	12.2	1 ms	23.7	9.4	3.6	0.3	52.3

Board Repo: OLIMEX/ESP32-EVB Board: ESP32-EVB_Rev_D.kicad_pcb Folder HARDWARE / REV-D Complexity 301 / 1000 (size 246, features 55) KESE features through vias, slotted holes, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20170123) Parts, tracks, vias 146, 2,818, 315 Triangles, simulation 2,219,460 in 143 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 78 MB 775 MB STEP 428 MB 1.0 GB STL 111 MB 801 MB OBJ 239 MB 1.5 GB Visual GLB 62 MB 1.1 GB OBJ 190 MB 1.3 GB

1838. ESP32-EVB_Rev_F

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	2.8	12.9	1.0 ms	11.1	0.4	1.5	0.3	29.8
Simulation, STEP	0.8	2.8	13.3	1 ms	10.8	6.9	1.4	0.3	36.3
Simulation, STL	0.7	2.8	12.9	1 ms	10.3	0.7	1.4	0.3	29.1
Simulation, OBJ	0.8	2.6	13.1	0.7 ms	10.7	14.9	1.4	0.2	43.6
Visual, GLB	0.8	2.6	12.8	0.8 ms	24.0	0.4	2.5	0.3	43.3
Visual, OBJ	0.7	2.7	12.6	0.7 ms	24.8	10.9	2.5	0.3	54.6

Board Repo: OLIMEX/ESP32-EVB Board: ESP32-EVB_Rev_F.kicad_pcb Folder HARDWARE / REV-F Complexity 301 / 1000 (size 246, features 55) KESE features through vias, slotted holes, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 148, 2,880, 303 Triangles, simulation 2,246,438 in 143 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 79 MB 931 MB STEP 438 MB 1.0 GB STL 112 MB 916 MB OBJ 242 MB 1.5 GB Visual GLB 63 MB 1.1 GB OBJ 193 MB 1.4 GB

1839. ESP32-EVB_Rev_H

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	2.3	11.1	0.7 ms	9.7	0.3	1.2	0.3	25.6
Simulation, STEP	0.6	2.3	11.1	0.7 ms	9.6	6.2	1.2	0.3	31.2
Simulation, STL	0.6	2.4	11.3	0.7 ms	9.7	0.6	1.1	0.3	26.0
Simulation, OBJ	0.7	2.4	11.5	1 ms	9.8	12.0	1.1	0.3	37.7
Visual, GLB	0.6	2.3	11.0	0.7 ms	21.0	0.3	2.0	0.2	37.5
Visual, OBJ	0.6	2.4	11.1	0.6 ms	20.9	9.5	2.2	0.2	46.9

Board Repo: OLIMEX/ESP32-EVB Board: ESP32-EVB_Rev_H.kicad_pcb Folder HARDWARE / REV-H Complexity 291 / 1000 (size 246, features 45) KESE features through vias, slotted holes, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 146, 2,965, 310 Triangles, simulation 2,248,598 in 140 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 79 MB 846 MB STEP 430 MB 1.0 GB STL 112 MB 936 MB OBJ 242 MB 1.5 GB Visual GLB 64 MB 1.1 GB OBJ 197 MB 1.3 GB

1840. ESP32-EVB_Rev_I

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	2.1	9.9	0.8 ms	8.5	0.3	1.0	0.2	22.5
Simulation, STEP	0.5	1.9	9.5	0.8 ms	8.7	5.2	1.0	0.2	27.1
Simulation, STL	0.6	1.9	9.7	0.9 ms	8.3	0.6	1.0	0.2	22.3
Simulation, OBJ	0.5	1.9	9.4	1 ms	8.5	9.2	1.1	0.2	30.9
Visual, GLB	0.6	1.8	9.5	0.8 ms	19.3	0.2	2.8	0.3	34.5
Visual, OBJ	0.5	1.9	9.4	0.9 ms	19.5	7.8	3.1	0.2	42.4

Board Repo: OLIMEX/ESP32-EVB Board: ESP32-EVB_Rev_I.kicad_pcb Folder HARDWARE / REV-I Complexity 301 / 1000 (size 246, features 55) KESE features through vias, slotted holes, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 147, 2,960, 310 Triangles, simulation 2,199,014 in 140 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 78 MB 858 MB STEP 417 MB 1.0 GB STL 110 MB 899 MB OBJ 236 MB 1.5 GB Visual GLB 63 MB 1.1 GB OBJ 193 MB 1.4 GB

1841. ESP32-EVB_Rev_J

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	2.6	11.0	0.8 ms	9.1	0.4	1.2	0.3	25.3
Simulation, STEP	0.8	2.3	11.6	1 ms	9.3	6.3	1.2	0.3	31.7
Simulation, STL	0.8	2.5	11.1	1 ms	9.1	0.6	1.3	0.3	25.7
Simulation, OBJ	0.7	2.7	11.3	1.0 ms	9.2	10.5	1.2	0.2	35.8
Visual, GLB	0.7	2.5	11.4	0.9 ms	22.5	0.3	2.6	0.3	40.3
Visual, OBJ	0.7	2.2	11.0	0.9 ms	23.5	8.8	2.7	0.3	49.2

Board Repo: OLIMEX/ESP32-EVB Board: ESP32-EVB_Rev_J.kicad_pcb Folder HARDWARE / REV-J Complexity 303 / 1000 (size 248, features 55) KESE features through vias, slotted holes, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 157, 3,235, 315 Triangles, simulation 2,334,232 in 145 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 82 MB 886 MB STEP 445 MB 1.1 GB STL 117 MB 890 MB OBJ 251 MB 1.6 GB Visual GLB 66 MB 1.2 GB OBJ 203 MB 1.4 GB

1842. ESP32-EVB_Rev_K

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	2.6	11.4	0.8 ms	8.8	0.3	1.1	0.3	25.3
Simulation, STEP	0.7	2.4	11.1	0.6 ms	8.7	5.9	1.1	0.2	30.0
Simulation, STL	0.8	2.5	11.5	0.9 ms	8.9	0.5	1.2	0.2	25.6
Simulation, OBJ	0.8	2.4	11.3	0.7 ms	8.8	12.1	1.2	0.2	36.8
Visual, GLB	0.7	2.5	11.0	0.4 ms	20.7	0.3	2.5	0.2	38.0
Visual, OBJ	0.7	2.4	10.7	0.8 ms	20.6	9.7	2.6	0.2	47.0

Board Repo: OLIMEX/ESP32-EVB Board: ESP32-EVB_Rev_K.kicad_pcb Folder HARDWARE / REV-K Complexity 303 / 1000 (size 248, features 55) KESE features through vias, slotted holes, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 157, 3,236, 315 Triangles, simulation 2,291,902 in 145 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 81 MB 890 MB STEP 430 MB 1.1 GB STL 115 MB 886 MB OBJ 247 MB 1.6 GB Visual GLB 66 MB 1.1 GB OBJ 203 MB 1.4 GB

1843. ESP32-EVB_Rev_K1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.9	2.8	13.3	0.9 ms	10.3	0.4	1.3	0.3	29.4
Simulation, STEP	1.0	2.8	13.0	0.8 ms	10.0	6.7	1.3	0.3	35.0
Simulation, STL	0.9	2.9	13.2	0.8 ms	9.9	0.7	1.2	0.3	29.2
Simulation, OBJ	0.9	2.9	13.3	0.9 ms	10.2	13.7	1.3	0.3	42.6
Visual, GLB	0.9	2.9	13.2	1.0 ms	24.8	0.3	2.9	0.3	45.3
Visual, OBJ	0.9	2.9	12.9	0.8 ms	24.1	11.4	3.0	0.3	55.6

Board Repo: OLIMEX/ESP32-EVB Board: ESP32-EVB_Rev_K1.kicad_pcb Folder HARDWARE / REV-K1 Complexity 303 / 1000 (size 248, features 55) KESE features through vias, slotted holes, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 157, 3,236, 315 Triangles, simulation 2,292,316 in 145 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 81 MB 865 MB STEP 430 MB 1.0 GB STL 115 MB 852 MB OBJ 247 MB 1.6 GB Visual GLB 66 MB 1.1 GB OBJ 203 MB 1.4 GB

1844. ESP32-EVB_Rev_K2

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	2.3	11.6	1.0 ms	8.9	0.3	1.1	0.3	25.4
Simulation, STEP	0.7	2.5	11.4	0.9 ms	8.7	6.0	1.1	0.3	30.7
Simulation, STL	0.7	2.5	11.7	1 ms	9.2	0.6	1.2	0.3	26.2
Simulation, OBJ	0.7	2.5	11.1	1.0 ms	9.0	11.1	1.3	0.2	36.0
Visual, GLB	0.8	2.4	11.1	1 ms	22.8	0.3	3.2	0.3	40.9
Visual, OBJ	0.8	2.4	11.7	0.9 ms	24.4	9.9	3.6	0.3	53.0

Board Repo: OLIMEX/ESP32-EVB Board: ESP32-EVB_Rev_K2.kicad_pcb Folder HARDWARE / REV-K2 Complexity 293 / 1000 (size 248, features 45) KESE features through vias, slotted holes, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 157, 3,236, 315 Triangles, simulation 2,292,312 in 145 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 81 MB 972 MB STEP 430 MB 1.1 GB STL 115 MB 900 MB OBJ 247 MB 1.6 GB Visual GLB 66 MB 1.1 GB OBJ 203 MB 1.3 GB

1845. ESP32-EVB_Rev_L

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	2.5	10.8	0.7 ms	8.9	0.3	1.1	0.2	24.7
Simulation, STEP	0.8	2.4	10.9	0.7 ms	9.2	5.9	1.0	0.2	30.6
Simulation, STL	1.0	2.3	11.1	0.8 ms	9.0	0.5	1.0	0.2	25.1
Simulation, OBJ	0.9	2.3	10.7	0.6 ms	9.0	11.6	1.2	0.3	36.0
Visual, GLB	0.9	2.3	11.2	0.8 ms	21.8	0.3	2.4	0.2	39.2
Visual, OBJ	0.9	2.5	11.0	0.7 ms	21.9	9.9	3.0	0.3	49.4

Board Repo: OLIMEX/ESP32-EVB Board: ESP32-EVB_Rev_L.kicad_pcb Folder HARDWARE / REV-L Complexity 307 / 1000 (size 247, features 60) KESE features through vias, slotted holes, filled zones, knockout text Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 155, 3,066, 307 Triangles, simulation 2,193,876 in 144 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 78 MB 830 MB STEP 424 MB 981 MB STL 110 MB 807 MB OBJ 237 MB 1.5 GB Visual GLB 62 MB 1.1 GB OBJ 191 MB 1.4 GB

1846. ESP32-GATEWAY_Rev_A

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.6	7.6	0.9 ms	5.3	0.3	0.7	0.3	16.2
Simulation, STEP	0.5	1.6	7.7	0.6 ms	5.2	4.0	0.7	0.3	20.0
Simulation, STL	0.5	1.6	7.3	0.5 ms	5.1	0.4	0.7	0.2	15.8
Simulation, OBJ	0.4	1.6	7.3	0.6 ms	5.3	8.0	0.7	0.2	23.7
Visual, GLB	0.4	1.5	7.6	0.6 ms	12.7	0.2	1.7	0.2	24.4
Visual, OBJ	0.5	1.6	7.2	0.5 ms	13.1	6.6	1.8	0.2	30.9

Board Repo: OLIMEX/ESP32-GATEWAY Board: ESP32-GATEWAY_Rev_A.kicad_pcb Folder HARDWARE / Hardware revision A Complexity 288 / 1000 (size 233, features 55) KESE features through vias, slotted holes, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20170123) Parts, tracks, vias 82, 1,876, 230 Triangles, simulation 1,311,668 in 104 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 47 MB 544 MB STEP 241 MB 642 MB STL 66 MB 551 MB OBJ 139 MB 933 MB Visual GLB 38 MB 716 MB OBJ 114 MB 783 MB

1847. ESP32-GATEWAY_Rev_B

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.4	6.7	0.6 ms	4.7	0.2	0.7	0.3	14.4
Simulation, STEP	0.4	1.4	6.5	0.6 ms	4.6	3.4	0.6	0.2	17.1
Simulation, STL	0.4	1.4	6.3	0.6 ms	4.8	0.5	0.6	0.3	14.3
Simulation, OBJ	0.5	1.4	6.3	0.5 ms	4.7	6.6	0.8	0.3	20.6
Visual, GLB	0.7	1.8	7.9	0.6 ms	12.6	0.2	1.6	0.3	25.0
Visual, OBJ	0.4	1.2	6.7	0.6 ms	12.7	5.8	1.9	0.2	28.9

Board Repo: OLIMEX/ESP32-GATEWAY Board: ESP32-GATEWAY_Rev_B.kicad_pcb Folder HARDWARE / Hardware revision B Complexity 288 / 1000 (size 233, features 55) KESE features through vias, slotted holes, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20170123) Parts, tracks, vias 83, 1,858, 229 Triangles, simulation 1,306,382 in 104 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 46 MB 547 MB STEP 240 MB 637 MB STL 65 MB 535 MB OBJ 138 MB 942 MB Visual GLB 38 MB 685 MB OBJ 114 MB 796 MB

1848. ESP32-GATEWAY_Rev_C

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.5	7.0	0.5 ms	4.8	0.2	0.6	0.3	14.9
Simulation, STEP	0.5	1.4	6.8	0.5 ms	4.6	3.8	0.6	0.2	17.9
Simulation, STL	0.5	1.5	6.9	0.6 ms	4.8	0.5	0.7	0.2	15.1
Simulation, OBJ	0.5	1.5	7.1	0.6 ms	4.8	7.4	0.6	0.3	22.1
Visual, GLB	0.4	1.6	6.8	0.5 ms	13.1	0.2	1.4	0.3	23.7
Visual, OBJ	0.5	1.6	6.9	0.5 ms	12.6	6.2	1.7	0.3	29.8

Board Repo: OLIMEX/ESP32-GATEWAY Board: ESP32-GATEWAY_Rev_C.kicad_pcb Folder HARDWARE / Hardware revision C Complexity 288 / 1000 (size 233, features 55) KESE features through vias, slotted holes, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 84, 1,868, 232 Triangles, simulation 1,333,358 in 104 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 47 MB 554 MB STEP 246 MB 670 MB STL 67 MB 558 MB OBJ 141 MB 950 MB Visual GLB 39 MB 758 MB OBJ 117 MB 822 MB

1849. ESP32-GATEWAY_Rev_D

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.9	7.2	0.5 ms	5.1	0.2	0.7	0.3	15.9
Simulation, STEP	0.5	1.9	7.1	0.5 ms	4.8	3.7	0.7	0.2	18.8
Simulation, STL	0.4	1.8	7.0	0.4 ms	4.8	0.4	0.7	0.3	15.4
Simulation, OBJ	0.5	1.9	6.9	0.4 ms	4.8	7.5	0.6	0.3	22.5
Visual, GLB	0.4	2.0	7.2	0.5 ms	11.8	0.2	1.4	0.2	23.2
Visual, OBJ	0.5	1.9	7.3	0.6 ms	12.2	6.4	1.5	0.3	30.0

Board Repo: OLIMEX/ESP32-GATEWAY Board: ESP32-GATEWAY_Rev_D.kicad_pcb Folder HARDWARE / Hardware revision D Complexity 288 / 1000 (size 233, features 55) KESE features through vias, slotted holes, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,793, 226 Triangles, simulation 1,276,634 in 102 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 45 MB 541 MB STEP 236 MB 642 MB STL 64 MB 544 MB OBJ 135 MB 888 MB Visual GLB 37 MB 697 MB OBJ 111 MB 803 MB

1850. ESP32-GATEWAY_Rev_E

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.5	5.9	0.5 ms	4.1	0.2	0.6	0.2	12.9
Simulation, STEP	0.4	1.6	5.8	0.5 ms	4.0	3.2	0.5	0.2	15.7
Simulation, STL	0.4	1.6	5.6	0.3 ms	4.0	0.3	0.5	0.2	12.7
Simulation, OBJ	0.4	1.6	5.7	0.3 ms	4.1	6.2	0.6	0.2	18.6
Visual, GLB	0.4	1.6	6.0	0.4 ms	9.9	0.2	1.1	0.2	19.3
Visual, OBJ	0.4	1.5	5.8	0.4 ms	10.3	5.3	1.2	0.2	24.8

Board Repo: OLIMEX/ESP32-GATEWAY Board: ESP32-GATEWAY_Rev_E.kicad_pcb Folder HARDWARE / Hardware revision E Complexity 288 / 1000 (size 233, features 55) KESE features through vias, slotted holes, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 82, 1,795, 226 Triangles, simulation 1,276,018 in 103 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 45 MB 541 MB STEP 236 MB 645 MB STL 64 MB 535 MB OBJ 134 MB 881 MB Visual GLB 37 MB 685 MB OBJ 111 MB 839 MB

1851. ESP32-GATEWAY_Rev_F

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.8	7.6	0.4 ms	5.4	0.2	0.7	0.3	16.5
Simulation, STEP	0.5	1.8	7.6	0.4 ms	5.5	4.0	0.7	0.2	20.3
Simulation, STL	0.5	1.8	7.8	0.4 ms	5.3	0.4	0.7	0.2	16.8
Simulation, OBJ	0.5	1.7	7.7	0.5 ms	5.4	8.4	0.7	0.2	24.7
Visual, GLB	0.5	1.8	7.8	0.3 ms	14.2	0.2	1.5	0.3	26.3
Visual, OBJ	0.5	1.8	7.8	0.7 ms	14.0	7.0	1.6	0.3	33.0

Board Repo: OLIMEX/ESP32-GATEWAY Board: ESP32-GATEWAY_Rev_F.kicad_pcb Folder HARDWARE / Hardware revision F Complexity 291 / 1000 (size 236, features 55) KESE features through vias, slotted holes, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 6 (20190331) Parts, tracks, vias 90, 1,929, 320 Triangles, simulation 1,424,536 in 110 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 50 MB 608 MB STEP 242 MB 696 MB STL 71 MB 603 MB OBJ 150 MB 1.0 GB Visual GLB 42 MB 772 MB OBJ 126 MB 959 MB

1852. ESP32-GATEWAY_Rev_G

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.8	8.2	0.5 ms	5.8	0.3	0.8	0.3	17.7
Simulation, STEP	0.6	1.8	8.2	0.6 ms	5.7	4.1	0.7	0.3	21.5
Simulation, STL	0.5	1.9	8.6	0.8 ms	5.8	0.5	0.7	0.3	18.2
Simulation, OBJ	0.5	1.8	8.2	0.3 ms	5.6	8.4	0.7	0.2	25.5
Visual, GLB	0.5	1.9	8.4	0.4 ms	15.2	0.2	1.7	0.3	28.1
Visual, OBJ	0.5	1.9	8.2	0.6 ms	14.1	7.3	1.8	0.3	34.1

Board Repo: OLIMEX/ESP32-GATEWAY Board: ESP32-GATEWAY_Rev_G.kicad_pcb Folder HARDWARE / Hardware revision G Complexity 291 / 1000 (size 236, features 55) KESE features through vias, slotted holes, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 90, 1,944, 322 Triangles, simulation 1,438,022 in 110 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 51 MB 607 MB STEP 245 MB 713 MB STL 72 MB 591 MB OBJ 151 MB 999 MB Visual GLB 42 MB 811 MB OBJ 127 MB 971 MB

1853. ESP32-GATEWAY_Rev_H

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.8	7.8	0.3 ms	6.0	0.3	0.7	0.2	17.3
Simulation, STEP	0.5	1.8	7.9	0.4 ms	6.0	4.2	0.7	0.3	21.5
Simulation, STL	0.6	1.8	7.9	0.3 ms	5.8	0.4	0.8	0.2	17.4
Simulation, OBJ	0.5	1.9	7.8	0.4 ms	6.1	9.2	0.8	0.3	26.4
Visual, GLB	0.5	1.8	7.6	0.4 ms	15.5	0.2	2.0	0.2	27.8
Visual, OBJ	0.5	1.7	7.6	0.4 ms	15.7	8.6	1.9	0.3	36.3

Board Repo: OLIMEX/ESP32-GATEWAY Board: ESP32-GATEWAY_Rev_H.kicad_pcb Folder HARDWARE / Hardware revision H Complexity 281 / 1000 (size 236, features 45) KESE features through vias, slotted holes, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 97, 1,920, 287 Triangles, simulation 1,463,584 in 110 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 52 MB 604 MB STEP 256 MB 724 MB STL 73 MB 651 MB OBJ 154 MB 1.0 GB Visual GLB 43 MB 788 MB OBJ 130 MB 920 MB

1854. ESP32-GATEWAY_Rev_I

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.5	6.6	0.6 ms	5.3	0.2	0.6	0.3	15.1
Simulation, STEP	0.5	1.5	6.8	0.6 ms	5.2	3.9	0.6	0.3	18.8
Simulation, STL	0.4	1.6	6.8	0.7 ms	5.8	0.4	0.7	0.3	16.1
Simulation, OBJ	0.4	1.7	6.7	0.7 ms	5.3	7.7	0.6	0.3	22.7
Visual, GLB	0.4	1.6	6.6	0.7 ms	14.3	0.2	1.9	0.2	25.3
Visual, OBJ	0.5	1.3	6.8	0.9 ms	14.4	5.8	2.0	0.3	31.2

Board Repo: OLIMEX/ESP32-GATEWAY Board: ESP32-GATEWAY_Rev_I.kicad_pcb Folder HARDWARE / Hardware revision I Complexity 281 / 1000 (size 236, features 45) KESE features through vias, slotted holes, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 98, 1,934, 287 Triangles, simulation 1,474,380 in 111 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 52 MB 608 MB STEP 259 MB 722 MB STL 74 MB 620 MB OBJ 156 MB 1.0 GB Visual GLB 43 MB 783 MB OBJ 131 MB 941 MB

1855. ESP32-H2-DevKit-LiPo_Rev_A

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.1	4.5	0.4 ms	3.9	0.2	0.5	0.2	10.9
Simulation, STEP	0.4	1.1	4.4	0.4 ms	4.0	3.0	0.5	0.2	13.5
Simulation, STL	0.5	1.1	4.5	0.4 ms	3.9	0.4	0.5	0.3	11.2
Simulation, OBJ	0.5	1.0	4.4	0.4 ms	3.8	5.6	0.5	0.2	16.1
Visual, GLB	0.4	1.1	4.4	0.4 ms	9.6	0.1	1.1	0.2	16.9
Visual, OBJ	0.4	1.1	4.4	0.4 ms	9.4	4.3	1.3	0.2	21.1

Board Repo: OLIMEX/ESP32-H2-DevKit-Lipo Board: ESP32-H2-DevKit-LiPo_Rev_A.kicad_pcb Folder HARDWARE / ESP32-H2-DevKit-Lipo-Rev.A Complexity 282 / 1000 (size 182, features 100) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 68, 1,096, 124 Triangles, simulation 1,066,038 in 83 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 38 MB 552 MB STEP 224 MB 574 MB STL 53 MB 517 MB OBJ 113 MB 790 MB Visual GLB 32 MB 694 MB OBJ 95 MB 719 MB

1856. ESP32-P4-DevKit_Rev_B

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	2.3	8.9	0.8 ms	8.8	0.4	1.4	0.3	22.9
Simulation, STEP	0.8	2.4	9.0	1 ms	8.8	6.1	1.4	0.2	28.7
Simulation, STL	0.8	2.2	9.0	1 ms	9.2	0.7	1.3	0.3	23.5
Simulation, OBJ	0.8	2.2	9.3	1 ms	9.0	11.6	1.5	0.3	34.7
Visual, GLB	0.9	2.3	9.1	1 ms	22.2	0.3	3.0	0.3	38.0
Visual, OBJ	0.9	2.4	9.2	1.0 ms	20.7	8.4	3.0	0.3	44.7

Board Repo: OLIMEX/ESP32-P4-DevKit Board: ESP32-P4-DevKit_Rev_B.kicad_pcb Folder HARDWARE / ESP32-P4-DevKit-Rev.B Complexity 363 / 1000 (size 268, features 95) KESE features through vias, slotted holes, filled zones, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 138, 2,985, 213 Triangles, simulation 2,254,720 in 189 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 80 MB 789 MB STEP 407 MB 988 MB STL 113 MB 773 MB OBJ 245 MB 1.6 GB Visual GLB 57 MB 978 MB OBJ 175 MB 1.2 GB

1857. ESP32-P4-DevKit_Rev_C

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	1.9	7.4	0.9 ms	7.9	0.3	1.0	0.2	19.4
Simulation, STEP	0.7	1.9	7.5	0.8 ms	7.5	5.1	1.0	0.3	24.0
Simulation, STL	0.7	1.9	7.4	0.7 ms	7.9	0.7	1.1	0.3	19.9
Simulation, OBJ	0.7	2.0	7.5	0.8 ms	7.7	10.0	1.3	0.3	29.5
Visual, GLB	0.7	2.0	7.6	1.0 ms	19.2	0.2	2.8	0.3	32.8
Visual, OBJ	0.7	2.0	7.8	1 ms	19.2	6.9	2.8	0.2	39.7

Board Repo: OLIMEX/ESP32-P4-DevKit Board: ESP32-P4-DevKit_Rev_C.kicad_pcb Folder HARDWARE / ESP32-P4-DevKit-Rev.C Complexity 374 / 1000 (size 269, features 105) KESE features through vias, slotted holes, filled zones, copper text, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 138, 3,235, 216 Triangles, simulation 2,286,940 in 189 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 82 MB 859 MB STEP 413 MB 978 MB STL 114 MB 820 MB OBJ 249 MB 1.6 GB Visual GLB 57 MB 1.0 GB OBJ 177 MB 1.2 GB

1858. ESP32-P4-DevKit_Rev_D

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.0	2.7	9.8	0.9 ms	9.9	0.5	1.5	0.3	25.8
Simulation, STEP	1.0	2.7	9.9	0.8 ms	9.9	6.9	1.6	0.3	32.2
Simulation, STL	1.0	2.7	9.9	1 ms	10.4	0.8	1.5	0.3	26.6
Simulation, OBJ	1.0	2.5	9.9	4 ms	11.1	14.8	1.7	0.3	41.2
Visual, GLB	1.0	2.6	10.6	1 ms	24.8	0.3	2.8	0.3	42.4
Visual, OBJ	1.1	3.0	10.8	1 ms	25.4	10.8	2.9	0.3	54.3

Board Repo: OLIMEX/ESP32-P4-DevKit Board: ESP32-P4-DevKit_Rev_D.kicad_pcb Folder HARDWARE / ESP32-P4-DevKit-Rev.D Complexity 375 / 1000 (size 270, features 105) KESE features through vias, slotted holes, filled zones, copper text, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 142, 3,494, 216 Triangles, simulation 2,292,888 in 191 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 82 MB 831 MB STEP 414 MB 951 MB STL 115 MB 779 MB OBJ 249 MB 1.6 GB Visual GLB 58 MB 1.0 GB OBJ 178 MB 1.3 GB

1859. ESP32-P4-DevKit_Rev_D1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.0	2.5	9.8	0.8 ms	9.8	0.4	1.5	0.3	25.3
Simulation, STEP	1.0	2.6	9.3	1 ms	9.2	6.2	1.4	0.3	30.0
Simulation, STL	1.7	3.7	11.0	0.8 ms	9.7	0.8	1.4	0.4	28.7
Simulation, OBJ	0.9	2.5	9.1	0.7 ms	9.2	12.4	1.5	0.3	35.8
Visual, GLB	0.8	2.3	8.6	0.7 ms	20.4	0.2	2.3	0.2	34.8
Visual, OBJ	0.8	2.3	8.6	0.9 ms	20.3	9.2	2.5	0.3	44.0

Board Repo: OLIMEX/ESP32-P4-DevKit Board: ESP32-P4-DevKit_Rev_D1.kicad_pcb Folder HARDWARE / ESP32-P4-DevKit-Rev.D1 Complexity 375 / 1000 (size 270, features 105) KESE features through vias, slotted holes, filled zones, copper text, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 142, 3,494, 216 Triangles, simulation 2,292,888 in 191 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 82 MB 841 MB STEP 414 MB 992 MB STL 115 MB 831 MB OBJ 249 MB 1.6 GB Visual GLB 58 MB 1.0 GB OBJ 178 MB 1.3 GB

1860. ESP32-P4-PC_Rev_B

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.3	3.6	13.1	2 ms	14.8	0.6	1.8	0.3	35.3
Simulation, STEP	1.2	3.7	13.2	0.7 ms	15.0	8.3	1.9	0.3	43.5
Simulation, STL	1.2	3.8	13.4	0.8 ms	14.9	1.5	2.1	0.3	37.2
Simulation, OBJ	1.3	3.7	13.5	1 ms	14.8	18.1	2.0	0.3	53.5
Visual, GLB	1.3	3.6	13.0	0.8 ms	33.4	0.4	4.4	0.2	56.4
Visual, OBJ	1.2	3.7	13.3	0.8 ms	34.4	11.9	5.0	0.3	69.8

Board Repo: OLIMEX/ESP32-P4-PC Board: ESP32-P4-PC_Rev_B.kicad_pcb Folder HARDWARE / ESP32-P4-PC-Rev.B Complexity 408 / 1000 (size 293, features 115) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 312, 5,090, 549 Triangles, simulation 4,020,402 in 316 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 142 MB 1.3 GB STEP 676 MB 1.6 GB STL 201 MB 1.3 GB OBJ 440 MB 2.7 GB Visual GLB 96 MB 1.5 GB OBJ 303 MB 2.0 GB

1861. ESP32-P4-PC_Rev_C

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.5	4.3	15.3	2 ms	15.6	0.8	2.2	0.3	39.9
Simulation, STEP	1.3	4.0	14.9	1 ms	16.5	9.4	2.2	0.4	48.8
Simulation, STL	1.5	4.0	14.5	0.7 ms	15.9	1.4	2.1	0.3	39.8
Simulation, OBJ	1.3	4.2	14.8	1.0 ms	15.7	19.0	2.1	0.3	57.6
Visual, GLB	1.3	4.0	15.0	0.9 ms	35.4	0.5	4.6	0.3	61.0
Visual, OBJ	1.5	4.1	15.1	2 ms	36.4	13.7	4.8	0.3	76.0

Board Repo: OLIMEX/ESP32-P4-PC Board: ESP32-P4-PC_Rev_C.kicad_pcb Folder HARDWARE / ESP32-P4-PC-Rev.C Complexity 409 / 1000 (size 294, features 115) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 312, 5,436, 553 Triangles, simulation 4,016,618 in 316 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 142 MB 1.3 GB STEP 671 MB 1.5 GB STL 201 MB 1.3 GB OBJ 439 MB 2.7 GB Visual GLB 95 MB 1.5 GB OBJ 302 MB 2.0 GB

1862. ESP32-PoE_Rev_B1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.4	6.7	0.4 ms	6.5	0.2	0.7	0.2	16.2
Simulation, STEP	0.5	1.4	6.4	0.4 ms	6.2	3.9	0.7	0.2	19.4
Simulation, STL	0.5	1.4	6.4	0.6 ms	6.5	0.4	0.7	0.2	16.0
Simulation, OBJ	0.4	1.4	6.4	0.6 ms	6.3	7.3	0.7	0.2	22.7
Visual, GLB	0.4	1.3	6.3	0.6 ms	13.3	0.2	1.0	0.2	22.8
Visual, OBJ	0.4	1.4	6.6	0.9 ms	13.1	6.5	1.0	0.2	29.2

Board Repo: OLIMEX/ESP32-POE Board: ESP32-PoE_Rev_B1.kicad_pcb Folder HARDWARE / ESP32-PoE-hardware-revision-B1 Complexity 294 / 1000 (size 239, features 55) KESE features through vias, slotted holes, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 111, 2,429, 176 Triangles, simulation 1,444,926 in 144 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 52 MB 554 MB STEP 288 MB 719 MB STL 72 MB 540 MB OBJ 154 MB 1.0 GB Visual GLB 43 MB 782 MB OBJ 129 MB 893 MB

1863. ESP32-PoE_Rev_B2

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.4	5.4	0.6 ms	5.6	0.2	0.7	0.2	13.9
Simulation, STEP	0.4	1.4	5.2	0.4 ms	5.4	3.3	0.6	0.2	16.5
Simulation, STL	0.4	1.5	5.3	0.3 ms	5.5	0.5	0.6	0.2	14.0
Simulation, OBJ	0.4	1.4	5.2	0.3 ms	5.7	5.9	0.7	0.2	19.5
Visual, GLB	0.4	1.5	5.2	0.4 ms	12.4	0.2	1.4	0.2	21.3
Visual, OBJ	0.4	1.5	5.3	0.6 ms	12.0	5.0	1.8	0.2	26.2

Board Repo: OLIMEX/ESP32-POE Board: ESP32-PoE_Rev_B2.kicad_pcb Folder HARDWARE / ESP32-PoE-hardware-revision-B2 Complexity 294 / 1000 (size 239, features 55) KESE features through vias, slotted holes, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 112, 2,429, 176 Triangles, simulation 1,427,864 in 144 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 51 MB 545 MB STEP 286 MB 746 MB STL 71 MB 531 MB OBJ 152 MB 996 MB Visual GLB 42 MB 811 MB OBJ 127 MB 902 MB

1864. ESP32-PoE_Rev_C

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.8	6.3	1 ms	6.5	0.2	0.8	0.3	16.2
Simulation, STEP	0.4	1.8	6.5	0.6 ms	6.3	3.9	0.8	0.3	20.0
Simulation, STL	0.4	1.8	6.6	0.9 ms	6.6	0.5	0.8	0.3	17.0
Simulation, OBJ	0.5	1.8	7.1	0.6 ms	6.6	7.4	0.9	0.2	24.5
Visual, GLB	0.4	1.9	6.3	0.6 ms	15.2	0.2	2.1	0.3	26.4
Visual, OBJ	0.5	1.8	6.6	0.7 ms	14.6	6.1	2.1	0.3	31.8

Board Repo: OLIMEX/ESP32-POE Board: ESP32-PoE_Rev_C.kicad_pcb Folder HARDWARE / ESP32-PoE-hardware-revision-C Complexity 294 / 1000 (size 239, features 55) KESE features through vias, slotted holes, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 111, 2,500, 173 Triangles, simulation 1,413,496 in 139 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 50 MB 524 MB STEP 284 MB 716 MB STL 71 MB 563 MB OBJ 151 MB 979 MB Visual GLB 42 MB 787 MB OBJ 126 MB 928 MB

1865. ESP32-PoE_Rev_C

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	2.0	7.2	0.6 ms	7.3	0.3	0.7	0.3	18.5
Simulation, STEP	0.6	1.9	7.1	0.7 ms	7.7	4.8	1.0	0.3	23.3
Simulation, STL	0.6	2.2	8.1	0.7 ms	7.9	0.5	0.8	0.3	20.4
Simulation, OBJ	0.5	2.0	7.5	0.9 ms	7.7	9.1	0.9	0.3	28.1
Visual, GLB	0.6	2.1	7.3	0.7 ms	17.3	0.2	2.2	0.3	29.9
Visual, OBJ	0.6	2.0	7.4	0.7 ms	15.9	7.7	2.3	0.3	36.3

Board Repo: OLIMEX/ESP32-POE Board: ESP32-PoE_Rev_C.kicad_pcb Folder HARDWARE / ESP32-PoE-hardware-revision-C1 Complexity 284 / 1000 (size 239, features 45) KESE features through vias, slotted holes, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 111, 2,500, 173 Triangles, simulation 1,379,052 in 139 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 49 MB 574 MB STEP 274 MB 672 MB STL 69 MB 578 MB OBJ 147 MB 981 MB Visual GLB 41 MB 783 MB OBJ 125 MB 908 MB

1866. ESP32-PoE_Rev_D

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	1.8	7.4	0.5 ms	6.1	0.2	0.9	0.3	17.4
Simulation, STEP	0.6	1.7	7.0	0.5 ms	6.1	4.4	1.0	0.3	21.2
Simulation, STL	0.7	1.7	7.3	0.6 ms	6.2	0.5	0.9	0.3	17.6
Simulation, OBJ	0.6	1.8	7.2	0.7 ms	6.3	9.2	0.9	0.2	26.2
Visual, GLB	0.5	1.7	7.2	0.8 ms	16.5	0.2	1.8	0.3	28.3
Visual, OBJ	0.5	1.7	7.1	0.7 ms	16.0	7.8	2.1	0.3	35.5

Board Repo: OLIMEX/ESP32-POE Board: ESP32-PoE_Rev_D.kicad_pcb Folder HARDWARE / ESP32-PoE-hardware-revision-D Complexity 307 / 1000 (size 242, features 65) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 117, 2,882, 234 Triangles, simulation 1,515,032 in 139 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 54 MB 653 MB STEP 292 MB 748 MB STL 76 MB 640 MB OBJ 161 MB 1.1 GB Visual GLB 45 MB 798 MB OBJ 137 MB 1.0 GB

1867. ESP32-PoE_Rev_E

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.6	6.6	1 ms	6.1	0.3	0.8	0.3	16.2
Simulation, STEP	0.5	1.6	6.5	0.8 ms	6.0	4.0	0.8	0.3	19.6
Simulation, STL	0.5	1.5	6.6	1 ms	6.0	0.5	0.9	0.3	16.2
Simulation, OBJ	0.4	1.5	6.8	0.9 ms	6.1	7.5	0.8	0.3	23.4
Visual, GLB	0.5	1.6	6.3	0.7 ms	15.5	0.3	2.0	0.3	26.3
Visual, OBJ	0.5	1.6	6.6	0.8 ms	15.1	6.2	2.1	0.3	32.3

Board Repo: OLIMEX/ESP32-POE Board: ESP32-PoE_Rev_E.kicad_pcb Folder HARDWARE / ESP32-PoE-hardware-revision-E Complexity 308 / 1000 (size 243, features 65) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 118, 2,894, 234 Triangles, simulation 1,515,626 in 139 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 54 MB 670 MB STEP 292 MB 760 MB STL 76 MB 661 MB OBJ 162 MB 1.1 GB Visual GLB 45 MB 826 MB OBJ 137 MB 949 MB

1868. ESP32-PoE_Rev_G1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.5	6.4	0.6 ms	5.5	0.2	0.8	0.2	15.1
Simulation, STEP	0.5	1.5	6.5	0.6 ms	5.7	3.9	0.8	0.2	19.0
Simulation, STL	0.5	1.6	6.3	0.7 ms	5.9	0.6	0.8	0.3	16.1
Simulation, OBJ	0.5	1.5	6.3	0.6 ms	5.6	8.5	0.8	0.2	23.5
Visual, GLB	0.6	1.5	6.6	0.5 ms	14.6	0.2	1.6	0.2	25.3
Visual, OBJ	0.5	1.5	6.5	0.9 ms	14.4	6.9	1.8	0.2	31.8

Board Repo: OLIMEX/ESP32-POE Board: ESP32-PoE_Rev_G1.kicad_pcb Folder HARDWARE / ESP32-PoE-hardware-revision-G1 Complexity 297 / 1000 (size 242, features 55) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 120, 2,717, 212 Triangles, simulation 1,477,504 in 135 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 53 MB 634 MB STEP 287 MB 744 MB STL 74 MB 642 MB OBJ 158 MB 1.0 GB Visual GLB 45 MB 783 MB OBJ 137 MB 982 MB

1869. ESP32-PoE_Rev_I

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	1.9	7.1	0.6 ms	7.0	0.3	1.0	0.3	18.2
Simulation, STEP	0.6	1.8	7.0	0.5 ms	7.0	4.8	0.9	0.2	22.3
Simulation, STL	0.6	2.0	7.0	0.6 ms	7.0	0.5	1.0	0.2	18.3
Simulation, OBJ	0.6	1.9	6.8	0.6 ms	6.8	10.0	1.0	0.2	27.5
Visual, GLB	0.6	1.9	7.0	0.6 ms	15.1	0.2	1.3	0.2	26.3
Visual, OBJ	0.6	1.8	6.8	0.7 ms	15.1	7.6	1.3	0.2	33.4

Board Repo: OLIMEX/ESP32-POE Board: ESP32-PoE_Rev_I.kicad_pcb Folder HARDWARE / ESP32-PoE-hardware-revision-I Complexity 324 / 1000 (size 259, features 65) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 123, 2,830, 219 Triangles, simulation 1,907,268 in 138 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 67 MB 694 MB STEP 306 MB 846 MB STL 95 MB 691 MB OBJ 204 MB 1.3 GB Visual GLB 48 MB 859 MB OBJ 147 MB 1.1 GB

1870. ESP32-PoE_Rev_J

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	2.0	6.4	0.6 ms	7.0	0.3	1.0	0.3	17.5
Simulation, STEP	0.5	2.1	6.6	0.7 ms	6.9	4.3	0.9	0.2	21.6
Simulation, STL	0.5	1.7	6.5	0.6 ms	6.9	0.6	0.9	0.3	17.5
Simulation, OBJ	0.6	2.1	6.7	0.9 ms	7.0	9.7	0.9	0.3	27.3
Visual, GLB	0.6	1.8	6.7	0.8 ms	17.0	0.2	2.1	0.3	28.7
Visual, OBJ	0.6	2.0	6.5	0.7 ms	17.5	7.1	2.4	0.3	36.4

Board Repo: OLIMEX/ESP32-POE Board: ESP32-PoE_Rev_J.kicad_pcb Folder HARDWARE / ESP32-PoE-hardware-revision-J Complexity 323 / 1000 (size 258, features 65) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 126, 2,532, 219 Triangles, simulation 2,002,088 in 139 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 71 MB 687 MB STEP 310 MB 840 MB STL 100 MB 708 MB OBJ 214 MB 1.4 GB Visual GLB 48 MB 854 MB OBJ 147 MB 1.1 GB

1871. ESP32-PoE_Rev_K

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	2.1	7.1	0.8 ms	7.3	0.3	1.0	0.3	18.8
Simulation, STEP	0.7	2.0	6.8	0.9 ms	7.2	4.8	1.0	0.3	22.8
Simulation, STL	0.6	2.0	7.0	0.6 ms	7.3	0.6	0.9	0.2	18.7
Simulation, OBJ	0.5	2.0	7.1	0.7 ms	7.3	10.6	1.0	0.3	28.8
Visual, GLB	0.5	2.2	7.2	0.8 ms	17.4	0.2	2.0	0.2	29.8
Visual, OBJ	0.6	2.0	6.6	0.9 ms	17.6	6.7	2.3	0.3	36.2

Board Repo: OLIMEX/ESP32-POE Board: ESP32-PoE_Rev_K.kicad_pcb Folder HARDWARE / ESP32-PoE-hardware-revision-K Complexity 323 / 1000 (size 258, features 65) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 128, 2,562, 219 Triangles, simulation 2,011,184 in 139 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 71 MB 782 MB STEP 312 MB 870 MB STL 101 MB 734 MB OBJ 215 MB 1.4 GB Visual GLB 49 MB 877 MB OBJ 148 MB 1.1 GB

1872. ESP32-PoE_Rev_L

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	2.3	7.8	0.7 ms	7.9	0.3	1.1	0.3	20.4
Simulation, STEP	0.7	2.2	7.8	0.6 ms	7.8	5.3	1.1	0.3	25.1
Simulation, STL	0.7	2.3	7.6	0.6 ms	7.8	0.6	1.0	0.3	20.3
Simulation, OBJ	0.7	2.2	7.7	0.6 ms	7.8	11.5	1.1	0.3	31.3
Visual, GLB	0.7	2.2	7.7	0.6 ms	17.8	0.2	1.8	0.2	30.6
Visual, OBJ	0.7	2.2	7.7	0.6 ms	18.1	8.5	1.8	0.3	39.3

Board Repo: OLIMEX/ESP32-POE Board: ESP32-PoE_Rev_L.kicad_pcb Folder HARDWARE / ESP32-PoE-hardware-revision-L Complexity 323 / 1000 (size 258, features 65) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 128, 2,574, 221 Triangles, simulation 2,018,962 in 139 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 71 MB 669 MB STEP 313 MB 857 MB STL 101 MB 677 MB OBJ 216 MB 1.4 GB Visual GLB 49 MB 864 MB OBJ 149 MB 1.1 GB

1873. ESP32-PoE_Rev_L1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	2.1	7.4	0.6 ms	7.4	0.3	1.0	0.2	19.2
Simulation, STEP	0.7	2.1	7.3	0.6 ms	7.3	5.0	1.0	0.3	23.7
Simulation, STL	0.7	2.3	7.6	0.6 ms	7.4	0.6	0.9	0.3	19.8
Simulation, OBJ	0.7	2.0	7.5	0.6 ms	7.3	11.4	1.0	0.3	30.2
Visual, GLB	0.7	2.2	7.6	0.6 ms	17.3	0.3	2.0	0.3	30.4
Visual, OBJ	0.7	2.0	7.2	0.6 ms	16.6	8.2	2.2	0.3	37.2

Board Repo: OLIMEX/ESP32-POE Board: ESP32-PoE_Rev_L1.kicad_pcb Folder HARDWARE / ESP32-PoE-hardware-revision-L1 Complexity 323 / 1000 (size 258, features 65) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 128, 2,574, 221 Triangles, simulation 2,024,004 in 139 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 71 MB 673 MB STEP 314 MB 826 MB STL 101 MB 703 MB OBJ 216 MB 1.4 GB Visual GLB 49 MB 860 MB OBJ 149 MB 1.1 GB

1874. ESP32-PoE_Rev_M

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	2.0	6.8	0.6 ms	6.9	0.3	1.0	0.3	18.0
Simulation, STEP	0.7	2.0	6.7	0.8 ms	6.7	4.6	1.0	0.3	22.1
Simulation, STL	0.7	2.1	6.9	0.5 ms	6.9	0.5	0.9	0.2	18.3
Simulation, OBJ	0.8	2.0	6.8	0.6 ms	6.7	10.4	1.0	0.3	28.0
Visual, GLB	0.8	2.1	6.8	0.6 ms	14.8	0.2	1.3	0.2	26.2
Visual, OBJ	0.7	2.0	6.9	0.7 ms	14.8	7.2	1.2	0.2	33.0

Board Repo: OLIMEX/ESP32-POE Board: ESP32-PoE_Rev_M.kicad_pcb Folder HARDWARE / ESP32-PoE-hardware-revision-M Complexity 368 / 1000 (size 258, features 110) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 127, 2,528, 233 Triangles, simulation 1,971,162 in 133 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 69 MB 722 MB STEP 335 MB 887 MB STL 99 MB 694 MB OBJ 211 MB 1.4 GB Visual GLB 47 MB 874 MB OBJ 144 MB 1.1 GB

1875. ESP32-PoE_Rev_M1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	1.7	5.7	0.7 ms	6.4	0.3	0.9	0.2	16.0
Simulation, STEP	0.6	1.7	5.5	0.6 ms	6.2	4.1	0.9	0.2	19.3
Simulation, STL	0.7	1.8	5.8	0.8 ms	6.5	0.6	1.0	0.3	16.6
Simulation, OBJ	0.6	1.8	5.7	1 ms	6.5	8.4	0.8	0.2	24.0
Visual, GLB	0.6	1.9	5.7	0.6 ms	14.9	0.2	1.9	0.2	25.4
Visual, OBJ	0.6	1.6	5.6	0.6 ms	14.2	6.0	1.9	0.2	30.1

Board Repo: OLIMEX/ESP32-POE Board: ESP32-PoE_Rev_M1.kicad_pcb Folder HARDWARE / ESP32-PoE-hardware-revision-M1 Complexity 368 / 1000 (size 258, features 110) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 127, 2,528, 233 Triangles, simulation 1,971,162 in 133 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 69 MB 741 MB STEP 335 MB 835 MB STL 99 MB 745 MB OBJ 211 MB 1.4 GB Visual GLB 47 MB 848 MB OBJ 144 MB 1.1 GB

1876. ESP32-PoE_Rev_M2

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.9	2.2	7.6	0.6 ms	7.7	0.3	1.0	0.3	20.1
Simulation, STEP	0.8	2.3	7.1	0.6 ms	7.7	5.2	1.0	0.3	24.4
Simulation, STL	0.8	2.4	7.7	0.6 ms	8.0	0.7	1.0	0.3	20.8
Simulation, OBJ	0.9	2.1	7.4	0.9 ms	7.6	11.6	1.1	0.3	31.1
Visual, GLB	0.8	2.3	8.3	0.9 ms	17.3	0.2	1.7	0.3	31.0
Visual, OBJ	0.8	2.2	7.9	0.7 ms	17.6	8.3	2.3	0.2	39.3

Board Repo: OLIMEX/ESP32-POE Board: ESP32-PoE_Rev_M2.kicad_pcb Folder HARDWARE / ESP32-PoE-hardware-revision-M2 Complexity 368 / 1000 (size 258, features 110) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 128, 2,528, 233 Triangles, simulation 1,972,166 in 133 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 69 MB 713 MB STEP 335 MB 843 MB STL 99 MB 761 MB OBJ 211 MB 1.4 GB Visual GLB 47 MB 835 MB OBJ 145 MB 1.0 GB

1877. ESP32-PoE-ISO_Rev_B

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	3.1	9.7	2 ms	11.2	0.4	1.3	0.4	26.9
Simulation, STEP	0.8	3.0	10.4	1 ms	11.3	6.9	1.5	0.3	34.2
Simulation, STL	0.9	3.8	10.1	1 ms	10.4	1.0	1.5	0.4	28.2
Simulation, OBJ	0.8	3.2	9.1	1 ms	10.4	14.2	1.1	0.3	39.2
Visual, GLB	0.7	2.9	8.6	1 ms	22.2	0.3	2.9	0.2	37.7
Visual, OBJ	0.7	2.6	8.3	1 ms	21.5	9.5	3.0	0.3	46.0

Board Repo: OLIMEX/ESP32-POE-ISO Board: ESP32-PoE-ISO_Rev_B.kicad_pcb Folder HARDWARE / ESP32-PoE-ISO-Rev.B Complexity 325 / 1000 (size 260, features 65) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 118, 2,830, 332 Triangles, simulation 2,271,626 in 142 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 79 MB 817 MB STEP 312 MB 892 MB STL 114 MB 805 MB OBJ 242 MB 1.5 GB Visual GLB 51 MB 892 MB OBJ 157 MB 1.1 GB

1878. ESP32-PoE-ISO_Rev_C

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	2.2	6.8	0.5 ms	8.0	0.4	1.0	0.3	19.3
Simulation, STEP	0.6	2.3	7.1	0.9 ms	8.1	5.0	1.0	0.2	24.2
Simulation, STL	0.7	2.4	7.1	0.4 ms	8.2	0.8	1.0	0.3	20.3
Simulation, OBJ	0.6	2.4	7.2	1 ms	7.9	11.7	1.0	0.3	31.1
Visual, GLB	0.6	2.3	7.3	0.6 ms	18.3	0.3	2.3	0.2	31.2
Visual, OBJ	0.5	2.3	6.9	0.6 ms	18.3	7.4	2.5	0.2	38.2

Board Repo: OLIMEX/ESP32-POE-ISO Board: ESP32-PoE-ISO_Rev_C.kicad_pcb Folder HARDWARE / ESP32-PoE-ISO-Rev.C Complexity 336 / 1000 (size 261, features 75) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 6 (20190516) Parts, tracks, vias 117, 2,943, 326 Triangles, simulation 2,260,980 in 142 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 79 MB 840 MB STEP 321 MB 905 MB STL 113 MB 788 MB OBJ 240 MB 1.5 GB Visual GLB 52 MB 920 MB OBJ 159 MB 1.1 GB

1879. ESP32-PoE-ISO_Rev_D

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	2.3	7.5	0.6 ms	7.6	0.4	0.9	0.3	19.9
Simulation, STEP	0.7	2.2	7.1	0.7 ms	7.8	5.0	1.0	0.3	24.0
Simulation, STL	0.6	2.2	7.5	0.5 ms	7.6	0.8	1.0	0.3	19.9
Simulation, OBJ	0.6	2.2	7.2	0.5 ms	7.9	11.7	0.9	0.2	30.8
Visual, GLB	0.6	2.4	7.2	0.5 ms	17.4	0.2	1.8	0.3	29.9
Visual, OBJ	0.6	2.2	7.5	0.5 ms	17.5	8.1	2.0	0.3	38.2

Board Repo: OLIMEX/ESP32-POE-ISO Board: ESP32-PoE-ISO_Rev_D.kicad_pcb Folder HARDWARE / ESP32-PoE-ISO-Rev.D Complexity 336 / 1000 (size 261, features 75) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 6 (20191123) Parts, tracks, vias 118, 2,957, 326 Triangles, simulation 2,205,456 in 142 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 77 MB 799 MB STEP 311 MB 874 MB STL 110 MB 787 MB OBJ 234 MB 1.5 GB Visual GLB 51 MB 894 MB OBJ 156 MB 1.1 GB

1880. ESP32-PoE-ISO_Rev_G1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	2.6	9.2	0.9 ms	11.0	0.4	1.2	0.3	25.4
Simulation, STEP	0.8	2.7	8.4	0.5 ms	10.0	5.8	1.2	0.3	29.1
Simulation, STL	0.7	2.7	8.3	0.6 ms	9.7	1.0	1.1	0.3	23.8
Simulation, OBJ	0.7	2.7	8.2	1.0 ms	9.6	13.7	1.0	0.3	36.3
Visual, GLB	0.7	2.7	8.4	0.6 ms	23.4	0.3	3.2	0.3	38.9
Visual, OBJ	0.7	2.9	9.2	0.8 ms	23.6	10.6	3.4	0.3	50.7

Board Repo: OLIMEX/ESP32-POE-ISO Board: ESP32-PoE-ISO_Rev_G1.kicad_pcb Folder HARDWARE / ESP32-PoE-ISO-Rev.G1 Complexity 337 / 1000 (size 262, features 75) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 122, 3,042, 331 Triangles, simulation 2,274,334 in 138 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 80 MB 818 MB STEP 318 MB 887 MB STL 114 MB 742 MB OBJ 242 MB 1.6 GB Visual GLB 52 MB 934 MB OBJ 160 MB 1.1 GB

1881. ESP32-PoE-ISO_Rev_H

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.9	6.1	0.4 ms	6.9	0.3	0.8	0.2	16.8
Simulation, STEP	0.5	2.0	6.0	0.3 ms	7.0	4.2	0.9	0.2	20.8
Simulation, STL	0.6	1.9	5.9	0.5 ms	7.4	0.6	0.9	0.2	17.4
Simulation, OBJ	0.5	1.9	5.9	0.6 ms	7.3	9.4	0.9	0.2	26.1
Visual, GLB	0.5	2.0	6.0	0.3 ms	16.5	0.2	2.4	0.2	27.9
Visual, OBJ	0.5	2.0	6.1	0.5 ms	16.8	6.4	2.4	0.2	34.5

Board Repo: OLIMEX/ESP32-POE-ISO Board: ESP32-PoE-ISO_Rev_H.kicad_pcb Folder HARDWARE / ESP32-PoE-ISO-Rev.H Complexity 337 / 1000 (size 262, features 75) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 123, 3,089, 329 Triangles, simulation 2,272,098 in 138 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 80 MB 801 MB STEP 318 MB 881 MB STL 114 MB 787 MB OBJ 242 MB 1.6 GB Visual GLB 52 MB 945 MB OBJ 160 MB 1.1 GB

1882. ESP32-PoE-ISO_Rev_I

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	2.3	7.2	0.4 ms	7.9	0.4	1.0	0.3	19.6
Simulation, STEP	0.6	2.3	7.2	0.4 ms	8.0	5.0	1.0	0.2	24.4
Simulation, STL	0.6	2.2	7.3	0.4 ms	8.1	0.6	1.0	0.2	20.1
Simulation, OBJ	0.6	2.3	7.5	0.6 ms	8.0	12.0	1.0	0.3	31.7
Visual, GLB	0.6	2.3	7.2	0.6 ms	18.2	0.3	1.7	0.2	30.4
Visual, OBJ	0.7	2.4	7.4	0.5 ms	17.9	7.9	1.7	0.3	38.3

Board Repo: OLIMEX/ESP32-POE-ISO Board: ESP32-PoE-ISO_Rev_I.kicad_pcb Folder HARDWARE / ESP32-PoE-ISO-Rev.I Complexity 337 / 1000 (size 262, features 75) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 123, 3,108, 329 Triangles, simulation 2,285,522 in 138 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 80 MB 800 MB STEP 321 MB 908 MB STL 114 MB 773 MB OBJ 244 MB 1.5 GB Visual GLB 53 MB 925 MB OBJ 161 MB 1.1 GB

1883. ESP32-PoE-ISO_Rev_J

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	2.5	7.7	0.4 ms	8.8	0.4	1.0	0.2	21.3
Simulation, STEP	0.7	2.3	7.8	0.6 ms	8.8	5.3	1.1	0.3	26.3
Simulation, STL	0.7	2.2	7.7	0.6 ms	8.7	0.6	1.0	0.3	21.3
Simulation, OBJ	0.6	2.0	7.6	0.6 ms	8.9	11.9	1.0	0.2	32.3
Visual, GLB	0.6	2.6	7.2	0.4 ms	19.3	0.2	2.1	0.3	32.2
Visual, OBJ	0.7	2.3	7.2	0.5 ms	18.5	7.4	2.3	0.3	38.7

Board Repo: OLIMEX/ESP32-POE-ISO Board: ESP32-PoE-ISO_Rev_J.kicad_pcb Folder HARDWARE / ESP32-PoE-ISO-Rev.J Complexity 337 / 1000 (size 262, features 75) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 126, 3,029, 319 Triangles, simulation 2,413,834 in 139 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 84 MB 765 MB STEP 345 MB 965 MB STL 121 MB 762 MB OBJ 257 MB 1.6 GB Visual GLB 56 MB 1.0 GB OBJ 171 MB 1.2 GB

1884. ESP32-PoE-ISO_Rev_K

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	2.4	7.7	0.7 ms	9.3	0.4	1.1	0.3	22.0
Simulation, STEP	0.7	2.4	7.5	0.3 ms	9.6	5.6	1.1	0.3	27.3
Simulation, STL	0.8	2.6	8.0	0.4 ms	9.6	0.8	1.1	0.3	23.1
Simulation, OBJ	0.7	2.4	7.7	0.5 ms	9.7	12.1	1.1	0.3	33.9
Visual, GLB	0.7	2.4	7.5	0.4 ms	21.5	0.3	3.2	0.3	35.9
Visual, OBJ	0.8	2.4	7.9	0.9 ms	21.1	8.2	3.2	0.3	43.8

Board Repo: OLIMEX/ESP32-POE-ISO Board: ESP32-PoE-ISO_Rev_K.kicad_pcb Folder HARDWARE / ESP32-PoE-ISO-Rev.K Complexity 337 / 1000 (size 262, features 75) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 128, 3,057, 320 Triangles, simulation 2,423,136 in 139 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 85 MB 782 MB STEP 346 MB 978 MB STL 121 MB 780 MB OBJ 258 MB 1.6 GB Visual GLB 56 MB 982 MB OBJ 172 MB 1.2 GB

1885. ESP32-PoE-ISO_Rev_L

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.9	2.9	9.0	0.7 ms	10.7	0.4	1.3	0.3	25.3
Simulation, STEP	0.8	2.6	8.9	0.4 ms	10.9	6.6	1.1	0.3	31.3
Simulation, STL	0.8	2.7	8.8	0.7 ms	11.6	1.0	1.3	0.3	26.7
Simulation, OBJ	0.9	2.9	9.3	0.5 ms	11.4	15.8	1.4	0.3	42.0
Visual, GLB	0.9	2.9	8.6	0.5 ms	24.2	0.3	3.1	0.3	40.3
Visual, OBJ	0.9	2.8	8.5	0.4 ms	24.6	10.1	3.2	0.3	50.4

Board Repo: OLIMEX/ESP32-POE-ISO Board: ESP32-PoE-ISO_Rev_L.kicad_pcb Folder HARDWARE / ESP32-PoE-ISO-Rev.L Complexity 337 / 1000 (size 262, features 75) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 128, 3,103, 321 Triangles, simulation 2,428,460 in 139 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 85 MB 755 MB STEP 347 MB 987 MB STL 121 MB 805 MB OBJ 259 MB 1.7 GB Visual GLB 56 MB 994 MB OBJ 172 MB 1.2 GB

1886. ESP32-PoE-ISO_Rev_M

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.0	2.7	8.1	0.6 ms	9.6	0.4	1.1	0.3	23.2
Simulation, STEP	1.0	2.7	8.1	0.8 ms	9.5	5.8	1.2	0.3	28.6
Simulation, STL	1.0	2.7	8.0	0.6 ms	9.6	0.9	1.2	0.3	23.7
Simulation, OBJ	1.0	2.7	8.2	0.4 ms	9.8	15.0	1.4	0.3	38.5
Visual, GLB	1.1	2.8	8.3	0.6 ms	22.2	0.3	3.1	0.3	38.1
Visual, OBJ	1.1	3.0	8.7	0.9 ms	25.0	10.2	3.1	0.3	51.5

Board Repo: OLIMEX/ESP32-POE-ISO Board: ESP32-PoE-ISO_Rev_M.kicad_pcb Folder HARDWARE / ESP32-PoE-ISO-Rev.M Complexity 389 / 1000 (size 264, features 125) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 125, 3,737, 325 Triangles, simulation 2,278,208 in 134 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 80 MB 861 MB STEP 342 MB 907 MB STL 114 MB 874 MB OBJ 244 MB 1.5 GB Visual GLB 53 MB 959 MB OBJ 162 MB 1.1 GB

1887. ESP32-PoE-ISO_Rev_M1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.1	3.0	8.7	0.6 ms	9.7	0.4	1.2	0.3	24.5
Simulation, STEP	1.3	2.5	8.7	0.5 ms	9.8	6.3	1.2	0.4	30.1
Simulation, STL	1.1	2.7	8.8	0.6 ms	9.7	0.7	1.2	0.3	24.6
Simulation, OBJ	1.0	2.7	8.8	0.5 ms	9.3	14.0	1.2	0.3	37.3
Visual, GLB	1.2	2.6	8.5	0.4 ms	21.0	0.2	1.9	0.3	35.7
Visual, OBJ	1.1	2.9	8.4	0.7 ms	20.7	9.4	2.1	0.3	44.9

Board Repo: OLIMEX/ESP32-POE-ISO Board: ESP32-PoE-ISO_Rev_M1.kicad_pcb Folder HARDWARE / ESP32-PoE-ISO-Rev.M1 Complexity 389 / 1000 (size 264, features 125) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 126, 3,737, 325 Triangles, simulation 2,279,540 in 134 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 80 MB 823 MB STEP 343 MB 902 MB STL 114 MB 854 MB OBJ 244 MB 1.6 GB Visual GLB 53 MB 953 MB OBJ 163 MB 1.2 GB

1888. ESP32-PoE-ISO_Rev_N

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.2	2.7	9.0	1 ms	9.8	0.4	1.2	0.3	24.5
Simulation, STEP	1.0	2.7	8.4	0.9 ms	9.5	6.0	1.3	0.3	29.0
Simulation, STL	1.0	2.8	8.7	1 ms	10.1	1.0	1.4	0.4	25.4
Simulation, OBJ	1.0	2.9	9.1	0.9 ms	9.7	14.4	1.2	0.3	38.7
Visual, GLB	1.1	2.7	8.4	0.9 ms	22.2	0.3	2.5	0.3	37.4
Visual, OBJ	1.0	2.6	8.3	0.9 ms	22.3	9.4	2.5	0.3	46.4

Board Repo: OLIMEX/ESP32-POE-ISO Board: ESP32-PoE-ISO_Rev_N.kicad_pcb Folder HARDWARE / ESP32-PoE-ISO-Rev.N Complexity 389 / 1000 (size 264, features 125) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 127, 3,683, 326 Triangles, simulation 2,294,172 in 134 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 80 MB 860 MB STEP 347 MB 917 MB STL 115 MB 844 MB OBJ 246 MB 1.6 GB Visual GLB 53 MB 955 MB OBJ 164 MB 1.1 GB

1889. ESP32-PoE-ISO_Rev_N1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.0	2.6	8.1	0.8 ms	9.4	0.4	1.1	0.3	22.9
Simulation, STEP	1.0	2.7	8.3	0.7 ms	9.2	5.8	1.2	0.3	28.5
Simulation, STL	1.1	2.7	8.3	0.8 ms	9.2	0.7	1.1	0.3	23.3
Simulation, OBJ	1.0	2.7	8.2	0.9 ms	9.4	13.7	1.1	0.3	36.4
Visual, GLB	1.0	2.6	8.3	0.9 ms	21.1	0.3	2.2	0.3	35.8
Visual, OBJ	1.0	2.6	8.2	0.9 ms	21.1	9.2	2.4	0.3	45.0

Board Repo: OLIMEX/ESP32-POE-ISO Board: ESP32-PoE-ISO_Rev_N1.kicad_pcb Folder HARDWARE / ESP32-PoE-ISO-Rev.N1 Complexity 389 / 1000 (size 264, features 125) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 128, 3,683, 326 Triangles, simulation 2,295,698 in 134 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 81 MB 838 MB STEP 348 MB 949 MB STL 115 MB 791 MB OBJ 246 MB 1.6 GB Visual GLB 53 MB 959 MB OBJ 164 MB 1.2 GB

1890. ESP32-PoE-ISO_Rev_O

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.9	2.2	7.4	1.0 ms	8.2	0.3	1.0	0.2	20.3
Simulation, STEP	0.9	2.3	7.5	0.7 ms	8.3	5.3	1.0	0.2	25.7
Simulation, STL	0.9	2.4	7.7	0.7 ms	8.5	0.7	1.0	0.3	21.4
Simulation, OBJ	0.8	2.5	7.5	0.7 ms	8.8	12.4	1.0	0.3	33.2
Visual, GLB	1.0	2.4	7.4	0.8 ms	19.0	0.3	1.8	0.3	32.1
Visual, OBJ	1.1	2.5	7.9	0.8 ms	18.6	8.8	1.6	0.3	40.7

Board Repo: OLIMEX/ESP32-POE-ISO Board: ESP32-PoE-ISO_Rev_O.kicad_pcb Folder HARDWARE / ESP32-PoE-ISO-Rev.O Complexity 379 / 1000 (size 264, features 115) KESE features through vias, slotted holes, filled zones, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 129, 3,704, 322 Triangles, simulation 2,304,726 in 134 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 81 MB 806 MB STEP 353 MB 940 MB STL 115 MB 789 MB OBJ 247 MB 1.6 GB Visual GLB 54 MB 990 MB OBJ 167 MB 1.2 GB

1891. ESP32-PoE2_Rev_B

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.9	2.5	8.8	0.8 ms	11.1	0.4	1.0	0.3	25.0
Simulation, STEP	0.8	2.5	9.2	0.8 ms	11.0	5.2	1.0	0.3	30.0
Simulation, STL	0.8	2.4	8.8	1 ms	10.8	0.7	1.1	0.3	24.9
Simulation, OBJ	0.8	2.4	8.4	0.8 ms	10.9	11.4	1.0	0.3	35.3
Visual, GLB	0.7	2.3	8.4	0.7 ms	18.4	0.2	2.4	0.3	32.7
Visual, OBJ	0.7	2.4	9.0	0.9 ms	18.0	7.9	2.8	0.3	41.1

Board Repo: OLIMEX/ESP32-POE2 Board: ESP32-PoE2_Rev_B.kicad_pcb Folder HARDWARE / ESP32-PoE2_Rev_B Complexity 380 / 1000 (size 260, features 120) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 142, 2,198, 390 Triangles, simulation 2,336,490 in 142 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 81 MB 780 MB STEP 346 MB 1.0 GB STL 117 MB 823 MB OBJ 250 MB 1.6 GB Visual GLB 54 MB 974 MB OBJ 167 MB 1.2 GB

1892. ESP32-PRO_Rev_B

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	2.1	7.4	1.0 ms	7.1	0.3	0.8	0.3	18.6
Simulation, STEP	0.5	2.0	7.2	0.9 ms	6.8	4.2	0.8	0.3	21.8
Simulation, STL	0.5	1.7	7.1	0.6 ms	6.9	0.5	0.9	0.3	17.9
Simulation, OBJ	0.5	1.8	7.3	1 ms	6.9	8.4	0.8	0.2	26.0
Visual, GLB	0.5	1.9	7.3	0.7 ms	17.0	0.2	2.0	0.2	29.2
Visual, OBJ	0.5	1.9	7.4	0.9 ms	17.3	6.9	2.2	0.3	36.5

Board Repo: OLIMEX/ESP32-PRO Board: ESP32-PRO_Rev_B.kicad_pcb Folder HARDWARE / REV-B Complexity 308 / 1000 (size 253, features 55) KESE features through vias, slotted holes, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 123, 3,549, 327 Triangles, simulation 1,642,858 in 123 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 59 MB 676 MB STEP 310 MB 815 MB STL 82 MB 676 MB OBJ 176 MB 1.2 GB Visual GLB 50 MB 865 MB OBJ 151 MB 1.0 GB

1893. ESP32-PRO_Rev_B1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	2.0	7.7	0.8 ms	7.2	0.3	0.8	0.3	18.7
Simulation, STEP	0.5	1.9	7.0	0.7 ms	7.0	4.2	0.7	0.3	21.7
Simulation, STL	0.6	2.0	7.3	0.7 ms	7.1	0.5	0.8	0.2	18.5
Simulation, OBJ	0.5	2.0	7.5	0.9 ms	7.2	8.0	0.8	0.3	26.3
Visual, GLB	0.6	1.9	7.4	0.6 ms	16.9	0.3	2.2	0.3	29.5
Visual, OBJ	0.5	2.1	7.3	0.6 ms	16.2	7.1	2.3	0.2	35.7

Board Repo: OLIMEX/ESP32-PRO Board: ESP32-PRO_Rev_B1.kicad_pcb Folder HARDWARE / REV-B1 Complexity 308 / 1000 (size 253, features 55) KESE features through vias, slotted holes, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 123, 3,548, 327 Triangles, simulation 1,641,446 in 123 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 58 MB 699 MB STEP 307 MB 791 MB STL 82 MB 701 MB OBJ 176 MB 1.2 GB Visual GLB 50 MB 849 MB OBJ 151 MB 1.1 GB

1894. ESP32-S2-DevKit-Lipo_Rev_B1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.6	6.5	0.5 ms	5.1	0.2	0.6	0.2	14.8
Simulation, STEP	0.5	1.5	6.4	0.5 ms	5.1	3.9	0.7	0.2	18.4
Simulation, STL	0.5	1.6	6.5	0.5 ms	5.1	0.4	0.7	0.2	15.0
Simulation, OBJ	0.5	1.7	6.4	0.6 ms	5.1	7.9	0.6	0.3	22.6
Visual, GLB	0.5	1.5	6.4	0.5 ms	12.7	0.2	1.3	0.2	22.8
Visual, OBJ	0.5	1.6	6.5	0.5 ms	13.0	6.5	1.6	0.2	29.8

Board Repo: OLIMEX/ESP32-S2-DevKit-LiPo Board: ESP32-S2-DevKit-Lipo_Rev_B1.kicad_pcb Folder HARDWARE / ESP32-S2-DevKit-Lipo-Rev.B1 Complexity 253 / 1000 (size 188, features 65) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 76, 1,472, 164 Triangles, simulation 1,273,136 in 91 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 45 MB 575 MB STEP 244 MB 643 MB STL 64 MB 561 MB OBJ 135 MB 905 MB Visual GLB 39 MB 787 MB OBJ 115 MB 847 MB

1895. ESP32-S2-DevKit-USB_Rev_B

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.3	5.6	0.4 ms	4.8	0.2	0.6	0.3	13.2
Simulation, STEP	0.4	1.4	5.6	0.5 ms	4.8	3.4	0.6	0.2	16.4
Simulation, STL	0.4	1.4	5.6	0.5 ms	4.7	0.4	0.6	0.2	13.4
Simulation, OBJ	0.4	1.4	5.6	0.3 ms	4.9	6.9	0.6	0.2	19.9
Visual, GLB	0.4	1.3	5.7	0.7 ms	11.9	0.2	1.2	0.3	21.0
Visual, OBJ	0.4	1.4	6.0	0.4 ms	11.1	6.9	1.6	0.3	27.6

Board Repo: OLIMEX/ESP32-S2-DevKit-LiPo-USB Board: ESP32-S2-DevKit-USB_Rev_B.kicad_pcb Folder HARDWARE / ESP32-S2-DevKit-USB-Rev-B Complexity 250 / 1000 (size 185, features 65) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 66, 1,299, 156 Triangles, simulation 1,257,842 in 78 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 45 MB 605 MB STEP 241 MB 667 MB STL 63 MB 589 MB OBJ 133 MB 868 MB Visual GLB 38 MB 772 MB OBJ 113 MB 840 MB

1896. ESP32-S3-DevKit-LiPo_Rev_B_DIMM

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.4	5.8	0.3 ms	4.2	0.2	0.6	0.3	13.1
Simulation, STEP	0.5	1.5	5.8	0.7 ms	4.1	3.3	0.5	0.2	15.8
Simulation, STL	0.5	1.4	5.8	0.6 ms	4.3	0.3	0.5	0.2	13.1
Simulation, OBJ	0.5	1.4	5.8	0.4 ms	4.3	6.7	0.6	0.3	19.6
Visual, GLB	0.5	1.4	6.0	0.3 ms	10.4	0.2	0.9	0.2	19.6
Visual, OBJ	0.5	1.5	6.1	0.3 ms	10.4	5.6	1.0	0.2	25.3

Board Repo: OLIMEX/ESP32-S3-DevKit-LiPo Board: ESP32-S3-DevKit-LiPo_Rev_B_DIMM.kicad_pcb Folder HARDWARE / Dimensions Complexity 237 / 1000 (size 182, features 55) KESE features through vias, slotted holes, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 54, 1,324, 128 Triangles, simulation 1,184,962 in 82 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 42 MB 562 MB STEP 233 MB 633 MB STL 59 MB 542 MB OBJ 125 MB 851 MB Visual GLB 35 MB 769 MB OBJ 106 MB 801 MB

1897. ESP32-S3-DevKit-LiPo_Rev_B

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.5	6.5	0.3 ms	4.6	0.2	0.6	0.3	14.1
Simulation, STEP	0.5	1.5	6.5	0.3 ms	4.5	3.7	0.7	0.3	17.6
Simulation, STL	0.5	1.6	6.4	0.4 ms	4.6	0.3	0.6	0.3	14.3
Simulation, OBJ	0.5	1.5	6.4	0.4 ms	4.7	7.4	0.6	0.2	21.4
Visual, GLB	0.5	1.6	6.5	0.8 ms	11.4	0.2	1.3	0.2	21.8
Visual, OBJ	0.5	1.6	6.5	0.5 ms	11.4	6.3	1.6	0.3	28.0

Board Repo: OLIMEX/ESP32-S3-DevKit-LiPo Board: ESP32-S3-DevKit-LiPo_Rev_B.kicad_pcb Folder HARDWARE / ESP32-S3-DevKit-LiPo_Rev_B Complexity 227 / 1000 (size 182, features 45) KESE features through vias, slotted holes, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 54, 1,324, 128 Triangles, simulation 1,241,654 in 82 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 44 MB 551 MB STEP 244 MB 654 MB STL 62 MB 609 MB OBJ 131 MB 859 MB Visual GLB 37 MB 710 MB OBJ 111 MB 852 MB

1898. ESP32-SBC-FabGL_Rev_A

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.8	9.4	0.8 ms	7.8	0.4	0.9	0.3	21.0
Simulation, STEP	0.4	1.9	9.0	1.0 ms	7.7	4.7	0.9	0.2	24.8
Simulation, STL	0.5	1.6	9.4	0.8 ms	7.4	0.7	0.9	0.2	20.8
Simulation, OBJ	0.5	1.7	9.6	0.7 ms	8.1	9.0	0.9	0.3	30.1
Visual, GLB	0.5	1.8	9.2	0.7 ms	16.3	0.3	2.1	0.2	30.5
Visual, OBJ	0.5	1.7	9.5	0.8 ms	16.6	6.8	2.0	0.3	37.5

Board Repo: OLIMEX/ESP32-SBC-FabGL Board: ESP32-SBC-FabGL_Rev_A.kicad_pcb Folder HARDWARE / Hardware-revision-A Complexity 249 / 1000 (size 194, features 55) KESE features through vias, slotted holes, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 107, 1,402, 264 Triangles, simulation 1,738,592 in 126 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 61 MB 642 MB STEP 313 MB 847 MB STL 87 MB 626 MB OBJ 184 MB 1.2 GB Visual GLB 49 MB 830 MB OBJ 148 MB 1.0 GB

1899. ESP32-SBC-FabGL_Rev_B

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.8	9.4	0.6 ms	7.4	0.3	0.8	0.2	20.5
Simulation, STEP	0.5	1.7	9.6	0.8 ms	7.8	4.8	0.8	0.2	25.4
Simulation, STL	0.5	1.8	9.5	0.6 ms	7.5	0.5	0.8	0.3	20.8
Simulation, OBJ	0.5	1.9	9.3	0.8 ms	7.7	10.1	0.9	0.3	30.6
Visual, GLB	0.5	1.9	9.6	0.9 ms	15.8	0.2	2.1	0.3	30.5
Visual, OBJ	0.5	1.8	9.5	0.8 ms	15.9	8.0	2.7	0.3	38.6

Board Repo: OLIMEX/ESP32-SBC-FabGL Board: ESP32-SBC-FabGL_Rev_B.kicad_pcb Folder HARDWARE / Hardware-revision-B Complexity 249 / 1000 (size 194, features 55) KESE features through vias, slotted holes, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 107, 1,405, 266 Triangles, simulation 1,795,894 in 123 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 63 MB 659 MB STEP 328 MB 860 MB STL 90 MB 672 MB OBJ 190 MB 1.2 GB Visual GLB 51 MB 857 MB OBJ 156 MB 1.1 GB

1900. Flash-e_Rev_C

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.2	4.8	0.6 ms	4.7	0.2	0.6	0.3	12.1
Simulation, STEP	0.4	1.1	4.9	0.3 ms	4.4	3.5	0.7	0.2	15.2
Simulation, STL	0.4	1.1	5.2	0.3 ms	4.6	0.3	0.7	0.3	12.6
Simulation, OBJ	0.3	1.1	5.0	0.3 ms	4.8	7.0	0.7	0.3	19.3
Visual, GLB	0.4	1.1	5.1	0.3 ms	9.1	0.1	1.1	0.3	17.2
Visual, OBJ	0.4	1.1	4.9	0.4 ms	9.2	4.5	1.2	0.3	21.6

Board Repo: OLIMEX/Flash-e Board: Flash-e_Rev_C.kicad_pcb Folder HARDWARE / Flash-e-Rev.C Complexity 288 / 1000 (size 243, features 45) KESE features through vias, filled zones, copper text Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 35, 1,162, 85 Triangles, simulation 1,152,680 in 79 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 40 MB 496 MB STEP 203 MB 571 MB STL 58 MB 487 MB OBJ 120 MB 823 MB Visual GLB 27 MB 561 MB OBJ 81 MB 631 MB

1901. FOSDEM-MUSIC-BOX_RevA

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.6	2.1	0.7 ms	1.8	88 ms	0.3	0.2	5.3
Simulation, STEP	0.2	0.5	2.3	0.3 ms	1.7	1.7	0.3	0.2	7.0
Simulation, STL	0.2	0.5	2.1	0.3 ms	1.9	0.1	0.3	0.2	5.5
Simulation, OBJ	0.2	0.6	2.1	0.4 ms	1.8	2.5	0.3	0.2	7.7
Visual, GLB	0.2	0.5	2.2	0.3 ms	4.0	51 ms	0.6	0.2	7.8
Visual, OBJ	0.2	0.6	2.2	0.3 ms	4.0	1.7	0.6	0.3	9.5

Board Repo: OLIMEX/FOSDEM-MUSIC-BOX Board: FOSDEM-MUSIC-BOX_RevA.kicad_pcb Folder HARDWARE / FOSDEM-MUSIC-BOX_RevA Complexity 195 / 1000 (size 130, features 65) KESE features filled zones, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 6 (20191123) Parts, tracks, vias 23, 122, 0 Triangles, simulation 568,428 in 32 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 20 MB 302 MB STEP 106 MB 347 MB STL 28 MB 309 MB OBJ 58 MB 427 MB Visual GLB 14 MB 358 MB OBJ 40 MB 370 MB

1902. GateMateA1-EVB_Rev_A

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.5	9.1	38.8	2 ms	33.4	1.4	5.2	0.4	90.8
Simulation, STEP	2.6	9.3	40.4	1.0 ms	33.3	18.8	5.0	0.4	109.8
Simulation, STL	2.6	9.2	38.7	1.0 ms	33.0	3.0	5.5	0.4	92.3
Simulation, OBJ	2.5	9.1	38.8	0.9 ms	32.5	43.9	5.2	0.4	132.5
Visual, GLB	2.4	8.9	38.6	1 ms	79.8	0.8	9.6	0.3	140.5
Visual, OBJ	2.6	9.4	38.8	0.9 ms	76.6	29.4	8.7	0.4	165.8

Board Repo: OLIMEX/GateMateA1-EVB Board: GateMateA1-EVB_Rev_A.kicad_pcb Folder HARDWARE / GateMateA1-EVB-Rev.A Complexity 427 / 1000 (size 302, features 125) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper text, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 267, 8,244, 1,191 Triangles, simulation 7,054,476 in 301 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 246 MB 2.0 GB STEP 1.1 GB 2.5 GB STL 353 MB 2.0 GB OBJ 767 MB 4.6 GB Visual GLB 167 MB 2.6 GB OBJ 537 MB 3.5 GB

1903. GateMateA1-EVB_Rev_B

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.2	8.3	36.7	1.0 ms	30.0	1.6	5.6	0.5	84.9
Simulation, STEP	2.5	8.8	37.5	1 ms	29.1	16.8	5.1	0.4	100.2
Simulation, STL	1.9	8.6	35.7	1 ms	29.2	3.4	5.4	0.5	84.7
Simulation, OBJ	1.9	8.4	37.1	3 ms	29.3	39.5	5.1	0.5	121.9
Visual, GLB	2.3	8.1	34.7	0.9 ms	75.6	0.8	9.8	0.4	131.8
Visual, OBJ	2.4	8.7	35.2	1 ms	75.5	27.3	9.5	0.3	159.0

Board Repo: OLIMEX/GateMateA1-EVB Board: GateMateA1-EVB_Rev_B.kicad_pcb Folder HARDWARE / GateMateA1-EVB-Rev.B Complexity 428 / 1000 (size 303, features 125) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper text, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 268, 9,050, 1,267 Triangles, simulation 7,178,598 in 302 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 250 MB 2.0 GB STEP 1.2 GB 2.6 GB STL 359 MB 2.1 GB OBJ 780 MB 4.7 GB Visual GLB 171 MB 2.6 GB OBJ 549 MB 3.6 GB

1904. GateMateA1-EVB_Rev_C

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.6	10.0	40.4	1 ms	33.2	1.5	5.7	0.4	93.8
Simulation, STEP	2.5	9.6	41.7	1.0 ms	33.9	19.2	5.2	0.4	112.5
Simulation, STL	2.5	9.7	41.5	1 ms	33.2	3.6	6.4	0.5	97.4
Simulation, OBJ	2.8	9.7	42.1	1 ms	34.2	51.4	5.8	0.4	146.2
Visual, GLB	2.5	9.7	41.6	2 ms	82.5	0.8	8.7	0.4	146.2
Visual, OBJ	2.6	9.6	40.4	1 ms	83.3	31.3	8.7	0.4	176.3

Board Repo: OLIMEX/GateMateA1-EVB Board: GateMateA1-EVB_Rev_C.kicad_pcb Folder HARDWARE / GateMateA1-EVB-Rev.C Complexity 429 / 1000 (size 304, features 125) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper text, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 268, 9,108, 1,267 Triangles, simulation 7,169,180 in 302 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 250 MB 2.1 GB STEP 1.1 GB 2.6 GB STL 358 MB 2.0 GB OBJ 779 MB 4.7 GB Visual GLB 171 MB 2.6 GB OBJ 548 MB 3.4 GB

1905. ICE40-ADC_Rev_A

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.2	5.6	5 ms	4.1	0.2	0.5	0.3	12.2
Simulation, STEP	0.3	1.1	5.4	0.3 ms	4.3	3.3	0.6	0.3	15.2
Simulation, STL	0.3	1.2	5.2	0.3 ms	4.1	0.4	0.6	0.3	12.1
Simulation, OBJ	0.3	1.2	5.6	0.5 ms	4.2	6.1	0.6	0.3	18.1
Visual, GLB	0.3	1.1	5.3	0.6 ms	9.8	0.1	1.2	0.3	18.2
Visual, OBJ	0.3	1.2	5.4	0.4 ms	9.7	5.1	1.3	0.3	23.2

Board Repo: OLIMEX/iCE40-ADC Board: ICE40-ADC_Rev_A.kicad_pcb Complexity 216 / 1000 (size 181, features 35) KESE features through vias, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20170123) Parts, tracks, vias 43, 1,220, 192 Triangles, simulation 1,044,008 in 65 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 36 MB 433 MB STEP 187 MB 507 MB STL 52 MB 440 MB OBJ 108 MB 743 MB Visual GLB 28 MB 595 MB OBJ 83 MB 640 MB

1906. ICE40-DAC_Rev_A1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.9	4.6	0.8 ms	3.5	0.2	0.5	0.3	10.3
Simulation, STEP	0.3	1.0	4.6	0.6 ms	3.4	2.8	0.5	0.3	12.9
Simulation, STL	0.3	0.9	4.5	0.5 ms	3.6	0.3	0.5	0.2	10.4
Simulation, OBJ	0.3	0.9	4.5	0.8 ms	3.5	5.1	0.6	0.2	15.0
Visual, GLB	0.3	0.9	4.4	0.7 ms	9.2	0.1	1.2	0.2	16.4
Visual, OBJ	0.3	0.9	4.4	0.7 ms	9.1	4.0	0.9	0.2	19.7

Board Repo: OLIMEX/iCE40-DAC Board: ICE40-DAC_Rev_A1.kicad_pcb Folder Hardware revision A1 Complexity 212 / 1000 (size 177, features 35) KESE features through vias, filled zones Tested 9th November 2026 to 10th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 39, 1,005, 166 Triangles, simulation 1,063,228 in 72 parts Verifier PASS in all six runs Run again Visual, GLB; Visual, OBJ: failed in the corpus run, run again with fixes to KESE made after the corpus run, and passed

File type File size Peak memory used Simulation GLB 37 MB 467 MB STEP 195 MB 518 MB STL 53 MB 470 MB OBJ 109 MB 753 MB Visual GLB 28 MB 608 MB OBJ 82 MB 631 MB

1907. ICE40-DAC_Rev_A

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.9	4.2	0.9 ms	3.2	0.2	0.5	0.3	9.5
Simulation, STEP	0.3	0.8	4.0	1 ms	3.0	2.5	0.5	0.2	11.3
Simulation, STL	0.2	0.9	4.2	0.7 ms	3.2	0.4	0.5	0.2	9.6
Simulation, OBJ	0.3	0.8	3.9	0.6 ms	3.2	4.7	0.5	0.3	13.7
Visual, GLB	0.2	0.7	4.1	0.8 ms	7.7	0.1	1.1	0.2	14.1
Visual, OBJ	0.3	0.8	4.0	0.9 ms	7.8	3.4	1.1	0.2	17.7

Board Repo: OLIMEX/iCE40-DAC Board: ICE40-DAC_Rev_A.kicad_pcb Complexity 212 / 1000 (size 177, features 35) KESE features through vias, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20170123) Parts, tracks, vias 39, 1,005, 166 Triangles, simulation 1,030,836 in 72 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 36 MB 467 MB STEP 194 MB 529 MB STL 52 MB 456 MB OBJ 106 MB 710 MB Visual GLB 27 MB 570 MB OBJ 80 MB 565 MB

1908. ICE40-DIO_Rev_A

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.5	7.8	0.5 ms	5.9	0.2	0.9	0.3	16.9
Simulation, STEP	0.4	1.4	7.6	0.5 ms	5.2	4.2	0.8	0.3	19.8
Simulation, STL	0.4	1.4	7.5	0.6 ms	5.1	0.4	0.7	0.2	15.7
Simulation, OBJ	0.4	1.4	7.7	0.7 ms	5.3	8.5	0.8	0.3	24.4
Visual, GLB	0.4	1.5	7.7	0.8 ms	12.8	0.2	1.4	0.3	24.2
Visual, OBJ	0.4	1.4	7.5	0.6 ms	12.7	6.5	1.3	0.3	30.2

Board Repo: OLIMEX/iCE40-DIO Board: ICE40-DIO_Rev_A.kicad_pcb Complexity 266 / 1000 (size 231, features 35) KESE features through vias, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20170123) Parts, tracks, vias 41, 1,703, 205 Triangles, simulation 1,473,352 in 89 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 51 MB 580 MB STEP 258 MB 686 MB STL 74 MB 587 MB OBJ 154 MB 984 MB Visual GLB 39 MB 726 MB OBJ 118 MB 880 MB

1909. ICE40-IO_Rev_A

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.0	4.7	0.6 ms	3.5	0.2	0.5	0.3	10.5
Simulation, STEP	0.3	1.0	4.7	0.5 ms	3.5	2.8	0.5	0.2	13.0
Simulation, STL	0.3	1.0	4.6	0.7 ms	3.5	0.2	0.5	0.2	10.3
Simulation, OBJ	0.3	1.0	4.6	0.7 ms	3.4	5.7	0.5	0.3	15.8
Visual, GLB	0.4	1.2	4.9	0.6 ms	7.8	0.1	0.8	0.2	15.4
Visual, OBJ	0.4	1.1	5.1	0.5 ms	7.9	4.3	0.7	0.2	19.6

Board Repo: OLIMEX/iCE40-IO Board: ICE40-IO_Rev_A.kicad_pcb Complexity 206 / 1000 (size 171, features 35) KESE features through vias, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20170123) Parts, tracks, vias 33, 751, 146 Triangles, simulation 1,043,876 in 64 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 36 MB 451 MB STEP 185 MB 529 MB STL 52 MB 450 MB OBJ 107 MB 736 MB Visual GLB 27 MB 583 MB OBJ 80 MB 600 MB

1910. ICE40-1KEVB_Rev_A

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.6	2.8	0.4 ms	1.8	96 ms	0.4	0.3	6.2
Simulation, STEP	0.3	0.7	2.9	0.3 ms	1.7	1.8	0.3	0.2	7.9
Simulation, STL	0.3	0.6	2.9	0.6 ms	1.7	0.1	0.3	0.3	6.1
Simulation, OBJ	0.2	0.6	2.6	0.4 ms	1.8	2.3	0.2	0.3	8.0
Visual, GLB	0.3	0.6	2.9	0.4 ms	4.2	57 ms	0.5	0.2	8.8
Visual, OBJ	0.2	0.7	3.0	2 ms	4.6	1.7	0.6	0.2	10.9

Board Repo: OLIMEX/iCE40HX1K-EVB Board: ICE40-1KEVB_Rev_A.kicad_pcb Complexity 102 / 1000 (size 102, features 0) Tested 9th November 2026 Copper layers 2 File format KiCad 4 (4) Parts, tracks, vias 67, 0, 0 Triangles, simulation 457,628 in 106 parts Note mostly unrouted Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 16 MB 301 MB STEP 69 MB 333 MB STL 23 MB 295 MB OBJ 48 MB 370 MB Visual GLB 11 MB 320 MB OBJ 31 MB 323 MB

1911. iCE40HX1K-EVB_Rev_B

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	2.3	8.1	1.0 ms	7.6	0.4	1.1	0.2	20.2
Simulation, STEP	0.5	2.2	7.9	0.6 ms	7.9	5.3	1.2	0.3	25.3
Simulation, STL	0.6	2.2	7.6	0.8 ms	7.8	0.7	1.1	0.3	20.3
Simulation, OBJ	0.6	2.4	7.7	0.9 ms	7.3	12.4	1.2	0.3	31.8
Visual, GLB	0.5	2.2	7.5	0.8 ms	17.4	0.2	1.7	0.3	29.9
Visual, OBJ	0.5	2.4	7.9	0.6 ms	17.6	8.7	1.9	0.2	39.3

Board Repo: OLIMEX/iCE40HX1K-EVB Board: iCE40HX1K-EVB_Rev_B.kicad_pcb Complexity 281 / 1000 (size 236, features 45) KESE features through vias, slotted holes, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 4 (4) Parts, tracks, vias 71, 2,527, 279 Triangles, simulation 1,966,590 in 110 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 68 MB 678 MB STEP 295 MB 808 MB STL 98 MB 716 MB OBJ 210 MB 1.3 GB Visual GLB 46 MB 886 MB OBJ 142 MB 1.0 GB

1912. iCE40HX8K-EVB_Rev_B

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.0	6.7	20.4	1 ms	21.2	0.9	3.1	0.4	53.7
Simulation, STEP	1.1	6.4	20.6	0.8 ms	21.4	12.5	3.1	0.4	65.5
Simulation, STL	1.1	7.0	20.8	0.8 ms	21.3	1.8	3.2	0.4	55.5
Simulation, OBJ	1.2	6.4	20.4	2 ms	21.3	31.9	3.2	0.3	84.8
Visual, GLB	1.2	6.5	20.9	3 ms	54.2	0.6	6.1	0.3	89.8
Visual, OBJ	1.1	6.6	20.6	2 ms	53.9	22.1	6.1	0.4	110.8

Board Repo: OLIMEX/iCE40HX8K-EVB Board: iCE40HX8K-EVB_Rev_B.kicad_pcb Folder HARDWARE / REV-B Complexity 314 / 1000 (size 269, features 45) KESE features through vias, slotted holes, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20160815) Parts, tracks, vias 96, 7,178, 863 Triangles, simulation 4,942,670 in 246 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 171 MB 1.5 GB STEP 730 MB 1.7 GB STL 247 MB 1.6 GB OBJ 540 MB 3.2 GB Visual GLB 115 MB 1.8 GB OBJ 371 MB 2.5 GB

1913. iCE40HX8K-EVB_Rev_B1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.1	6.3	19.0	1 ms	19.8	0.9	3.1	0.4	50.7
Simulation, STEP	1.2	6.4	18.9	1 ms	19.9	12.1	2.9	0.3	61.7
Simulation, STL	1.1	6.2	18.5	0.8 ms	19.7	2.1	3.2	0.3	51.1
Simulation, OBJ	1.1	6.1	18.3	1 ms	19.7	30.7	2.9	0.3	79.1
Visual, GLB	1.1	6.1	18.7	0.8 ms	49.3	0.6	6.6	0.3	82.7
Visual, OBJ	1.2	6.2	19.1	0.7 ms	49.7	20.2	6.3	0.3	103.0

Board Repo: OLIMEX/iCE40HX8K-EVB Board: iCE40HX8K-EVB_Rev_B1.kicad_pcb Folder HARDWARE / REV-B1 Complexity 314 / 1000 (size 269, features 45) KESE features through vias, slotted holes, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 96, 7,178, 863 Triangles, simulation 5,101,374 in 247 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 177 MB 1.5 GB STEP 734 MB 1.8 GB STL 255 MB 1.5 GB OBJ 558 MB 3.3 GB Visual GLB 117 MB 2.0 GB OBJ 377 MB 2.6 GB

1914. iMX8MPLUS-SOM_Rev_B

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.1	8.8	31.9	1 ms	34.9	1.9	6.3	0.5	86.4
Simulation, STEP	1.9	8.8	32.3	1 ms	34.7	21.0	5.7	0.4	104.8
Simulation, STL	2.0	9.1	32.8	1 ms	37.6	3.8	6.2	0.4	91.9
Simulation, OBJ	2.1	9.0	32.4	1 ms	36.2	56.3	5.6	0.4	141.9
Visual, GLB	1.9	8.8	31.9	2 ms	80.4	0.9	8.1	0.3	132.4
Visual, OBJ	1.9	8.9	31.8	1 ms	76.6	31.8	8.1	0.4	159.5

Board Repo: OLIMEX/iMX8MP-SOM Board: iMX8MPLUS-SOM_Rev_B.kicad_pcb Folder HARDWARE / iMX8MP-SOM-xGB-IND Complexity 363 / 1000 (size 318, features 45) KESE features through vias, filled zones, copper text Tested 9th November 2026 Copper layers 6 File format KiCad 5 (20171130) Parts, tracks, vias 203, 11,532, 988 Triangles, simulation 8,457,830 in 438 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 294 MB 2.2 GB STEP 1.2 GB 2.8 GB STL 423 MB 2.3 GB OBJ 916 MB 5.4 GB Visual GLB 163 MB 2.6 GB OBJ 535 MB 3.4 GB

1915. iMX8MPLUS-SOM-EVB_Rev_B

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.1	8.3	36.6	1 ms	27.3	1.3	4.8	0.3	80.8
Simulation, STEP	2.1	8.6	36.5	0.9 ms	27.4	17.8	4.2	0.3	96.9
Simulation, STL	2.0	8.4	36.4	0.9 ms	27.7	2.4	4.7	0.3	81.9
Simulation, OBJ	2.2	8.6	35.7	1 ms	27.6	51.1	4.7	0.4	130.4
Visual, GLB	2.2	8.7	37.6	2 ms	81.9	0.8	10.2	0.3	141.6
Visual, OBJ	2.2	8.8	37.1	1 ms	81.0	31.4	9.6	0.4	170.5

Board Repo: OLIMEX/iMX8MP-SOM-EVB Board: iMX8MPLUS-SOM-EVB_Rev_B.kicad_pcb Folder HARDWARE / iMX8MP-SOM-EVB-rev.b Complexity 364 / 1000 (size 299, features 65) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 317, 7,518, 1,183 Triangles, simulation 7,608,794 in 443 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 265 MB 2.3 GB STEP 1.1 GB 2.9 GB STL 380 MB 2.2 GB OBJ 824 MB 4.9 GB Visual GLB 184 MB 2.8 GB OBJ 592 MB 3.7 GB

1916. Lime2-SHIELD_RevC

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.2	3.4	0.5 ms	3.7	0.2	0.5	0.3	9.7
Simulation, STEP	0.3	1.1	3.2	0.4 ms	3.5	2.7	0.5	0.2	11.7
Simulation, STL	0.3	1.0	3.2	0.6 ms	3.5	0.3	0.5	0.2	9.0
Simulation, OBJ	0.4	1.2	3.1	0.5 ms	3.5	5.3	0.5	0.3	14.3
Visual, GLB	0.4	1.2	3.1	0.5 ms	8.3	0.1	1.1	0.3	14.5
Visual, OBJ	0.4	1.1	3.2	0.4 ms	8.1	4.3	0.9	0.2	18.4

Board Repo: OLIMEX/LIME2-SHIELD Board: Lime2-SHIELD_RevC.kicad_pcb Folder HARDWARE / Lime2-SHIELD-Rev.C Complexity 232 / 1000 (size 187, features 45) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 39, 689, 117 Triangles, simulation 1,041,168 in 165 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 37 MB 482 MB STEP 165 MB 581 MB STL 52 MB 474 MB OBJ 109 MB 779 MB Visual GLB 27 MB 639 MB OBJ 83 MB 627 MB

1917. LoRa_RevA

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.5	1.6	0.6 ms	1.3	49 ms	0.2	0.2	3.9
Simulation, STEP	0.2	0.4	1.6	0.5 ms	1.3	1.3	0.2	0.2	5.2
Simulation, STL	0.1	0.5	1.7	0.2 ms	1.2	83 ms	0.2	0.2	3.9
Simulation, OBJ	0.2	0.5	1.7	0.8 ms	1.2	1.6	0.2	0.2	5.4
Visual, GLB	0.2	0.5	1.6	0.5 ms	3.1	39 ms	0.3	0.2	5.8
Visual, OBJ	0.2	0.5	1.5	0.3 ms	3.0	1.0	0.3	0.2	6.7

Board Repo: OLIMEX/LoRa-868-915 Board: LoRa_RevA.kicad_pcb Folder HARDWARE / LoRa-Rev-A Complexity 265 / 1000 (size 195, features 70) KESE features through vias, slotted holes, custom pads, filled zones, copper drawings Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 31, 322, 45 Triangles, simulation 350,196 in 40 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 13 MB 260 MB STEP 63 MB 265 MB STL 18 MB 264 MB OBJ 37 MB 283 MB Visual GLB 8.5 MB 255 MB OBJ 25 MB 242 MB

1918. LoRa_RevB

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	1.7	0.2 ms	1.3	66 ms	0.2	0.2	4.0
Simulation, STEP	0.2	0.4	1.7	0.2 ms	1.3	1.3	0.2	0.2	5.3
Simulation, STL	0.2	0.4	1.7	0.3 ms	1.4	0.1	0.2	0.2	4.1
Simulation, OBJ	0.2	0.4	1.6	0.3 ms	1.3	1.8	0.2	0.2	5.7
Visual, GLB	0.2	0.4	1.7	0.3 ms	3.1	44 ms	0.4	0.2	5.9
Visual, OBJ	0.1	0.4	1.8	0.3 ms	3.3	1.3	0.3	0.2	7.4

Board Repo: OLIMEX/LoRa-868-915 Board: LoRa_RevB.kicad_pcb Folder HARDWARE / LoRa-Rev-B Complexity 261 / 1000 (size 191, features 70) KESE features through vias, slotted holes, custom pads, filled zones, copper drawings Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 26, 270, 45 Triangles, simulation 371,904 in 41 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 13 MB 265 MB STEP 67 MB 275 MB STL 19 MB 261 MB OBJ 39 MB 304 MB Visual GLB 9.1 MB 249 MB OBJ 27 MB 266 MB

1919. MOD-LoRa_RevB

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	1.2	0.3 ms	1.1	48 ms	0.1	0.2	3.1
Simulation, STEP	0.2	0.3	1.1	0.2 ms	1.0	1.0	0.1	0.2	4.0
Simulation, STL	0.1	0.3	1.2	0.2 ms	1.0	63 ms	0.2	0.3	3.1
Simulation, OBJ	0.1	0.3	1.1	0.1 ms	1.0	1.4	0.2	0.2	4.4
Visual, GLB	0.2	0.3	1.2	0.2 ms	2.5	39 ms	0.2	0.2	4.6
Visual, OBJ	0.2	0.3	1.2	0.2 ms	2.5	1.1	0.2	0.2	5.6

Board Repo: OLIMEX/LoRa-868-915 Board: MOD-LoRa_RevB.kicad_pcb Folder HARDWARE / MOD-LoRa-Rev-B Complexity 235 / 1000 (size 190, features 45) KESE features through vias, slotted holes, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 25, 237, 51 Triangles, simulation 251,278 in 39 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 9.3 MB 226 MB STEP 44 MB 256 MB STL 13 MB 232 MB OBJ 26 MB 226 MB Visual GLB 7.1 MB 215 MB OBJ 20 MB 213 MB

1920. STM32WL-DevKit_RevB

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.9	4.7	0.3 ms	4.5	0.2	0.6	0.2	11.5
Simulation, STEP	0.3	0.9	4.8	0.5 ms	4.3	2.7	0.6	0.2	13.9
Simulation, STL	0.4	1.1	4.5	0.4 ms	4.4	0.3	0.6	0.2	11.6
Simulation, OBJ	0.3	1.0	4.6	0.3 ms	4.2	6.2	0.6	0.3	17.2
Visual, GLB	0.4	1.1	4.6	0.5 ms	8.8	0.1	0.9	0.2	16.2
Visual, OBJ	0.4	1.0	4.6	0.4 ms	11.0	4.7	1.3	0.3	23.3

Board Repo: OLIMEX/LoRa-STM32WL-DevKIT Board: STM32WL-DevKit_RevB.kicad_pcb Folder HARDWARE / LoRa-STM32WL-DevKIT / LoRa-STM32WL-DevKit-RevB Complexity 308 / 1000 (size 228, features 80) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 49, 640, 110 Triangles, simulation 1,098,314 in 74 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 37 MB 449 MB STEP 167 MB 573 MB STL 55 MB 445 MB OBJ 112 MB 801 MB Visual GLB 26 MB 634 MB OBJ 77 MB 629 MB

1921. LoRa-STM32WL-DevKit_RevD1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.1	5.0	0.4 ms	3.9	0.2	0.5	0.2	11.3
Simulation, STEP	0.3	1.0	5.1	0.4 ms	4.0	2.7	0.5	0.2	13.9
Simulation, STL	0.3	1.0	4.8	0.4 ms	3.8	0.2	0.5	0.2	10.9
Simulation, OBJ	0.3	0.9	4.8	0.4 ms	3.8	5.0	0.5	0.2	15.5
Visual, GLB	0.3	1.0	4.7	0.4 ms	8.1	0.1	1.1	0.2	15.6
Visual, OBJ	0.3	1.1	4.7	0.4 ms	8.1	4.1	1.1	0.2	19.7

Board Repo: OLIMEX/LoRa-STM32WL-DevKIT Board: LoRa-STM32WL-DevKit_RevD1.kicad_pcb Folder HARDWARE / LoRa-STM32WL-DevKIT / LoRa-STM32WL-DevKit-RevD1 Complexity 271 / 1000 (size 216, features 55) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 54, 739, 137 Triangles, simulation 943,760 in 78 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 33 MB 429 MB STEP 164 MB 541 MB STL 47 MB 451 MB OBJ 97 MB 678 MB Visual GLB 27 MB 571 MB OBJ 80 MB 637 MB

1922. MiniBot_charger_RevA

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.1	0.5	0.1 ms	0.7	22 ms	65 ms	0.2	1.7
Simulation, STEP	0.1	0.1	0.5	0.1 ms	0.7	0.9	62 ms	0.2	2.5
Simulation, STL	0.1	0.1	0.5	0.1 ms	0.7	32 ms	67 ms	0.2	1.7
Simulation, OBJ	0.1	0.1	0.6	0.1 ms	0.7	0.6	73 ms	0.2	2.4
Visual, GLB	0.1	0.1	0.5	0.1 ms	1.5	19 ms	0.1	0.2	2.5
Visual, OBJ	0.1	0.1	0.5	0.1 ms	1.5	0.6	0.1	0.2	3.2

Board Repo: OLIMEX/Minibot Board: MiniBot_charger_RevA.kicad_pcb Folder HARDWARE / charger Complexity 168 / 1000 (size 123, features 45) KESE features through vias, slotted holes, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 12, 107, 3 Triangles, simulation 117,320 in 27 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 4.3 MB 188 MB STEP 23 MB 201 MB STL 5.9 MB 189 MB OBJ 12 MB 189 MB Visual GLB 3.6 MB 158 MB OBJ 10.0 MB 158 MB

1923. MiniBot_RevA

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.4	1.5	0.2 ms	1.2	56 ms	0.2	0.2	3.7
Simulation, STEP	0.2	0.4	1.5	0.3 ms	1.4	1.5	0.2	0.2	5.4
Simulation, STL	0.2	0.4	1.5	0.2 ms	1.3	82 ms	0.2	0.3	4.0
Simulation, OBJ	0.2	0.4	1.5	0.2 ms	1.3	2.1	0.2	0.3	5.9
Visual, GLB	0.2	0.4	1.4	0.2 ms	3.2	45 ms	0.4	0.2	5.8
Visual, OBJ	0.2	0.4	1.5	0.2 ms	3.2	1.7	0.4	0.2	7.6

Board Repo: OLIMEX/Minibot Board: MiniBot_RevA.kicad_pcb Folder HARDWARE Complexity 202 / 1000 (size 147, features 55) KESE features through vias, slotted holes, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 27, 251, 19 Triangles, simulation 312,404 in 29 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 11 MB 243 MB STEP 60 MB 262 MB STL 16 MB 244 MB OBJ 32 MB 263 MB Visual GLB 8.8 MB 244 MB OBJ 26 MB 256 MB

1924. MIPI-HDMI_Rev_B

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.8	2.9	0.3 ms	2.7	0.1	0.4	0.2	7.5
Simulation, STEP	0.3	0.8	2.9	0.2 ms	2.5	1.9	0.3	0.2	8.9
Simulation, STL	0.3	0.9	2.9	0.3 ms	2.6	0.3	0.4	0.2	7.5
Simulation, OBJ	0.3	0.8	3.2	0.3 ms	2.6	3.8	0.4	0.2	11.3
Visual, GLB	0.3	0.8	3.0	0.3 ms	6.5	0.1	0.8	0.2	11.8
Visual, OBJ	0.3	0.8	3.1	0.2 ms	6.2	2.7	0.6	0.2	14.0

Board Repo: OLIMEX/MIPI-HDMI Board: MIPI-HDMI_Rev_B.kicad_pcb Folder HARDWARE / MIPI-HDMI-Rev.B Complexity 342 / 1000 (size 237, features 105) KESE features through vias, slotted holes, filled zones, copper text, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 55, 1,070, 162 Triangles, simulation 962,002 in 86 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 34 MB 441 MB STEP 146 MB 518 MB STL 48 MB 460 MB OBJ 100 MB 703 MB Visual GLB 23 MB 539 MB OBJ 71 MB 589 MB

1925. MOD-BME280_RevA

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.1	0.4	0.1 ms	0.5	16 ms	44 ms	0.2	1.4
Simulation, STEP	0.1	0.1	0.4	0.1 ms	0.5	0.8	60 ms	0.2	2.2
Simulation, STL	0.1	0.1	0.4	0.1 ms	0.5	22 ms	47 ms	0.2	1.5
Simulation, OBJ	95 ms	0.1	0.5	0.1 ms	0.5	0.5	53 ms	0.2	2.0
Visual, GLB	98 ms	0.1	0.4	0.1 ms	1.1	14 ms	90 ms	0.2	2.1
Visual, OBJ	0.1	0.2	0.4	0.2 ms	1.0	0.4	82 ms	0.2	2.4

Board Repo: OLIMEX/MOD-BME280 Board: MOD-BME280_RevA.kicad_pcb Folder HARDWARE / MOD-BME280-Rev.A1 Complexity 154 / 1000 (size 119, features 35) KESE features through vias, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20170123) Parts, tracks, vias 8, 95, 7 Triangles, simulation 76,542 in 21 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 2.9 MB 177 MB STEP 14 MB 190 MB STL 3.8 MB 180 MB OBJ 7.8 MB 182 MB Visual GLB 2.5 MB 155 MB OBJ 6.9 MB 155 MB

1926. MOD-BME280_RevB

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.1	0.4	0.1 ms	0.5	25 ms	65 ms	0.2	1.6
Simulation, STEP	0.1	0.1	0.5	0.1 ms	0.6	0.9	48 ms	0.2	2.5
Simulation, STL	0.1	0.1	0.4	0.1 ms	0.5	25 ms	49 ms	0.2	1.6
Simulation, OBJ	0.1	0.2	0.5	0.1 ms	0.6	0.5	55 ms	0.2	2.1
Visual, GLB	0.1	0.2	0.5	0.1 ms	1.3	16 ms	0.1	0.3	2.5
Visual, OBJ	0.1	0.2	0.5	0.1 ms	1.2	0.4	96 ms	0.3	2.8

Board Repo: OLIMEX/MOD-BME280 Board: MOD-BME280_RevB.kicad_pcb Folder HARDWARE / MOD-BME280-Rev.B Complexity 163 / 1000 (size 118, features 45) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 8, 93, 7 Triangles, simulation 80,616 in 19 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 3.0 MB 189 MB STEP 15 MB 188 MB STL 4.0 MB 189 MB OBJ 8.2 MB 186 MB Visual GLB 2.6 MB 154 MB OBJ 7.3 MB 155 MB

1927. MOD-ENV_revB

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.4	0.1 ms	0.6	21 ms	73 ms	0.2	1.6
Simulation, STEP	0.1	0.2	0.4	0.1 ms	0.7	0.8	61 ms	0.2	2.4
Simulation, STL	0.1	0.2	0.4	0.1 ms	0.6	53 ms	61 ms	0.2	1.6
Simulation, OBJ	0.1	0.2	0.4	0.1 ms	0.7	0.6	64 ms	0.2	2.2
Visual, GLB	0.1	0.2	0.4	0.1 ms	1.3	22 ms	0.2	0.2	2.4
Visual, OBJ	0.1	0.2	0.4	0.1 ms	1.2	0.5	0.1	0.2	2.8

Board Repo: OLIMEX/MOD-ENV Board: MOD-ENV_revB.kicad_pcb Folder HARDWARE / REV-B Complexity 188 / 1000 (size 133, features 55) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 13, 167, 15 Triangles, simulation 140,154 in 23 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 5.1 MB 200 MB STEP 26 MB 216 MB STL 7.0 MB 201 MB OBJ 14 MB 201 MB Visual GLB 4.3 MB 178 MB OBJ 12 MB 179 MB

1928. MOD-ESP32-C5_Rev_A

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.6	1.9	0.3 ms	1.5	73 ms	0.2	0.2	4.8
Simulation, STEP	0.3	0.6	1.9	0.4 ms	1.5	1.5	0.3	0.2	6.3
Simulation, STL	0.3	0.6	2.0	0.3 ms	1.5	0.1	0.3	0.2	5.0
Simulation, OBJ	0.3	0.6	1.8	0.3 ms	1.5	2.5	0.3	0.2	7.1
Visual, GLB	0.3	0.6	2.0	0.7 ms	4.1	65 ms	0.5	0.2	7.8
Visual, OBJ	0.3	0.6	1.9	0.5 ms	4.0	2.1	0.5	0.2	9.6

Board Repo: OLIMEX/MOD-ESP32-C5 Board: MOD-ESP32-C5_Rev_A.kicad_pcb Folder HARDWARE / MOD-ESP32-C5.Rev.A Complexity 274 / 1000 (size 169, features 105) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 26, 873, 107 Triangles, simulation 437,814 in 54 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 16 MB 298 MB STEP 73 MB 323 MB STL 22 MB 292 MB OBJ 45 MB 351 MB Visual GLB 13 MB 341 MB OBJ 39 MB 337 MB

1929. MOD-IR-TEMP_RevA

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	91 ms	89 ms	0.3	0.1 ms	0.5	16 ms	42 ms	0.2	1.2
Simulation, STEP	85 ms	0.1	0.4	0.1 ms	0.5	0.7	38 ms	0.2	2.0
Simulation, STL	85 ms	89 ms	0.4	0.2 ms	0.5	18 ms	37 ms	0.2	1.3
Simulation, OBJ	0.1	0.1	0.3	0.1 ms	0.4	0.4	41 ms	0.2	1.6
Visual, GLB	95 ms	99 ms	0.4	0.1 ms	1.1	11 ms	71 ms	0.2	2.0
Visual, OBJ	85 ms	95 ms	0.4	0.1 ms	1.1	0.3	73 ms	0.2	2.3

Board Repo: OLIMEX/MOD-IR-TEMP Board: MOD-IR-TEMP_RevA.kicad_pcb Folder HARDWARE / REV.A Complexity 138 / 1000 (size 103, features 35) KESE features through vias, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20160815) Parts, tracks, vias 6, 42, 4 Triangles, simulation 65,598 in 22 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 2.4 MB 172 MB STEP 11 MB 176 MB STL 3.3 MB 171 MB OBJ 6.6 MB 172 MB Visual GLB 1.8 MB 153 MB OBJ 5.0 MB 151 MB

1930. MOD-LCD2.8RTP_RevB

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.6	2.3	0.2 ms	1.9	75 ms	0.2	0.2	5.6
Simulation, STEP	0.2	0.6	2.4	0.2 ms	1.9	1.9	0.2	0.2	7.4
Simulation, STL	0.2	0.7	2.4	0.2 ms	2.1	0.1	0.2	0.2	6.0
Simulation, OBJ	0.2	0.7	2.3	0.2 ms	1.9	2.7	0.2	0.3	8.4
Visual, GLB	0.2	0.7	2.3	0.3 ms	4.0	64 ms	0.5	0.3	8.2
Visual, OBJ	0.2	0.7	2.5	0.2 ms	4.0	2.3	0.7	0.3	10.6

Board Repo: OLIMEX/MOD-LCD2.8RTP Board: MOD-LCD2.8RTP_RevB.kicad_pcb Folder HARDWARE / SCHEMATICS / Hardware-revision-B Complexity 193 / 1000 (size 158, features 35) KESE features through vias, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 24, 490, 60 Triangles, simulation 384,728 in 45 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 14 MB 300 MB STEP 72 MB 336 MB STL 19 MB 290 MB OBJ 40 MB 327 MB Visual GLB 12 MB 341 MB OBJ 36 MB 337 MB

1931. MOD-LCD2.8RTP_Rev_C

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.2	3.3	0.4 ms	2.4	0.1	0.4	0.2	8.0
Simulation, STEP	0.3	1.2	3.5	0.2 ms	2.4	2.0	0.3	0.2	10.0
Simulation, STL	0.3	1.3	3.3	0.2 ms	2.4	0.2	0.4	0.2	8.1
Simulation, OBJ	0.3	1.3	3.4	0.2 ms	2.4	3.6	0.3	0.2	11.5
Visual, GLB	0.3	1.2	3.5	0.4 ms	5.1	92 ms	0.5	0.2	11.0
Visual, OBJ	0.3	1.3	3.3	0.3 ms	5.1	2.9	0.5	0.2	13.6

Board Repo: OLIMEX/MOD-LCD2.8RTP Board: MOD-LCD2.8RTP_Rev_C.kicad_pcb Folder HARDWARE / SCHEMATICS / Hardware-revision-C Complexity 229 / 1000 (size 174, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 27, 821, 284 Triangles, simulation 677,624 in 45 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 24 MB 401 MB STEP 98 MB 496 MB STL 34 MB 412 MB OBJ 70 MB 485 MB Visual GLB 20 MB 493 MB OBJ 60 MB 540 MB

1932. MOD-LCD2.8RTP_Rev_D

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.7	1.8	0.3 ms	1.6	56 ms	0.2	0.2	4.8
Simulation, STEP	0.4	0.7	1.9	0.4 ms	1.7	1.5	0.2	0.2	6.6
Simulation, STL	0.3	0.7	1.8	0.3 ms	1.7	0.1	0.2	0.2	4.9
Simulation, OBJ	0.4	0.7	1.9	0.3 ms	1.7	2.1	0.2	0.2	7.2
Visual, GLB	0.2	0.8	2.0	0.3 ms	3.7	52 ms	0.5	0.2	7.5
Visual, OBJ	0.3	0.8	1.6	0.3 ms	3.8	1.9	0.6	0.2	9.2

Board Repo: OLIMEX/MOD-LCD2.8RTP Board: MOD-LCD2.8RTP_Rev_D.kicad_pcb Folder HARDWARE / SCHEMATICS / Hardware-revision-D Complexity 262 / 1000 (size 162, features 100) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 26, 413, 121 Triangles, simulation 409,860 in 42 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 15 MB 305 MB STEP 72 MB 353 MB STL 20 MB 297 MB OBJ 42 MB 346 MB Visual GLB 12 MB 346 MB OBJ 36 MB 345 MB

1933. mod-mpu9150

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.8	0.2 ms	0.8	32 ms	0.1	0.2	2.3
Simulation, STEP	0.1	0.2	0.8	0.2 ms	0.8	0.9	0.1	0.2	3.1
Simulation, STL	0.1	0.2	0.8	0.1 ms	0.8	44 ms	0.1	0.2	2.2
Simulation, OBJ	0.1	0.2	0.8	0.2 ms	0.7	1.0	0.1	0.2	3.2
Visual, GLB	0.1	0.2	0.8	0.2 ms	1.9	26 ms	0.2	0.2	3.5
Visual, OBJ	0.1	0.2	0.9	0.2 ms	2.0	0.8	0.2	0.2	4.3

Board Repo: OLIMEX/MOD-MPU9150 Board: mod-mpu9150.kicad_pcb Folder HARDWARE / MOD-MPU9150-Rev.A Complexity 163 / 1000 (size 128, features 35) KESE features through vias, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 4 (4) Parts, tracks, vias 14, 125, 9 Triangles, simulation 199,710 in 38 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 7.2 MB 218 MB STEP 39 MB 232 MB STL 10.0 MB 220 MB OBJ 20 MB 217 MB Visual GLB 6.0 MB 214 MB OBJ 17 MB 212 MB

1934. mod-oled-128x64

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.1	0.6	0.1 ms	0.5	25 ms	61 ms	0.2	1.7
Simulation, STEP	0.1	0.2	0.5	0.1 ms	0.5	0.8	50 ms	0.2	2.3
Simulation, STL	0.1	0.1	0.5	0.1 ms	0.5	23 ms	49 ms	0.2	1.5
Simulation, OBJ	0.1	0.2	0.5	0.1 ms	0.5	0.5	51 ms	0.2	2.1
Visual, GLB	0.1	0.1	0.6	0.1 ms	1.1	15 ms	95 ms	0.2	2.3
Visual, OBJ	0.1	0.2	0.6	0.1 ms	1.2	0.4	81 ms	0.2	2.7

Board Repo: OLIMEX/MOD-OLED-128x64 Board: mod-oled-128x64.kicad_pcb Folder HARDWARE / MOD-OLED-128x64_Rev.A Complexity 169 / 1000 (size 134, features 35) KESE features through vias, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 4 (4) Parts, tracks, vias 13, 191, 12 Triangles, simulation 97,926 in 30 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 3.6 MB 192 MB STEP 18 MB 196 MB STL 4.9 MB 190 MB OBJ 10 MB 186 MB Visual GLB 3.0 MB 161 MB OBJ 8.2 MB 159 MB

1935. MOD-RTC2_Rev_A

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	84 ms	0.1	0.7	0.2 ms	0.6	21 ms	67 ms	0.2	1.8
Simulation, STEP	96 ms	0.1	0.6	0.2 ms	0.7	0.8	82 ms	0.2	2.6
Simulation, STL	0.1	0.1	0.6	0.1 ms	0.6	38 ms	73 ms	0.3	1.9
Simulation, OBJ	0.1	0.1	0.6	0.1 ms	0.6	0.6	75 ms	0.2	2.4
Visual, GLB	98 ms	0.1	0.6	0.1 ms	1.4	19 ms	0.1	0.2	2.6
Visual, OBJ	88 ms	0.1	0.6	0.2 ms	1.5	0.4	0.1	0.2	3.1

Board Repo: OLIMEX/MOD-RTC2 Board: MOD-RTC2_Rev_A.kicad_pcb Folder Hardware / MOD-RTC2-A Complexity 170 / 1000 (size 125, features 45) KESE features through vias, slotted holes, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171114) Parts, tracks, vias 9, 123, 14 Triangles, simulation 126,452 in 26 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 4.6 MB 194 MB STEP 23 MB 198 MB STL 6.3 MB 185 MB OBJ 13 MB 186 MB Visual GLB 3.5 MB 159 MB OBJ 9.7 MB 159 MB

1936. NB-IoT-DevKit_Rev_B

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	1.9	6.5	1 ms	5.8	0.3	0.8	0.2	16.1
Simulation, STEP	0.6	1.9	6.3	0.7 ms	5.8	4.2	0.8	0.3	19.9
Simulation, STL	0.5	1.9	6.4	0.6 ms	6.1	0.6	0.8	0.2	16.5
Simulation, OBJ	0.6	1.9	6.6	0.9 ms	5.8	9.8	0.8	0.3	25.8
Visual, GLB	0.6	1.9	6.4	0.7 ms	15.2	0.2	1.5	0.2	26.0
Visual, OBJ	0.6	1.9	6.6	1 ms	15.8	6.8	1.7	0.3	33.7

Board Repo: OLIMEX/NB-IoT Board: NB-IoT-DevKit_Rev_B.kicad_pcb Folder HARDWARE / NB-IoT-DevKit_Rev_B Complexity 307 / 1000 (size 217, features 90) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text Tested 9th November 2026 Copper layers 4 File format KiCad 6 (20190905) Parts, tracks, vias 105, 2,707, 203 Triangles, simulation 1,641,942 in 137 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 58 MB 671 MB STEP 263 MB 725 MB STL 82 MB 640 MB OBJ 174 MB 1.1 GB Visual GLB 40 MB 780 MB OBJ 120 MB 968 MB

1937. NB-IoT-DevKit_Rev_C

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.7	5.6	0.6 ms	5.4	0.3	0.7	0.2	14.4
Simulation, STEP	0.5	1.8	5.6	0.7 ms	5.2	3.7	0.8	0.2	17.8
Simulation, STL	0.5	1.7	5.7	1 ms	5.3	0.4	0.8	0.2	14.5
Simulation, OBJ	0.5	1.7	5.5	0.5 ms	5.3	8.6	0.7	0.2	22.5
Visual, GLB	0.5	1.6	5.7	0.6 ms	13.7	0.2	1.2	0.2	23.2
Visual, OBJ	0.5	1.6	5.6	0.6 ms	13.7	5.9	1.4	0.2	29.0

Board Repo: OLIMEX/NB-IoT Board: NB-IoT-DevKit_Rev_C.kicad_pcb Folder HARDWARE / NB-IoT-DevKit_Rev_C Complexity 307 / 1000 (size 217, features 90) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 105, 2,707, 203 Triangles, simulation 1,641,972 in 137 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 58 MB 652 MB STEP 263 MB 725 MB STL 82 MB 675 MB OBJ 174 MB 1.1 GB Visual GLB 40 MB 750 MB OBJ 120 MB 907 MB

1938. NB-IoT-DevKit_Rev_D

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	2.0	6.7	0.9 ms	7.0	0.3	0.9	0.3	17.9
Simulation, STEP	0.7	2.0	7.8	0.7 ms	7.4	5.1	1.0	0.4	24.4
Simulation, STL	0.7	2.2	7.2	0.8 ms	7.4	0.6	1.1	0.3	19.5
Simulation, OBJ	0.6	2.0	6.8	1 ms	6.9	10.7	1.1	0.3	28.3
Visual, GLB	0.7	2.1	6.8	0.6 ms	18.0	0.2	1.8	0.3	30.0
Visual, OBJ	0.6	2.3	7.0	0.9 ms	17.1	7.1	1.7	0.2	36.1

Board Repo: OLIMEX/NB-IoT Board: NB-IoT-DevKit_Rev_D.kicad_pcb Folder HARDWARE / NB-IoT-DevKit_Rev_D Complexity 307 / 1000 (size 217, features 90) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 105, 2,813, 196 Triangles, simulation 1,716,800 in 137 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 60 MB 637 MB STEP 275 MB 766 MB STL 86 MB 673 MB OBJ 182 MB 1.2 GB Visual GLB 42 MB 820 MB OBJ 126 MB 982 MB

1939. Neo6502_Rev_B

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	2.9	9.8	0.8 ms	8.9	0.3	1.1	0.3	24.1
Simulation, STEP	0.6	2.6	9.6	0.8 ms	8.9	6.2	1.1	0.2	29.3
Simulation, STL	0.7	2.8	9.6	0.8 ms	8.9	0.8	1.1	0.2	24.2
Simulation, OBJ	0.7	2.8	9.3	1.0 ms	10.1	11.9	1.2	0.3	36.3
Visual, GLB	0.7	2.8	11.1	0.9 ms	26.4	0.3	3.0	0.2	44.5
Visual, OBJ	0.8	3.0	10.6	0.8 ms	21.6	10.8	3.1	0.2	50.2

Board Repo: OLIMEX/Neo6502 Board: Neo6502_Rev_B.kicad_pcb Folder HARDWARE / Neo6502-rev-B Complexity 303 / 1000 (size 248, features 55) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 89, 2,635, 438 Triangles, simulation 2,044,474 in 142 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 72 MB 902 MB STEP 388 MB 1.1 GB STL 102 MB 856 MB OBJ 217 MB 1.4 GB Visual GLB 64 MB 1.1 GB OBJ 196 MB 1.3 GB

1940. Neo6502_Rev_B1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	2.3	8.0	0.7 ms	8.1	0.3	1.0	0.3	20.4
Simulation, STEP	0.6	2.2	8.0	0.9 ms	8.2	5.1	1.0	0.2	25.4
Simulation, STL	0.6	2.2	7.9	0.8 ms	7.8	0.5	0.9	0.2	20.0
Simulation, OBJ	0.6	2.2	7.9	0.8 ms	7.8	8.7	1.1	0.3	28.6
Visual, GLB	0.6	2.2	7.8	1.0 ms	18.4	0.3	3.2	0.3	32.8
Visual, OBJ	0.5	2.2	7.7	1 ms	19.1	7.9	3.0	0.3	40.7

Board Repo: OLIMEX/Neo6502 Board: Neo6502_Rev_B1.kicad_pcb Folder HARDWARE / Neo6502-rev-B1 Complexity 303 / 1000 (size 248, features 55) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 89, 2,635, 438 Triangles, simulation 2,044,474 in 142 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 72 MB 929 MB STEP 388 MB 1.1 GB STL 102 MB 896 MB OBJ 217 MB 1.4 GB Visual GLB 64 MB 1.1 GB OBJ 196 MB 1.4 GB

1941. Neo6502_Rev_A

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.1	4.4	0.4 ms	2.7	0.1	0.3	0.2	9.3
Simulation, STEP	0.4	1.1	4.6	0.4 ms	2.7	2.4	0.3	0.2	11.8
Simulation, STL	0.4	1.1	4.5	0.4 ms	2.8	0.2	0.3	0.2	9.5
Simulation, OBJ	0.4	1.1	4.4	0.4 ms	2.7	3.6	0.4	0.3	12.9
Visual, GLB	0.4	1.2	4.5	0.6 ms	7.0	0.1	0.9	0.3	14.5
Visual, OBJ	0.4	1.1	4.6	0.4 ms	7.1	3.5	0.9	0.2	17.8

Board Repo: OLIMEX/Neo6502 Board: Neo6502_Rev_A.kicad_pcb Folder HARDWARE / New6502-Rev-A Complexity 266 / 1000 (size 221, features 45) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, copper text Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 89, 625, 45 Triangles, simulation 618,484 in 142 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 23 MB 380 MB STEP 108 MB 452 MB STL 31 MB 376 MB OBJ 66 MB 489 MB Visual GLB 19 MB 445 MB OBJ 56 MB 492 MB

1942. Neo6502kbd_Rev_A

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.9	3.1	10.7	0.9 ms	9.1	0.4	1.3	0.3	25.8
Simulation, STEP	0.9	3.0	11.2	0.5 ms	8.8	5.6	1.3	0.3	31.0
Simulation, STL	0.9	3.1	11.5	1 ms	9.1	0.8	1.4	0.3	27.1
Simulation, OBJ	0.9	3.1	10.8	0.9 ms	8.6	12.0	1.3	0.2	37.0
Visual, GLB	0.9	3.0	10.8	1 ms	20.8	0.2	2.7	0.2	38.7
Visual, OBJ	0.9	3.1	10.5	1 ms	20.2	8.6	2.9	0.2	46.3

Board Repo: OLIMEX/Neo6502kbd Board: Neo6502kbd_Rev_A.kicad_pcb Folder HARDWARE / Neo6502kbd-Rev.A Complexity 377 / 1000 (size 272, features 105) KESE features through vias, slotted holes, filled zones, copper text, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 134, 3,008, 558 Triangles, simulation 2,878,202 in 179 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 101 MB 1.1 GB STEP 404 MB 1.3 GB STL 144 MB 1.1 GB OBJ 310 MB 2.0 GB Visual GLB 66 MB 1.2 GB OBJ 207 MB 1.5 GB

1943. Neo6502PC-CPU_Rev_B

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.1	4.7	13.3	1 ms	13.5	0.5	1.9	0.3	35.3
Simulation, STEP	1.0	4.7	13.5	2 ms	13.0	8.2	1.8	0.3	42.4
Simulation, STL	1.0	4.5	13.3	1 ms	13.5	1.2	2.0	0.3	36.0
Simulation, OBJ	1.3	4.6	13.6	1 ms	13.7	18.1	2.1	0.4	53.8
Visual, GLB	1.1	4.8	13.4	1 ms	31.7	0.4	4.2	0.3	55.9
Visual, OBJ	1.3	4.8	13.2	1 ms	31.5	11.9	4.1	0.3	67.1

Board Repo: OLIMEX/Neo6502pc Board: Neo6502PC-CPU_Rev_B.kicad_pcb Folder HARDWARE / Neo6502pc-CPU-rev.B Complexity 378 / 1000 (size 273, features 105) KESE features through vias, slotted holes, filled zones, copper text, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 100, 3,940, 752 Triangles, simulation 3,472,416 in 168 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 121 MB 1.3 GB STEP 496 MB 1.5 GB STL 174 MB 1.2 GB OBJ 374 MB 2.3 GB Visual GLB 81 MB 1.3 GB OBJ 254 MB 1.8 GB

1944. Neo6502PC-PWR_Rev_B

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.6	4.6	0.8 ms	3.7	0.2	0.5	0.3	11.3
Simulation, STEP	0.6	1.6	4.6	0.6 ms	3.8	2.4	0.5	0.2	13.8
Simulation, STL	0.5	1.6	4.4	0.5 ms	3.8	0.2	0.5	0.2	11.2
Simulation, OBJ	0.5	1.6	4.6	0.6 ms	3.7	5.6	0.5	0.2	16.7
Visual, GLB	0.5	1.6	4.6	0.7 ms	9.2	0.1	1.0	0.2	17.2
Visual, OBJ	0.5	1.6	4.6	0.5 ms	8.8	5.1	1.1	0.2	21.9

Board Repo: OLIMEX/Neo6502pc Board: Neo6502PC-PWR_Rev_B.kicad_pcb Folder HARDWARE / Neo6502pc-PWR-rev.B Complexity 299 / 1000 (size 194, features 105) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 53, 2,056, 491 Triangles, simulation 1,079,874 in 72 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 38 MB 501 MB STEP 155 MB 621 MB STL 54 MB 514 MB OBJ 112 MB 770 MB Visual GLB 33 MB 685 MB OBJ 100 MB 790 MB

Previous	Next
Corpus Page 17	Corpus Page 19