Corpus Testing 27

Corpus Page 27

Part 27 of 29 of Corpus Testing: boards 2,809 to 2,916, six runs each, one file format a run, as Corpus Testing describes.

2809. breakout-sky-qfn

breakout-sky-qfn: stages 4 and 6 take 47% to 81% of a run. Simulation, GLB takes 14 s. Simulation, STEP takes 17 s. Simulation, STL takes 14 s. Simulation, OBJ takes 22 s. Visual, GLB takes 20 s. Visual, OBJ takes 28 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	1.4	4.9	0.3 ms	5.2	0.3	0.8	0.3	13.6
Simulation, STEP	0.7	1.6	5.0	0.4 ms	4.9	3.9	0.8	0.2	17.1
Simulation, STL	0.8	1.6	4.9	0.3 ms	5.2	0.4	0.8	0.3	14.1
Simulation, OBJ	0.6	1.6	5.1	0.7 ms	5.1	8.4	0.9	0.2	21.9
Visual, GLB	0.7	1.5	4.8	0.4 ms	11.6	0.2	1.3	0.2	20.3
Visual, OBJ	0.6	1.6	4.9	0.3 ms	11.3	7.0	2.6	0.2	28.2

Board	Repo: TinyTapeout/breakout-pcb Board: `breakout-sky-qfn.kicad_pcb`
Folder	breakout-sky-qfn
Complexity	358 / 1000 (size 238, features 120)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ, mask and silkscreen colours
Tested	9th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	47, 1,139, 200
Triangles, simulation	1,409,674 in 97 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	49 MB	555 MB
STEP	193 MB	691 MB
STL	70 MB	525 MB
OBJ	147 MB	1.0 GB
Visual
GLB	34 MB	723 MB
OBJ	105 MB	804 MB

2810. breakout-tt04-qfn-socket

breakout-tt04-qfn-socket: stages 4 and 6 take 52% to 82% of a run. Simulation, GLB takes 10 s. Simulation, STEP takes 13 s. Simulation, STL takes 10 s. Simulation, OBJ takes 15 s. Visual, GLB takes 17 s. Visual, OBJ takes 21 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.0	4.1	0.3 ms	3.7	0.2	0.5	0.3	10.1
Simulation, STEP	0.4	1.1	4.1	0.2 ms	3.6	2.7	0.5	0.3	12.6
Simulation, STL	0.4	1.0	4.2	0.6 ms	3.7	0.4	0.5	0.3	10.5
Simulation, OBJ	0.4	1.0	4.2	0.4 ms	3.5	4.8	0.5	0.3	14.8
Visual, GLB	0.4	1.0	4.2	0.6 ms	10.0	0.1	1.4	0.3	17.4
Visual, OBJ	0.4	1.0	4.3	0.4 ms	9.5	4.0	1.4	0.2	20.8

Board	Repo: TinyTapeout/breakout-pcb Board: `breakout-tt04-qfn-socket.kicad_pcb`
Folder	breakout-tt04-qfn-socket
Complexity	316 / 1000 (size 201, features 115)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	13, 761, 128
Triangles, simulation	975,262 in 66 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	34 MB	516 MB
STEP	154 MB	546 MB
STL	49 MB	487 MB
OBJ	99 MB	685 MB
Visual
GLB	27 MB	681 MB
OBJ	82 MB	660 MB

2811. breakout-tt06-qfn-socket

breakout-tt06-qfn-socket: stages 4 and 6 take 52% to 83% of a run. Simulation, GLB takes 12 s. Simulation, STEP takes 15 s. Simulation, STL takes 12 s. Simulation, OBJ takes 18 s. Visual, GLB takes 19 s. Visual, OBJ takes 23 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.1	5.1	0.4 ms	4.3	0.2	0.7	0.2	12.1
Simulation, STEP	0.5	1.1	4.8	0.3 ms	4.2	3.5	0.7	0.2	15.0
Simulation, STL	0.5	1.1	5.0	0.3 ms	4.2	0.4	0.6	0.3	11.9
Simulation, OBJ	0.5	1.1	4.9	0.2 ms	4.4	6.1	0.7	0.2	17.8
Visual, GLB	0.6	1.1	5.2	0.6 ms	10.4	0.2	1.1	0.3	18.7
Visual, OBJ	0.5	1.2	4.8	0.3 ms	9.9	5.3	1.2	0.2	23.1

Board	Repo: TinyTapeout/breakout-pcb Board: `breakout-tt06-qfn-socket.kicad_pcb`
Folder	breakout-tt06-qfn-socket
Complexity	324 / 1000 (size 214, features 110)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, TrueType text
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	42, 925, 99
Triangles, simulation	1,062,926 in 77 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	37 MB	479 MB
STEP	189 MB	599 MB
STL	53 MB	468 MB
OBJ	108 MB	741 MB
Visual
GLB	30 MB	653 MB
OBJ	90 MB	694 MB

2812. tinytapeout-demo

tinytapeout-demo: stages 4 and 6 take 51% to 82% of a run. Simulation, GLB takes 35 s. Simulation, STEP takes 43 s. Simulation, STL takes 34 s. Simulation, OBJ takes 53 s. Visual, GLB takes 56 s. Visual, OBJ takes 67 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.2	3.9	14.1	1 ms	13.3	0.7	1.9	0.2	35.3
Simulation, STEP	1.2	3.9	13.7	0.5 ms	12.7	9.1	1.8	0.3	42.8
Simulation, STL	1.4	3.6	13.3	0.5 ms	12.9	1.1	1.8	0.3	34.4
Simulation, OBJ	1.3	3.6	14.0	0.5 ms	13.0	18.8	2.0	0.3	53.1
Visual, GLB	1.2	3.7	13.5	1 ms	32.4	0.4	4.2	0.3	55.7
Visual, OBJ	1.3	3.9	13.6	0.6 ms	31.0	12.8	4.3	0.3	67.1

Board	Repo: TinyTapeout/tt-demo-pcb Board: `tinytapeout-demo.kicad_pcb`
Complexity	404 / 1000 (size 264, features 140)
KESE features	through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ, mask and silkscreen colours
Tested	9th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	158, 2,785, 401
Triangles, simulation	3,981,250 in 162 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	137 MB	1.2 GB
STEP	608 MB	1.5 GB
STL	199 MB	1.2 GB
OBJ	427 MB	2.6 GB
Visual
GLB	93 MB	1.5 GB
OBJ	294 MB	2.1 GB

2813. syzygy-mipi-adapter

syzygy-mipi-adapter: stages 4 and 6 take 46% to 82% of a run. Simulation, GLB takes 17 s. Simulation, STEP takes 23 s. Simulation, STL takes 17 s. Simulation, OBJ takes 26 s. Visual, GLB takes 27 s. Visual, OBJ takes 35 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	1.7	4.7	0.7 ms	7.7	0.3	1.1	0.3	16.5
Simulation, STEP	0.7	1.7	4.9	1 ms	8.1	6.2	1.0	0.3	23.0
Simulation, STL	0.8	1.7	4.7	0.6 ms	7.7	0.6	1.0	0.3	16.7
Simulation, OBJ	0.8	1.8	4.7	0.7 ms	7.2	10.4	0.9	0.3	26.1
Visual, GLB	0.8	1.7	4.5	0.7 ms	17.6	0.2	2.0	0.3	27.1
Visual, OBJ	0.7	1.7	4.8	0.7 ms	17.2	7.9	2.1	0.3	34.7

Board	Repo: tinyvision-ai-inc/oshw-adapters Board: `syzygy-mipi-adapter.kicad_pcb`
Folder	syzygy-mipi-adapter / board / Rev0
Complexity	387 / 1000 (size 252, features 135)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	77, 2,383, 207
Triangles, simulation	1,732,038 in 183 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	59 MB	776 MB
STEP	268 MB	864 MB
STL	87 MB	776 MB
OBJ	182 MB	1.2 GB
Visual
GLB	43 MB	781 MB
OBJ	135 MB	950 MB

2814. syzygy-mipi-adapter

syzygy-mipi-adapter: stages 4 and 6 take 46% to 82% of a run. Simulation, GLB takes 13 s. Simulation, STEP takes 18 s. Simulation, STL takes 13 s. Simulation, OBJ takes 22 s. Visual, GLB takes 22 s. Visual, OBJ takes 29 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	1.4	3.9	0.6 ms	6.2	0.2	0.8	0.2	13.4
Simulation, STEP	0.6	1.4	4.1	0.6 ms	6.1	4.6	0.8	0.2	17.7
Simulation, STL	0.6	1.4	4.0	0.8 ms	5.7	0.6	0.8	0.2	13.4
Simulation, OBJ	0.7	1.4	4.0	0.6 ms	6.2	8.7	0.8	0.2	21.9
Visual, GLB	0.7	1.4	4.1	0.5 ms	13.7	0.2	1.4	0.2	21.8
Visual, OBJ	0.6	1.5	4.1	0.5 ms	14.2	6.6	1.6	0.3	28.9

Board	Repo: tinyvision-ai-inc/oshw-adapters Board: `syzygy-mipi-adapter.kicad_pcb`
Folder	syzygy-mipi-adapter / board / Rev1
Complexity	386 / 1000 (size 251, features 135)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	75, 2,381, 204
Triangles, simulation	1,718,452 in 183 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	59 MB	772 MB
STEP	267 MB	829 MB
STL	86 MB	770 MB
OBJ	181 MB	1.2 GB
Visual
GLB	43 MB	877 MB
OBJ	134 MB	967 MB

2815. pico-ice

pico-ice: stages 4 and 6 take 48% to 83% of a run. Simulation, GLB takes 20 s. Simulation, STEP takes 25 s. Simulation, STL takes 21 s. Simulation, OBJ takes 34 s. Visual, GLB takes 30 s. Visual, OBJ takes 38 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	2.3	8.0	0.6 ms	7.9	0.3	1.0	0.2	20.4
Simulation, STEP	0.6	2.2	7.9	0.6 ms	7.9	5.5	1.0	0.2	25.3
Simulation, STL	0.6	2.3	8.6	0.5 ms	7.8	0.7	1.0	0.3	21.3
Simulation, OBJ	0.7	2.2	8.7	0.5 ms	8.0	13.5	1.0	0.3	34.4
Visual, GLB	0.7	2.5	8.1	0.8 ms	16.6	0.2	1.6	0.3	29.9
Visual, OBJ	0.6	2.3	8.1	0.6 ms	17.4	7.3	1.9	0.3	38.0

Board	Repo: tinyvision-ai-inc/pico-ice Board: `pico-ice.kicad_pcb`
Folder	Board / Rev0
Complexity	375 / 1000 (size 255, features 120)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 6 (20211014)
Parts, tracks, vias	95, 1,537, 178
Triangles, simulation	2,230,612 in 110 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	77 MB	749 MB
STEP	401 MB	889 MB
STL	112 MB	779 MB
OBJ	242 MB	1.6 GB
Visual
GLB	48 MB	888 MB
OBJ	149 MB	1.1 GB

2816. pico-ice

pico-ice: stages 4 and 6 take 49% to 83% of a run. Simulation, GLB takes 23 s. Simulation, STEP takes 28 s. Simulation, STL takes 23 s. Simulation, OBJ takes 36 s. Visual, GLB takes 33 s. Visual, OBJ takes 40 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	2.7	8.7	1.0 ms	9.6	0.4	1.1	0.3	23.4
Simulation, STEP	0.6	2.6	8.6	0.5 ms	9.2	6.1	1.1	0.2	28.4
Simulation, STL	0.6	2.6	8.7	0.7 ms	9.4	0.6	1.1	0.3	23.3
Simulation, OBJ	0.7	2.6	8.3	0.5 ms	9.3	13.9	1.1	0.2	36.0
Visual, GLB	0.7	2.6	8.5	0.6 ms	18.8	0.3	1.7	0.3	32.8
Visual, OBJ	0.6	2.7	8.8	0.8 ms	17.8	8.0	1.6	0.2	39.7

Board	Repo: tinyvision-ai-inc/pico-ice Board: `pico-ice.kicad_pcb`
Folder	Board / Rev1
Complexity	375 / 1000 (size 255, features 120)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 6 (20211014)
Parts, tracks, vias	86, 1,748, 182
Triangles, simulation	2,332,170 in 113 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	81 MB	752 MB
STEP	423 MB	912 MB
STL	117 MB	793 MB
OBJ	253 MB	1.6 GB
Visual
GLB	51 MB	937 MB
OBJ	157 MB	1.1 GB

2817. pico-ice

pico-ice: stages 4 and 6 take 52% to 82% of a run. Simulation, GLB takes 22 s. Simulation, STEP takes 27 s. Simulation, STL takes 23 s. Simulation, OBJ takes 34 s. Visual, GLB takes 32 s. Visual, OBJ takes 39 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	2.4	8.2	0.6 ms	8.7	0.4	1.1	0.3	21.7
Simulation, STEP	0.6	2.3	8.3	0.6 ms	8.8	5.7	1.0	0.2	26.9
Simulation, STL	0.5	2.6	8.3	0.6 ms	9.1	0.9	1.0	0.3	22.7
Simulation, OBJ	0.5	2.5	8.3	0.8 ms	9.4	11.9	1.1	0.2	33.8
Visual, GLB	0.6	2.6	8.2	0.5 ms	18.2	0.2	2.4	0.2	32.4
Visual, OBJ	0.5	2.3	7.8	0.7 ms	18.2	7.4	2.6	0.3	39.1

Board	Repo: tinyvision-ai-inc/pico-ice Board: `pico-ice.kicad_pcb`
Folder	Board / Rev2
Complexity	375 / 1000 (size 255, features 120)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 6 (20211014)
Parts, tracks, vias	86, 1,748, 182
Triangles, simulation	2,341,844 in 113 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	81 MB	814 MB
STEP	425 MB	936 MB
STL	117 MB	742 MB
OBJ	254 MB	1.6 GB
Visual
GLB	51 MB	961 MB
OBJ	158 MB	1.1 GB

2818. pico-ice

pico-ice: stages 4 and 6 take 51% to 81% of a run. Simulation, GLB takes 24 s. Simulation, STEP takes 29 s. Simulation, STL takes 24 s. Simulation, OBJ takes 36 s. Visual, GLB takes 36 s. Visual, OBJ takes 43 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	2.8	8.6	0.7 ms	9.6	0.4	1.3	0.3	23.6
Simulation, STEP	0.6	2.9	9.0	0.6 ms	9.4	6.1	1.2	0.3	29.4
Simulation, STL	0.6	2.8	8.8	0.6 ms	9.6	0.7	1.2	0.2	23.9
Simulation, OBJ	0.7	2.8	8.7	0.6 ms	9.3	12.6	1.2	0.3	35.5
Visual, GLB	0.6	2.8	8.8	0.8 ms	20.3	0.3	2.6	0.3	35.7
Visual, OBJ	0.6	2.7	8.7	0.7 ms	20.3	8.2	2.6	0.3	43.4

Board	Repo: tinyvision-ai-inc/pico-ice Board: `pico-ice.kicad_pcb`
Folder	Board / Rev3
Complexity	375 / 1000 (size 255, features 120)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 8 (20240108)
Parts, tracks, vias	87, 1,689, 189
Triangles, simulation	2,375,218 in 111 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	82 MB	809 MB
STEP	429 MB	952 MB
STL	119 MB	853 MB
OBJ	257 MB	1.6 GB
Visual
GLB	51 MB	1.0 GB
OBJ	159 MB	1.1 GB

2819. pico2-ice

pico2-ice: stages 4 and 6 take 51% to 83% of a run. Simulation, GLB takes 26 s. Simulation, STEP takes 32 s. Simulation, STL takes 26 s. Simulation, OBJ takes 39 s. Visual, GLB takes 39 s. Visual, OBJ takes 48 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	3.2	9.8	0.9 ms	9.9	0.5	1.5	0.3	25.8
Simulation, STEP	0.7	2.9	9.8	0.9 ms	10.5	6.5	1.4	0.3	32.0
Simulation, STL	0.7	3.0	9.6	1 ms	10.1	0.7	1.3	0.3	25.7
Simulation, OBJ	0.7	3.0	9.8	0.9 ms	10.0	13.8	1.4	0.3	39.1
Visual, GLB	0.7	3.1	10.5	0.8 ms	21.3	0.3	2.3	0.3	38.5
Visual, OBJ	0.7	3.3	10.4	0.9 ms	20.8	10.0	2.3	0.3	47.8

Board	Repo: tinyvision-ai-inc/pico2-ice Board: `pico2-ice.kicad_pcb`
Folder	Board / Rev0
Complexity	381 / 1000 (size 261, features 120)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026 to 10th November 2026
Copper layers	4
File format	KiCad 8 (20240108)
Parts, tracks, vias	108, 2,040, 262
Triangles, simulation	2,664,998 in 141 parts
Verifier	PASS in all six runs
Run again	Simulation, GLB; Simulation, STEP; Simulation, STL; Simulation, OBJ: failed in the corpus run, run again with fixes to KESE made after the corpus run, and passed

File type	File size	Peak memory used
Simulation
GLB	92 MB	1.0 GB
STEP	451 MB	1.0 GB
STL	133 MB	988 MB
OBJ	290 MB	1.8 GB
Visual
GLB	58 MB	1.1 GB
OBJ	183 MB	1.3 GB

2820. pico2-ice

pico2-ice: stages 4 and 6 take 51% to 82% of a run. Simulation, GLB takes 24 s. Simulation, STEP takes 30 s. Simulation, STL takes 24 s. Simulation, OBJ takes 37 s. Visual, GLB takes 37 s. Visual, OBJ takes 46 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	2.8	9.3	0.8 ms	9.8	0.5	1.2	0.3	24.5
Simulation, STEP	0.6	2.8	8.9	0.7 ms	9.8	6.0	1.2	0.3	29.6
Simulation, STL	0.5	2.7	8.9	0.9 ms	9.7	0.8	1.3	0.2	24.3
Simulation, OBJ	0.7	2.9	9.1	1 ms	9.9	12.8	1.5	0.3	37.2
Visual, GLB	0.7	2.8	9.0	1 ms	21.1	0.3	2.8	0.2	36.9
Visual, OBJ	0.7	2.9	9.1	0.9 ms	21.6	8.3	2.9	0.3	45.9

Board	Repo: tinyvision-ai-inc/pico2-ice Board: `pico2-ice.kicad_pcb`
Folder	Board / Rev1
Complexity	382 / 1000 (size 262, features 120)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 8 (20240108)
Parts, tracks, vias	109, 2,181, 270
Triangles, simulation	2,707,426 in 139 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	94 MB	967 MB
STEP	458 MB	1.0 GB
STL	135 MB	1.0 GB
OBJ	294 MB	1.8 GB
Visual
GLB	59 MB	1.1 GB
OBJ	187 MB	1.4 GB

2821. pico2-ice

pico2-ice: stages 4 and 6 take 50% to 82% of a run. Simulation, GLB takes 28 s. Simulation, STEP takes 35 s. Simulation, STL takes 29 s. Simulation, OBJ takes 44 s. Visual, GLB takes 39 s. Visual, OBJ takes 50 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	3.2	10.8	0.7 ms	11.4	0.5	1.4	0.3	28.2
Simulation, STEP	0.8	3.4	10.8	0.4 ms	11.3	7.4	1.4	0.3	35.5
Simulation, STL	0.8	3.3	11.1	0.8 ms	11.5	0.9	1.4	0.3	29.2
Simulation, OBJ	0.8	3.2	11.0	0.7 ms	11.0	15.8	1.4	0.3	43.5
Visual, GLB	0.9	3.2	10.8	0.7 ms	21.1	0.3	2.3	0.3	38.9
Visual, OBJ	0.8	3.2	10.6	0.8 ms	22.3	10.2	2.3	0.3	49.6

Board	Repo: tinyvision-ai-inc/pico2-ice Board: `pico2-ice.kicad_pcb`
Folder	Board / Rev2
Complexity	382 / 1000 (size 262, features 120)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	110, 2,189, 270
Triangles, simulation	2,736,022 in 139 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	95 MB	980 MB
STEP	463 MB	1.1 GB
STL	137 MB	900 MB
OBJ	298 MB	1.8 GB
Visual
GLB	60 MB	1.1 GB
OBJ	189 MB	1.3 GB

2822. pico2-nx-module

pico2-nx-module: stages 4 and 6 take 41% to 81% of a run. Simulation, GLB takes 13 s. Simulation, STEP takes 16 s. Simulation, STL takes 13 s. Simulation, OBJ takes 23 s. Visual, GLB takes 20 s. Visual, OBJ takes 25 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.8	3.9	0.5 ms	5.7	0.3	0.8	0.2	13.1
Simulation, STEP	0.4	1.8	3.9	0.6 ms	5.7	3.5	0.8	0.2	16.3
Simulation, STL	0.4	1.9	3.9	0.6 ms	5.7	0.5	0.8	0.2	13.4
Simulation, OBJ	0.4	1.8	3.8	0.5 ms	5.6	10.4	0.9	0.2	23.1
Visual, GLB	0.4	1.9	3.9	0.7 ms	12.1	0.1	1.1	0.2	19.6
Visual, OBJ	0.4	1.9	3.9	0.9 ms	11.4	5.7	1.1	0.2	24.6

Board	Repo: tinyvision-ai-inc/pico2-nx Board: `pico2-nx-module.kicad_pcb`
Folder	board / Rev0 / pico2-nx-module
Complexity	347 / 1000 (size 272, features 75)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	6
File format	KiCad 9 (20241229)
Parts, tracks, vias	71, 1,994, 270
Triangles, simulation	1,969,336 in 138 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	66 MB	642 MB
STEP	223 MB	774 MB
STL	98 MB	655 MB
OBJ	204 MB	1.3 GB
Visual
GLB	36 MB	738 MB
OBJ	112 MB	801 MB

2823. pico2-nx

pico2-nx: stages 4 and 6 take 50% to 83% of a run. Simulation, GLB takes 18 s. Simulation, STEP takes 24 s. Simulation, STL takes 19 s. Simulation, OBJ takes 28 s. Visual, GLB takes 27 s. Visual, OBJ takes 33 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	1.9	7.7	0.9 ms	6.5	0.3	0.8	0.3	18.2
Simulation, STEP	0.8	2.0	7.6	1.0 ms	6.9	5.3	0.8	0.3	23.7
Simulation, STL	0.7	2.0	7.7	0.7 ms	6.7	0.5	0.8	0.3	18.8
Simulation, OBJ	0.8	2.0	7.4	1 ms	6.8	10.5	0.8	0.3	28.5
Visual, GLB	0.7	2.1	7.7	0.9 ms	14.7	0.2	1.3	0.3	27.1
Visual, OBJ	0.8	1.9	7.5	2 ms	14.8	6.5	1.7	0.2	33.4

Board	Repo: tinyvision-ai-inc/pico2-nx Board: `pico2-nx.kicad_pcb`
Folder	board / Rev0 / pico2-nx
Complexity	336 / 1000 (size 221, features 115)
KESE features	microvias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, copper drawings, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	237, 10, 81
Triangles, simulation	1,634,060 in 259 parts
Note	mostly unrouted
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	55 MB	692 MB
STEP	252 MB	780 MB
STL	82 MB	608 MB
OBJ	168 MB	1.1 GB
Visual
GLB	37 MB	907 MB
OBJ	111 MB	821 MB

2824. nx-module-breakout

nx-module-breakout: stages 4 and 6 take 52% to 84% of a run. Simulation, GLB takes 14 s. Simulation, STEP takes 17 s. Simulation, STL takes 14 s. Simulation, OBJ takes 20 s. Visual, GLB takes 21 s. Visual, OBJ takes 26 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.4	5.9	0.4 ms	4.9	0.2	0.7	0.2	13.7
Simulation, STEP	0.4	1.3	5.5	0.4 ms	5.1	4.0	0.8	0.2	17.4
Simulation, STL	0.5	1.4	5.6	0.4 ms	5.0	0.4	0.7	0.3	14.0
Simulation, OBJ	0.4	1.3	5.8	0.9 ms	4.7	6.9	0.8	0.2	20.0
Visual, GLB	0.4	1.3	5.6	0.3 ms	11.8	0.2	1.4	0.2	20.9
Visual, OBJ	0.4	1.3	6.0	0.7 ms	12.0	4.7	1.5	0.2	26.1

Board	Repo: tinyvision-ai-inc/pico2-nx Board: `nx-module-breakout.kicad_pcb`
Folder	board / Rev2 / nx-module-breakout
Complexity	320 / 1000 (size 195, features 125)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	45, 1,224, 92
Triangles, simulation	1,514,246 in 139 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	52 MB	547 MB
STEP	228 MB	721 MB
STL	76 MB	586 MB
OBJ	160 MB	1.1 GB
Visual
GLB	35 MB	676 MB
OBJ	107 MB	773 MB

2825. pico2-nx-module

pico2-nx-module: stages 4 and 6 take 43% to 84% of a run. Simulation, GLB takes 16 s. Simulation, STEP takes 21 s. Simulation, STL takes 16 s. Simulation, OBJ takes 26 s. Visual, GLB takes 25 s. Visual, OBJ takes 33 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	1.7	4.1	1.0 ms	7.8	0.3	1.0	0.3	15.8
Simulation, STEP	0.7	1.6	4.1	0.5 ms	7.3	5.6	1.0	0.3	20.6
Simulation, STL	0.8	1.6	4.0	0.6 ms	7.5	0.6	1.0	0.3	15.8
Simulation, OBJ	0.8	1.7	4.2	0.5 ms	7.3	11.3	1.1	0.3	26.5
Visual, GLB	0.7	1.7	4.2	0.5 ms	16.8	0.2	1.2	0.3	25.1
Visual, OBJ	0.7	1.6	4.1	0.5 ms	17.1	7.4	1.6	0.2	32.8

Board	Repo: tinyvision-ai-inc/pico2-nx Board: `pico2-nx-module.kicad_pcb`
Folder	board / Rev2 / nx-module
Complexity	376 / 1000 (size 276, features 100)
KESE features	through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	6
File format	KiCad 9 (20241229)
Parts, tracks, vias	71, 2,995, 254
Triangles, simulation	1,957,374 in 138 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	66 MB	664 MB
STEP	256 MB	873 MB
STL	98 MB	663 MB
OBJ	204 MB	1.3 GB
Visual
GLB	42 MB	992 MB
OBJ	131 MB	1.0 GB

2826. pogo_adapter

pogo_adapter: stages 4 and 6 take 48% to 76% of a run. Simulation, GLB takes 1.8 s. Simulation, STEP takes 2.5 s. Simulation, STL takes 1.8 s. Simulation, OBJ takes 2.4 s. Visual, GLB takes 2.4 s. Visual, OBJ takes 2.9 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	97 ms	0.2	0.6	0.1 ms	0.6	22 ms	84 ms	0.2	1.8
Simulation, STEP	0.1	0.1	0.6	0.1 ms	0.6	0.8	79 ms	0.2	2.5
Simulation, STL	0.1	0.1	0.6	0.1 ms	0.6	36 ms	80 ms	0.2	1.8
Simulation, OBJ	0.1	0.1	0.6	0.1 ms	0.6	0.7	92 ms	0.2	2.4
Visual, GLB	0.1	0.1	0.6	0.1 ms	1.3	23 ms	0.1	0.2	2.4
Visual, OBJ	0.1	0.1	0.6	0.2 ms	1.3	0.5	0.1	0.2	2.9

Board	Repo: tinyvision-ai-inc/upduino-jtag Board: `pogo_adapter.kicad_pcb`
Folder	board / pogo_adapter
Complexity	181 / 1000 (size 111, features 70)
KESE features	through vias, filled zones, stack-up, dielectric εr and tanδ, mask and silkscreen colours
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	2, 55, 32
Triangles, simulation	139,780 in 20 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	4.8 MB	196 MB
STEP	19 MB	201 MB
STL	7.0 MB	191 MB
OBJ	14 MB	192 MB
Visual
GLB	3.8 MB	160 MB
OBJ	11 MB	165 MB

2827. upduino-jtag

upduino-jtag: stages 4 and 6 take 49% to 80% of a run. Simulation, GLB takes 3.9 s. Simulation, STEP takes 5.0 s. Simulation, STL takes 3.8 s. Simulation, OBJ takes 5.9 s. Visual, GLB takes 5.5 s. Visual, OBJ takes 6.8 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	1.6	0.3 ms	1.3	62 ms	0.2	0.3	3.9
Simulation, STEP	0.1	0.3	1.6	0.3 ms	1.2	1.3	0.2	0.2	5.0
Simulation, STL	0.1	0.3	1.6	0.2 ms	1.3	86 ms	0.3	0.2	3.8
Simulation, OBJ	0.1	0.3	1.7	0.3 ms	1.3	2.0	0.2	0.2	5.9
Visual, GLB	0.1	0.3	1.6	0.3 ms	2.9	40 ms	0.4	0.3	5.5
Visual, OBJ	0.1	0.3	1.7	0.3 ms	2.9	1.3	0.3	0.2	6.8

Board	Repo: tinyvision-ai-inc/upduino-jtag Board: `upduino-jtag.kicad_pcb`
Folder	board / upduino_adapter
Complexity	208 / 1000 (size 128, features 80)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ, mask and silkscreen colours
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	6, 94, 49
Triangles, simulation	365,398 in 59 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	12 MB	263 MB
STEP	46 MB	284 MB
STL	18 MB	275 MB
OBJ	36 MB	288 MB
Visual
GLB	8.2 MB	265 MB
OBJ	24 MB	268 MB

2828. UPduino_v3.0

UPduino_v3.0: stages 4 and 6 take 52% to 84% of a run. Simulation, GLB takes 16 s. Simulation, STEP takes 20 s. Simulation, STL takes 16 s. Simulation, OBJ takes 24 s. Visual, GLB takes 22 s. Visual, OBJ takes 28 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.8	6.7	0.4 ms	5.8	0.3	0.7	0.2	15.8
Simulation, STEP	0.4	1.8	6.6	0.4 ms	5.8	4.1	0.7	0.2	19.6
Simulation, STL	0.4	1.8	6.6	0.4 ms	5.8	0.4	0.7	0.3	16.0
Simulation, OBJ	0.4	1.8	6.7	0.4 ms	5.7	8.3	0.8	0.2	23.8
Visual, GLB	0.4	1.9	6.5	0.5 ms	12.2	0.2	1.0	0.2	22.4
Visual, OBJ	0.4	1.8	6.7	0.5 ms	12.0	5.3	1.1	0.2	27.6

Board	Repo: tinyvision-ai-inc/upduino-v3.0 Board: `UPduino_v3.0.kicad_pcb`
Folder	Board / v1.0
Complexity	344 / 1000 (size 254, features 90)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline
Tested	9th November 2026
Copper layers	4
File format	KiCad 5 (20171130)
Parts, tracks, vias	85, 1,713, 127
Triangles, simulation	1,650,130 in 109 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	58 MB	588 MB
STEP	277 MB	707 MB
STL	83 MB	569 MB
OBJ	174 MB	1.1 GB
Visual
GLB	36 MB	714 MB
OBJ	107 MB	794 MB

2829. UPduino_v3.0

UPduino_v3.0: stages 4 and 6 take 54% to 84% of a run. Simulation, GLB takes 14 s. Simulation, STEP takes 18 s. Simulation, STL takes 15 s. Simulation, OBJ takes 20 s. Visual, GLB takes 22 s. Visual, OBJ takes 25 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.7	5.8	0.5 ms	5.1	0.3	0.7	0.2	14.1
Simulation, STEP	0.4	1.4	5.8	0.6 ms	5.5	3.8	0.8	0.3	17.9
Simulation, STL	0.4	1.6	6.3	0.6 ms	5.6	0.5	0.7	0.2	15.3
Simulation, OBJ	0.3	1.5	5.7	0.4 ms	5.4	6.7	0.7	0.2	20.4
Visual, GLB	0.3	1.6	6.3	0.6 ms	12.5	0.2	1.3	0.2	22.3
Visual, OBJ	0.4	1.6	5.8	0.6 ms	11.6	4.2	1.5	0.2	25.3

Board	Repo: tinyvision-ai-inc/upduino-v3.0 Board: `UPduino_v3.0.kicad_pcb`
Folder	Board / v2.0
Complexity	342 / 1000 (size 252, features 90)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline
Tested	9th November 2026
Copper layers	4
File format	KiCad 5 (20171130)
Parts, tracks, vias	83, 1,589, 122
Triangles, simulation	1,625,058 in 105 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	57 MB	587 MB
STEP	272 MB	692 MB
STL	81 MB	602 MB
OBJ	171 MB	1.1 GB
Visual
GLB	35 MB	723 MB
OBJ	106 MB	807 MB

2830. UPduino_v3.0

UPduino_v3.0: stages 4 and 6 take 53% to 83% of a run. Simulation, GLB takes 15 s. Simulation, STEP takes 19 s. Simulation, STL takes 16 s. Simulation, OBJ takes 23 s. Visual, GLB takes 23 s. Visual, OBJ takes 29 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.8	6.0	0.5 ms	5.7	0.2	0.7	0.2	15.1
Simulation, STEP	0.4	1.7	6.3	0.4 ms	5.9	3.7	0.8	0.3	19.1
Simulation, STL	0.3	1.8	6.3	0.5 ms	6.0	0.6	0.7	0.2	15.9
Simulation, OBJ	0.4	1.8	6.4	0.5 ms	5.9	7.6	0.9	0.3	23.2
Visual, GLB	0.4	1.9	6.1	0.6 ms	13.0	0.2	1.3	0.2	23.1
Visual, OBJ	0.4	1.7	6.4	0.3 ms	13.4	4.9	1.7	0.2	28.6

Board	Repo: tinyvision-ai-inc/upduino-v3.0 Board: `UPduino_v3.0.kicad_pcb`
Folder	Board / v3.0
Complexity	342 / 1000 (size 252, features 90)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline
Tested	9th November 2026
Copper layers	4
File format	KiCad 5 (20171130)
Parts, tracks, vias	83, 1,585, 123
Triangles, simulation	1,629,942 in 105 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	57 MB	597 MB
STEP	272 MB	690 MB
STL	82 MB	597 MB
OBJ	172 MB	1.1 GB
Visual
GLB	35 MB	770 MB
OBJ	106 MB	811 MB

2831. UPduino_v3.01

UPduino_v3.01: stages 4 and 6 take 49% to 83% of a run. Simulation, GLB takes 15 s. Simulation, STEP takes 18 s. Simulation, STL takes 16 s. Simulation, OBJ takes 24 s. Visual, GLB takes 22 s. Visual, OBJ takes 29 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	1.7	5.7	0.4 ms	5.5	0.2	0.7	0.3	14.8
Simulation, STEP	0.5	1.8	5.7	0.5 ms	5.5	4.0	0.8	0.3	18.4
Simulation, STL	0.5	1.9	6.1	0.5 ms	5.8	0.4	0.8	0.2	15.6
Simulation, OBJ	0.5	1.7	6.1	0.6 ms	5.6	9.1	0.7	0.2	23.9
Visual, GLB	0.6	1.7	6.0	0.4 ms	12.3	0.2	1.1	0.2	22.0
Visual, OBJ	0.5	1.7	6.1	0.7 ms	12.5	5.9	1.5	0.2	28.5

Board	Repo: tinyvision-ai-inc/upduino-v3.0 Board: `UPduino_v3.01.kicad_pcb`
Folder	Board / v3.01
Complexity	342 / 1000 (size 252, features 90)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline
Tested	9th November 2026
Copper layers	4
File format	KiCad 8 (20240108)
Parts, tracks, vias	83, 1,585, 123
Triangles, simulation	1,581,102 in 105 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	56 MB	581 MB
STEP	283 MB	695 MB
STL	79 MB	616 MB
OBJ	167 MB	1.1 GB
Visual
GLB	34 MB	751 MB
OBJ	102 MB	774 MB

2832. Speeduino_base

Speeduino_base: stages 4 and 6 take 58% to 86% of a run. Simulation, GLB takes 33 s. Simulation, STEP takes 41 s. Simulation, STL takes 34 s. Simulation, OBJ takes 48 s. Visual, GLB takes 48 s. Visual, OBJ takes 59 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	3.0	15.8	0.6 ms	11.7	0.4	1.6	0.3	33.4
Simulation, STEP	0.6	3.0	16.4	0.6 ms	11.1	7.6	1.5	0.3	40.5
Simulation, STL	0.6	3.0	16.0	0.7 ms	11.7	0.7	1.5	0.3	33.8
Simulation, OBJ	0.6	3.1	16.0	0.6 ms	11.6	14.7	1.4	0.2	47.8
Visual, GLB	0.6	3.1	16.3	0.6 ms	25.4	0.3	2.3	0.2	48.3
Visual, OBJ	0.6	3.3	16.8	0.6 ms	25.7	10.1	2.2	0.3	58.8

Board	Repo: tjeerdie/spectre Board: `Speeduino_base.kicad_pcb`
Folder	SPECTRE_V0.3
Complexity	249 / 1000 (size 204, features 45)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones
Tested	9th November 2026
Copper layers	2
File format	KiCad 5 (20171130)
Parts, tracks, vias	161, 2,568, 227
Triangles, simulation	2,573,754 in 189 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	89 MB	824 MB
STEP	483 MB	1.1 GB
STL	129 MB	810 MB
OBJ	274 MB	1.7 GB
Visual
GLB	64 MB	1.2 GB
OBJ	199 MB	1.3 GB

2833. Speeduino_base

Speeduino_base: stages 4 and 6 take 55% to 86% of a run. Simulation, GLB takes 47 s. Simulation, STEP takes 64 s. Simulation, STL takes 48 s. Simulation, OBJ takes 68 s. Visual, GLB takes 75 s. Visual, OBJ takes 92 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.9	4.4	22.3	1 ms	16.0	0.7	2.8	0.3	47.4
Simulation, STEP	0.9	4.3	24.1	1 ms	18.3	13.1	2.5	0.4	63.6
Simulation, STL	0.9	4.1	22.2	2 ms	16.5	1.3	2.4	0.3	47.7
Simulation, OBJ	0.9	4.4	21.6	2 ms	15.8	22.4	2.4	0.3	67.8
Visual, GLB	0.8	4.1	22.0	1 ms	42.8	0.5	4.9	0.3	75.5
Visual, OBJ	0.9	4.3	22.1	1 ms	41.3	17.6	5.7	0.3	92.2

Board	Repo: tjeerdie/spectre Board: `Speeduino_base.kicad_pcb`
Folder	SPECTRE_V0.4
Complexity	261 / 1000 (size 206, features 55)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline
Tested	9th November 2026
Copper layers	2
File format	KiCad 5 (20171130)
Parts, tracks, vias	185, 2,262, 308
Triangles, simulation	3,444,736 in 206 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	119 MB	1.2 GB
STEP	644 MB	1.5 GB
STL	172 MB	1.2 GB
OBJ	367 MB	2.3 GB
Visual
GLB	89 MB	1.5 GB
OBJ	280 MB	1.9 GB

2834. Speeduino_base

Speeduino_base: stages 4 and 6 take 58% to 87% of a run. Simulation, GLB takes 43 s. Simulation, STEP takes 52 s. Simulation, STL takes 43 s. Simulation, OBJ takes 62 s. Visual, GLB takes 62 s. Visual, OBJ takes 76 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	3.5	19.7	1 ms	16.1	0.6	2.1	0.3	43.0
Simulation, STEP	0.7	3.5	20.0	1.0 ms	15.5	10.1	1.9	0.3	52.0
Simulation, STL	0.8	3.5	19.4	1.0 ms	15.7	1.1	2.1	0.2	42.8
Simulation, OBJ	0.8	3.5	20.2	0.6 ms	15.8	19.2	1.9	0.3	61.7
Visual, GLB	0.8	3.6	19.7	1.0 ms	34.6	0.4	3.1	0.2	62.4
Visual, OBJ	0.7	3.6	19.4	1 ms	33.2	14.2	4.5	0.3	75.9

Board	Repo: tjeerdie/spectre Board: `Speeduino_base.kicad_pcb`
Folder	SPECTRE_V0.5.1
Complexity	264 / 1000 (size 209, features 55)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline
Tested	10th November 2026
Copper layers	2
File format	KiCad 5 (20171130)
Parts, tracks, vias	204, 2,483, 368
Triangles, simulation	3,634,522 in 217 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	126 MB	1.1 GB
STEP	687 MB	1.6 GB
STL	182 MB	1.1 GB
OBJ	388 MB	2.4 GB
Visual
GLB	94 MB	1.6 GB
OBJ	295 MB	1.9 GB

2835. Speeduino_base

Speeduino_base: stages 4 and 6 take 56% to 84% of a run. Simulation, GLB takes 49 s. Simulation, STEP takes 61 s. Simulation, STL takes 49 s. Simulation, OBJ takes 70 s. Visual, GLB takes 84 s. Visual, OBJ takes 99 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.9	4.5	23.4	0.8 ms	16.9	0.7	2.4	0.4	49.1
Simulation, STEP	0.8	4.2	22.9	0.8 ms	17.0	12.7	2.7	0.3	60.6
Simulation, STL	0.9	4.3	22.6	0.9 ms	17.1	1.5	2.7	0.3	49.4
Simulation, OBJ	0.9	4.2	23.0	1 ms	16.6	22.5	2.9	0.3	70.4
Visual, GLB	0.8	4.4	22.9	1 ms	47.8	0.6	7.1	0.3	83.9
Visual, OBJ	1.0	4.4	24.0	1 ms	46.7	16.2	6.8	0.3	99.4

Board	Repo: tjeerdie/spectre Board: `Speeduino_base.kicad_pcb`
Folder	SPECTRE_V0.5.2
Complexity	267 / 1000 (size 212, features 55)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline
Tested	9th November 2026
Copper layers	2
File format	KiCad 5 (20171130)
Parts, tracks, vias	211, 3,015, 444
Triangles, simulation	4,220,042 in 275 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	145 MB	1.4 GB
STEP	789 MB	1.7 GB
STL	211 MB	1.4 GB
OBJ	451 MB	2.7 GB
Visual
GLB	109 MB	1.8 GB
OBJ	341 MB	2.2 GB

2836. Speeduino_base

Speeduino_base: stages 4 and 6 take 58% to 85% of a run. Simulation, GLB takes 44 s. Simulation, STEP takes 53 s. Simulation, STL takes 47 s. Simulation, OBJ takes 64 s. Visual, GLB takes 73 s. Visual, OBJ takes 88 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	3.8	20.8	2 ms	15.4	0.7	2.4	0.3	44.0
Simulation, STEP	0.8	3.8	20.6	1 ms	15.4	10.2	2.3	0.3	53.3
Simulation, STL	0.8	4.2	21.9	2 ms	16.0	1.3	2.5	0.3	46.9
Simulation, OBJ	0.7	4.0	21.5	1 ms	15.8	19.2	2.6	0.3	64.0
Visual, GLB	0.7	4.1	19.9	2 ms	42.0	0.4	5.7	0.3	73.1
Visual, OBJ	0.6	4.1	20.7	0.8 ms	42.9	13.9	5.3	0.3	87.8

Board	Repo: tjeerdie/spectre Board: `Speeduino_base.kicad_pcb`
Folder	SPECTRE_V0.5.3
Complexity	268 / 1000 (size 213, features 55)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline
Tested	9th November 2026
Copper layers	2
File format	KiCad 5 (20171130)
Parts, tracks, vias	217, 3,070, 450
Triangles, simulation	4,263,228 in 282 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	147 MB	1.4 GB
STEP	799 MB	1.7 GB
STL	213 MB	1.4 GB
OBJ	456 MB	2.8 GB
Visual
GLB	110 MB	1.8 GB
OBJ	346 MB	2.3 GB

2837. Speeduino_base

Speeduino_base: stages 4 and 6 take 58% to 86% of a run. Simulation, GLB takes 39 s. Simulation, STEP takes 48 s. Simulation, STL takes 40 s. Simulation, OBJ takes 55 s. Visual, GLB takes 59 s. Visual, OBJ takes 73 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	3.3	17.9	1 ms	14.1	0.6	1.9	0.3	38.6
Simulation, STEP	0.6	3.5	18.5	1 ms	13.7	9.5	2.1	0.3	48.2
Simulation, STL	0.6	3.4	18.7	0.6 ms	13.9	1.3	2.0	0.3	40.3
Simulation, OBJ	0.6	3.6	18.3	0.8 ms	14.0	16.5	2.0	0.3	55.3
Visual, GLB	0.6	3.3	19.2	2 ms	32.1	0.4	3.6	0.2	59.5
Visual, OBJ	0.6	3.6	19.2	1 ms	34.0	12.0	3.3	0.3	73.0

Board	Repo: tjeerdie/spectre Board: `Speeduino_base.kicad_pcb`
Folder	SPECTRE_V0.5.4
Complexity	262 / 1000 (size 207, features 55)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline
Tested	9th November 2026
Copper layers	2
File format	KiCad 5 (20171130)
Parts, tracks, vias	197, 1,996, 420
Triangles, simulation	3,873,032 in 281 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	133 MB	1.3 GB
STEP	709 MB	1.6 GB
STL	194 MB	1.3 GB
OBJ	415 MB	2.5 GB
Visual
GLB	98 MB	1.8 GB
OBJ	306 MB	2.1 GB

2838. Speeduino_base

Speeduino_base: stages 4 and 6 take 58% to 85% of a run. Simulation, GLB takes 41 s. Simulation, STEP takes 51 s. Simulation, STL takes 40 s. Simulation, OBJ takes 58 s. Visual, GLB takes 61 s. Visual, OBJ takes 75 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	3.8	18.1	1 ms	15.8	0.6	2.0	0.3	41.3
Simulation, STEP	0.7	3.7	18.2	1 ms	15.8	10.3	2.0	0.3	51.0
Simulation, STL	0.7	3.4	17.6	0.7 ms	14.9	1.4	1.9	0.3	40.2
Simulation, OBJ	0.7	3.7	18.5	0.6 ms	15.5	17.7	2.0	0.3	58.3
Visual, GLB	0.7	3.5	17.2	0.7 ms	34.3	0.4	4.6	0.3	61.0
Visual, OBJ	0.6	3.7	18.1	2 ms	34.9	13.1	4.6	0.2	75.2

Board	Repo: tjeerdie/spectre Board: `Speeduino_base.kicad_pcb`
Folder	SPECTRE_V0.5
Complexity	265 / 1000 (size 210, features 55)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline
Tested	9th November 2026
Copper layers	2
File format	KiCad 5 (20171130)
Parts, tracks, vias	213, 2,582, 407
Triangles, simulation	3,773,130 in 220 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	130 MB	1.2 GB
STEP	713 MB	1.6 GB
STL	189 MB	1.2 GB
OBJ	403 MB	2.5 GB
Visual
GLB	98 MB	1.6 GB
OBJ	308 MB	2.1 GB

2839. upsy-desky

upsy-desky: stages 4 and 6 take 53% to 83% of a run. Simulation, GLB takes 4.6 s. Simulation, STEP takes 6.4 s. Simulation, STL takes 4.5 s. Simulation, OBJ takes 6.4 s. Visual, GLB takes 6.1 s. Visual, OBJ takes 7.6 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.4	1.3	0.3 ms	2.0	66 ms	0.2	0.3	4.6
Simulation, STEP	0.2	0.3	1.2	0.2 ms	2.3	2.0	0.2	0.2	6.4
Simulation, STL	0.2	0.3	1.3	0.3 ms	2.2	0.1	0.3	0.2	4.5
Simulation, OBJ	0.2	0.3	1.3	0.3 ms	2.1	2.1	0.2	0.2	6.4
Visual, GLB	0.2	0.3	1.4	0.2 ms	3.7	57 ms	0.3	0.2	6.1
Visual, OBJ	0.2	0.3	1.3	0.4 ms	3.6	1.6	0.4	0.2	7.6

Board	Repo: tjhorner/upsy-desky Board: `upsy-desky.kicad_pcb`
Folder	pcb
Complexity	286 / 1000 (size 201, features 85)
KESE features	through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	44, 391, 48
Triangles, simulation	447,552 in 85 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	15 MB	326 MB
STEP	74 MB	351 MB
STL	22 MB	306 MB
OBJ	45 MB	365 MB
Visual
GLB	12 MB	389 MB
OBJ	35 MB	390 MB

2840. CM4IOv5

CM4IOv5: stages 4 and 6 take 55% to 81% of a run. Simulation, GLB takes 46 s. Simulation, STEP takes 58 s. Simulation, STL takes 47 s. Simulation, OBJ takes 70 s. Visual, GLB takes 76 s. Visual, OBJ takes 89 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.9	4.9	16.9	0.7 ms	20.2	0.7	2.3	0.3	46.1
Simulation, STEP	0.9	4.8	16.8	2 ms	20.8	11.2	2.7	0.4	57.7
Simulation, STL	0.9	4.5	17.0	0.9 ms	20.4	1.5	2.6	0.3	47.1
Simulation, OBJ	0.8	4.5	17.4	1 ms	21.4	23.3	2.6	0.3	70.2
Visual, GLB	0.9	5.3	18.2	0.9 ms	44.0	0.6	7.1	0.4	76.5
Visual, OBJ	0.8	4.5	16.9	0.7 ms	44.3	15.3	6.5	0.3	88.5

Board	Repo: tlalexander/rpi-cm4-switch-board Board: `CM4IOv5.kicad_pcb`
Folder	CM4IO
Complexity	409 / 1000 (size 274, features 135)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours
Tested	9th November 2026
Copper layers	4
File format	KiCad 6 (20201002)
Parts, tracks, vias	137, 5,669, 782
Triangles, simulation	4,961,408 in 261 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	166 MB	1.4 GB
STEP	690 MB	2.0 GB
STL	248 MB	1.4 GB
OBJ	523 MB	3.2 GB
Visual
GLB	116 MB	1.9 GB
OBJ	368 MB	2.4 GB

2841. rpi-cm4-switch-board

rpi-cm4-switch-board: stages 4 and 6 take 60% to 82% of a run. Simulation, GLB takes 16 s. Simulation, STEP takes 21 s. Simulation, STL takes 17 s. Simulation, OBJ takes 22 s. Visual, GLB takes 23 s. Visual, OBJ takes 28 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.5	5.8	0.5 ms	7.3	0.2	0.6	0.3	16.1
Simulation, STEP	0.4	1.5	5.8	0.4 ms	7.5	5.1	0.7	0.2	21.3
Simulation, STL	0.4	1.7	5.9	0.3 ms	7.5	0.5	0.6	0.3	16.9
Simulation, OBJ	0.4	1.4	6.0	0.3 ms	7.3	6.1	0.6	0.3	22.1
Visual, GLB	0.4	1.5	6.0	0.5 ms	12.6	0.2	1.9	0.2	22.7
Visual, OBJ	0.4	1.5	6.3	0.3 ms	13.2	4.6	2.0	0.3	28.1

Board	Repo: tlalexander/rpi-cm4-switch-board Board: `rpi-cm4-switch-board.kicad_pcb`
Folder	hardware / rpi-cm4-switch-board
Complexity	326 / 1000 (size 221, features 105)
KESE features	through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, stack-up, dielectric εr and tanδ, mask and silkscreen colours
Tested	9th November 2026
Copper layers	2
File format	KiCad 6 (20210722)
Parts, tracks, vias	94, 1,008, 34
Triangles, simulation	1,474,964 in 156 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	51 MB	651 MB
STEP	276 MB	738 MB
STL	74 MB	651 MB
OBJ	152 MB	984 MB
Visual
GLB	39 MB	751 MB
OBJ	118 MB	884 MB

2842. add_sub

add_sub: stages 4 and 6 take 51% to 83% of a run. Simulation, GLB takes 15 s. Simulation, STEP takes 20 s. Simulation, STL takes 15 s. Simulation, OBJ takes 23 s. Visual, GLB takes 25 s. Visual, OBJ takes 31 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	1.8	6.6	1 ms	5.5	0.3	0.5	0.2	15.4
Simulation, STEP	0.7	1.9	6.3	0.7 ms	5.7	4.4	0.5	0.2	19.7
Simulation, STL	0.6	1.6	6.0	0.8 ms	5.4	0.5	0.5	0.2	14.8
Simulation, OBJ	0.6	1.6	6.1	0.7 ms	5.4	8.2	0.5	0.2	22.6
Visual, GLB	0.7	1.7	6.1	1 ms	14.3	0.2	1.4	0.3	24.7
Visual, OBJ	0.6	1.7	6.3	0.6 ms	13.4	6.3	2.0	0.3	30.5

Board	Repo: tmarhguy/alu Board: `add_sub.kicad_pcb`
Folder	schematics / kicad / boards / add_sub
Complexity	84 / 1000 (size 74, features 10)
KESE features	rounded, trapezoid or chamfered pads
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	200, 0, 0
Triangles, simulation	1,454,268 in 244 parts
Note	mostly unrouted
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	49 MB	588 MB
STEP	235 MB	784 MB
STL	73 MB	583 MB
OBJ	154 MB	1.0 GB
Visual
GLB	41 MB	992 MB
OBJ	123 MB	849 MB

2843. flags

flags: stages 4 and 6 take 45% to 77% of a run. Simulation, GLB takes 2.3 s. Simulation, STEP takes 3.4 s. Simulation, STL takes 2.4 s. Simulation, OBJ takes 3.4 s. Visual, GLB takes 3.5 s. Visual, OBJ takes 4.4 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.8	0.2 ms	0.7	39 ms	0.1	0.2	2.3
Simulation, STEP	0.1	0.2	1.0	0.2 ms	0.7	1.0	0.1	0.2	3.4
Simulation, STL	0.2	0.2	0.9	0.2 ms	0.8	53 ms	0.1	0.2	2.4
Simulation, OBJ	0.1	0.2	0.8	0.2 ms	0.7	1.2	0.1	0.2	3.4
Visual, GLB	0.1	0.2	0.9	0.2 ms	1.8	26 ms	0.2	0.2	3.5
Visual, OBJ	0.1	0.2	0.9	0.2 ms	1.8	0.9	0.2	0.2	4.4

Board	Repo: tmarhguy/alu Board: `flags.kicad_pcb`
Folder	schematics / kicad / boards / flags
Complexity	62 / 1000 (size 52, features 10)
KESE features	rounded, trapezoid or chamfered pads
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	26, 0, 0
Triangles, simulation	227,560 in 61 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	7.6 MB	216 MB
STEP	32 MB	241 MB
STL	11 MB	222 MB
OBJ	23 MB	216 MB
Visual
GLB	5.7 MB	258 MB
OBJ	16 MB	273 MB

2844. led_panel_1

led_panel_1: stages 4 and 6 take 53% to 82% of a run. Simulation, GLB takes 9.6 s. Simulation, STEP takes 12 s. Simulation, STL takes 9.3 s. Simulation, OBJ takes 14 s. Visual, GLB takes 15 s. Visual, OBJ takes 19 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.0	3.6	0.5 ms	3.8	0.1	0.3	0.2	9.6
Simulation, STEP	0.4	1.0	3.6	0.4 ms	3.6	3.2	0.3	0.3	12.3
Simulation, STL	0.4	1.0	3.4	0.3 ms	3.6	0.5	0.3	0.2	9.3
Simulation, OBJ	0.4	1.0	3.4	0.4 ms	4.0	4.6	0.3	0.2	13.8
Visual, GLB	0.4	1.0	3.5	0.4 ms	8.6	0.1	0.9	0.2	14.7
Visual, OBJ	0.4	1.0	3.5	0.4 ms	8.7	3.7	1.1	0.2	18.5

Board	Repo: tmarhguy/alu Board: `led_panel_1.kicad_pcb`
Folder	schematics / kicad / boards / led_panel / led_panel_1
Complexity	208 / 1000 (size 183, features 25)
KESE features	through vias, rounded, trapezoid or chamfered pads
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	131, 713, 92
Triangles, simulation	885,558 in 82 parts
Note	panel
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	30 MB	492 MB
STEP	167 MB	565 MB
STL	44 MB	493 MB
OBJ	90 MB	631 MB
Visual
GLB	25 MB	564 MB
OBJ	74 MB	703 MB

2845. led_panel_2

led_panel_2: stages 4 and 6 take 51% to 80% of a run. Simulation, GLB takes 6.4 s. Simulation, STEP takes 8.4 s. Simulation, STL takes 6.4 s. Simulation, OBJ takes 9.2 s. Visual, GLB takes 11 s. Visual, OBJ takes 13 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	0.7	2.5	0.6 ms	2.3	87 ms	0.2	0.2	6.4
Simulation, STEP	0.4	0.8	2.4	0.3 ms	2.3	2.1	0.2	0.2	8.4
Simulation, STL	0.3	0.8	2.4	0.3 ms	2.3	0.2	0.2	0.2	6.4
Simulation, OBJ	0.3	0.8	2.5	0.3 ms	2.2	2.9	0.2	0.2	9.2
Visual, GLB	0.3	0.6	2.4	0.3 ms	6.1	85 ms	0.9	0.2	10.6
Visual, OBJ	0.3	0.8	2.3	0.4 ms	6.1	2.4	0.8	0.2	13.0

Board	Repo: tmarhguy/alu Board: `led_panel_2.kicad_pcb`
Folder	schematics / kicad / boards / led_panel / led_panel_2
Complexity	80 / 1000 (size 70, features 10)
KESE features	rounded, trapezoid or chamfered pads
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	129, 0, 0
Triangles, simulation	644,854 in 91 parts
Note	panel, mostly unrouted
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	22 MB	425 MB
STEP	111 MB	477 MB
STL	32 MB	395 MB
OBJ	67 MB	484 MB
Visual
GLB	20 MB	525 MB
OBJ	59 MB	527 MB

2846. led_panel_3

led_panel_3: stages 4 and 6 take 47% to 75% of a run. Simulation, GLB takes 2.3 s. Simulation, STEP takes 3.4 s. Simulation, STL takes 2.4 s. Simulation, OBJ takes 3.2 s. Visual, GLB takes 3.8 s. Visual, OBJ takes 4.7 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.2	0.8	0.2 ms	0.8	36 ms	89 ms	0.2	2.3
Simulation, STEP	0.2	0.2	0.8	0.2 ms	0.8	1.1	96 ms	0.2	3.4
Simulation, STL	0.2	0.2	0.8	0.3 ms	0.8	64 ms	96 ms	0.2	2.4
Simulation, OBJ	0.2	0.2	0.9	0.2 ms	0.7	0.9	0.1	0.2	3.2
Visual, GLB	0.2	0.2	0.8	0.2 ms	2.1	31 ms	0.3	0.2	3.8
Visual, OBJ	0.1	0.2	0.8	0.2 ms	2.2	0.9	0.3	0.2	4.7

Board	Repo: tmarhguy/alu Board: `led_panel_3.kicad_pcb`
Folder	schematics / kicad / boards / led_panel / led_panel_3
Complexity	66 / 1000 (size 56, features 10)
KESE features	rounded, trapezoid or chamfered pads
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	35, 0, 0
Triangles, simulation	209,734 in 47 parts
Note	panel
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	7.2 MB	227 MB
STEP	32 MB	238 MB
STL	10 MB	220 MB
OBJ	21 MB	229 MB
Visual
GLB	5.9 MB	229 MB
OBJ	17 MB	238 MB

2847. main_control

main_control: stages 4 and 6 take 56% to 81% of a run. Simulation, GLB takes 5.6 s. Simulation, STEP takes 6.6 s. Simulation, STL takes 4.9 s. Simulation, OBJ takes 7.6 s. Visual, GLB takes 8.7 s. Visual, OBJ takes 9.7 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.5	2.3	2 ms	2.1	90 ms	0.2	0.2	5.6
Simulation, STEP	0.2	0.4	2.0	0.4 ms	1.9	1.7	0.2	0.2	6.6
Simulation, STL	0.2	0.4	2.0	0.5 ms	1.8	0.2	0.2	0.2	4.9
Simulation, OBJ	0.2	0.5	2.1	0.5 ms	2.1	2.3	0.2	0.2	7.6
Visual, GLB	0.2	0.4	2.2	0.6 ms	4.8	74 ms	0.8	0.2	8.7
Visual, OBJ	0.2	0.5	2.0	0.6 ms	4.6	1.8	0.5	0.2	9.7

Board	Repo: tmarhguy/alu Board: `main_control.kicad_pcb`
Folder	schematics / kicad / boards / main_control
Complexity	68 / 1000 (size 58, features 10)
KESE features	rounded, trapezoid or chamfered pads
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	42, 0, 0
Triangles, simulation	561,324 in 172 parts
Note	mostly unrouted
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	19 MB	317 MB
STEP	88 MB	397 MB
STL	28 MB	317 MB
OBJ	58 MB	431 MB
Visual
GLB	15 MB	468 MB
OBJ	45 MB	509 MB

2848. main_logic

main_logic: stages 4 and 6 take 52% to 84% of a run. Simulation, GLB takes 10 s. Simulation, STEP takes 14 s. Simulation, STL takes 11 s. Simulation, OBJ takes 16 s. Visual, GLB takes 17 s. Visual, OBJ takes 22 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.1	4.7	2 ms	3.5	0.2	0.4	0.2	10.5
Simulation, STEP	0.3	1.1	4.6	0.9 ms	4.3	3.4	0.4	0.2	14.3
Simulation, STL	0.4	1.2	4.6	0.6 ms	3.6	0.3	0.4	0.3	10.8
Simulation, OBJ	0.4	1.2	4.8	0.7 ms	3.7	5.7	0.4	0.3	16.3
Visual, GLB	0.3	1.0	4.8	1.0 ms	9.8	0.1	1.1	0.2	17.5
Visual, OBJ	0.4	1.2	5.4	1 ms	9.9	4.2	1.2	0.2	22.5

Board	Repo: tmarhguy/alu Board: `main_logic.kicad_pcb`
Folder	schematics / kicad / boards / main_logic
Complexity	79 / 1000 (size 69, features 10)
KESE features	rounded, trapezoid or chamfered pads
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	122, 0, 0
Triangles, simulation	1,212,090 in 206 parts
Note	mostly unrouted
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	41 MB	503 MB
STEP	194 MB	639 MB
STL	61 MB	533 MB
OBJ	127 MB	843 MB
Visual
GLB	32 MB	633 MB
OBJ	97 MB	744 MB

2849. gate_and_2in

gate_and_2in: stages 4 and 6 take 44% to 73% of a run. Simulation, GLB takes 1.6 s. Simulation, STEP takes 2.5 s. Simulation, STL takes 1.6 s. Simulation, OBJ takes 2.2 s. Visual, GLB takes 2.1 s. Visual, OBJ takes 2.4 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.1	0.5	0.1 ms	0.6	18 ms	67 ms	0.2	1.6
Simulation, STEP	0.1	0.1	0.4	0.2 ms	0.6	0.8	78 ms	0.2	2.5
Simulation, STL	0.1	0.1	0.4	0.1 ms	0.6	36 ms	70 ms	0.3	1.6
Simulation, OBJ	88 ms	0.1	0.5	0.1 ms	0.7	0.5	65 ms	0.2	2.2
Visual, GLB	0.1	0.1	0.5	0.1 ms	1.0	14 ms	97 ms	0.2	2.1
Visual, OBJ	96 ms	0.1	0.4	0.1 ms	1.0	0.4	91 ms	0.2	2.4

Board	Repo: tmarhguy/alu Board: `gate_and_2in.kicad_pcb`
Folder	schematics / kicad / modules / gates / gate_and / gate_and_2in
Complexity	119 / 1000 (size 104, features 15)
KESE features	through vias
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	6, 42, 5
Triangles, simulation	103,594 in 17 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	3.4 MB	174 MB
STEP	13 MB	187 MB
STL	5.2 MB	180 MB
OBJ	9.8 MB	175 MB
Visual
GLB	2.2 MB	151 MB
OBJ	6.2 MB	150 MB

2850. gate_and_4in

gate_and_4in: stages 4 and 6 take 38% to 57% of a run. Simulation, GLB takes 0.9 s. Simulation, STEP takes 1.3 s. Simulation, STL takes 0.8 s. Simulation, OBJ takes 1.1 s. Visual, GLB takes 1.1 s. Visual, OBJ takes 1.4 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	88 ms	67 ms	0.2	0.2 ms	0.3	10 ms	24 ms	0.2	0.9
Simulation, STEP	0.1	62 ms	0.2	0.2 ms	0.3	0.4	24 ms	0.2	1.3
Simulation, STL	86 ms	61 ms	0.2	0.3 ms	0.3	11 ms	23 ms	0.2	0.8
Simulation, OBJ	0.1	74 ms	0.1	0.1 ms	0.3	0.2	32 ms	0.3	1.1
Visual, GLB	89 ms	62 ms	0.2	0.1 ms	0.5	8 ms	85 ms	0.2	1.1
Visual, OBJ	0.1	67 ms	0.1	0.2 ms	0.6	0.2	69 ms	0.2	1.4

Board	Repo: tmarhguy/alu Board: `gate_and_4in.kicad_pcb`
Folder	schematics / kicad / modules / gates / gate_and / gate_and_4in
Complexity	53 / 1000 (size 43, features 10)
KESE features	rounded, trapezoid or chamfered pads
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	10, 0, 0
Triangles, simulation	40,752 in 17 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	1.4 MB	69 MB
STEP	6.0 MB	73 MB
STL	2.0 MB	71 MB
OBJ	4.0 MB	79 MB
Visual
GLB	1.4 MB	102 MB
OBJ	3.8 MB	100 MB

2851. gate_inv_1bit

gate_inv_1bit: stages 4 and 6 take 42% to 59% of a run. Simulation, GLB takes 0.7 s. Simulation, STEP takes 1.0 s. Simulation, STL takes 0.8 s. Simulation, OBJ takes 0.9 s. Visual, GLB takes 0.8 s. Visual, OBJ takes 0.9 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	66 ms	38 ms	0.1	0.1 ms	0.2	7 ms	24 ms	0.2	0.7
Simulation, STEP	63 ms	40 ms	0.1	0.1 ms	0.3	0.3	26 ms	0.2	1.0
Simulation, STL	72 ms	65 ms	0.1	0.1 ms	0.3	12 ms	22 ms	0.2	0.8
Simulation, OBJ	77 ms	42 ms	0.1	0.1 ms	0.3	0.1	25 ms	0.2	0.9
Visual, GLB	67 ms	42 ms	0.1	0.1 ms	0.3	6 ms	45 ms	0.2	0.8
Visual, OBJ	71 ms	41 ms	0.1	0.1 ms	0.3	80 ms	36 ms	0.2	0.9

Board	Repo: tmarhguy/alu Board: `gate_inv_1bit.kicad_pcb`
Folder	schematics / kicad / modules / gates / gate_inv / gate_inv_1bit
Complexity	65 / 1000 (size 65, features 0)
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	2, 8, 0
Triangles, simulation	33,822 in 14 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	1.1 MB	64 MB
STEP	4.2 MB	68 MB
STL	1.7 MB	65 MB
OBJ	3.2 MB	71 MB
Visual
GLB	764 kB	100 MB
OBJ	2.1 MB	100 MB

2852. gate_nand_2in

gate_nand_2in: stages 4 and 6 take 41% to 70% of a run. Simulation, GLB takes 1.1 s. Simulation, STEP takes 1.8 s. Simulation, STL takes 1.1 s. Simulation, OBJ takes 1.5 s. Visual, GLB takes 1.6 s. Visual, OBJ takes 1.8 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	74 ms	78 ms	0.3	0.1 ms	0.4	11 ms	36 ms	0.2	1.1
Simulation, STEP	75 ms	79 ms	0.3	0.2 ms	0.4	0.7	38 ms	0.2	1.8
Simulation, STL	73 ms	79 ms	0.3	0.1 ms	0.5	16 ms	38 ms	0.2	1.1
Simulation, OBJ	84 ms	77 ms	0.3	0.1 ms	0.4	0.4	40 ms	0.2	1.5
Visual, GLB	76 ms	96 ms	0.3	0.1 ms	0.8	10 ms	75 ms	0.2	1.6
Visual, OBJ	79 ms	85 ms	0.3	0.1 ms	0.8	0.3	87 ms	0.2	1.8

Board	Repo: tmarhguy/alu Board: `gate_nand_2in.kicad_pcb`
Folder	schematics / kicad / modules / gates / gate_nand / gate_nand_2in
Complexity	105 / 1000 (size 90, features 15)
KESE features	through vias
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	4, 24, 2
Triangles, simulation	71,860 in 16 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	2.4 MB	170 MB
STEP	9.3 MB	174 MB
STL	3.6 MB	172 MB
OBJ	6.8 MB	168 MB
Visual
GLB	1.6 MB	149 MB
OBJ	4.4 MB	150 MB

2853. gate_nor_2in

gate_nor_2in: stages 4 and 6 take 44% to 66% of a run. Simulation, GLB takes 1.3 s. Simulation, STEP takes 2.1 s. Simulation, STL takes 1.3 s. Simulation, OBJ takes 1.7 s. Visual, GLB takes 1.4 s. Visual, OBJ takes 1.6 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	87 ms	81 ms	0.3	0.2 ms	0.6	12 ms	46 ms	0.2	1.3
Simulation, STEP	86 ms	74 ms	0.3	0.1 ms	0.6	0.8	45 ms	0.2	2.1
Simulation, STL	88 ms	88 ms	0.3	0.1 ms	0.5	17 ms	43 ms	0.2	1.3
Simulation, OBJ	83 ms	72 ms	0.3	0.1 ms	0.6	0.4	50 ms	0.2	1.7
Visual, GLB	92 ms	75 ms	0.3	0.2 ms	0.6	8 ms	80 ms	0.2	1.4
Visual, OBJ	87 ms	76 ms	0.3	0.1 ms	0.6	0.2	69 ms	0.2	1.6

Board	Repo: tmarhguy/alu Board: `gate_nor_2in.kicad_pcb`
Folder	schematics / kicad / modules / gates / gate_nor / gate_nor_2in_1bit
Complexity	104 / 1000 (size 89, features 15)
KESE features	through vias
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	4, 24, 1
Triangles, simulation	66,598 in 16 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	2.2 MB	71 MB
STEP	8.7 MB	180 MB
STL	3.3 MB	72 MB
OBJ	6.3 MB	97 MB
Visual
GLB	1.4 MB	102 MB
OBJ	3.9 MB	116 MB

2854. gate_or_2in

gate_or_2in: stages 4 and 6 take 45% to 75% of a run. Simulation, GLB takes 1.6 s. Simulation, STEP takes 2.4 s. Simulation, STL takes 1.6 s. Simulation, OBJ takes 2.3 s. Visual, GLB takes 2.2 s. Visual, OBJ takes 2.6 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.1	0.5	0.1 ms	0.6	21 ms	76 ms	0.2	1.6
Simulation, STEP	0.1	0.1	0.5	0.1 ms	0.6	0.8	77 ms	0.2	2.4
Simulation, STL	96 ms	0.1	0.5	0.2 ms	0.6	28 ms	71 ms	0.2	1.6
Simulation, OBJ	96 ms	0.1	0.5	0.1 ms	0.6	0.7	0.1	0.2	2.3
Visual, GLB	99 ms	0.1	0.5	0.2 ms	1.1	15 ms	93 ms	0.2	2.2
Visual, OBJ	98 ms	0.1	0.5	0.1 ms	1.1	0.5	84 ms	0.2	2.6

Board	Repo: tmarhguy/alu Board: `gate_or_2in.kicad_pcb`
Folder	schematics / kicad / modules / gates / gate_or / gate_or_2in
Complexity	137 / 1000 (size 102, features 35)
KESE features	through vias, filled zones
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	6, 40, 3
Triangles, simulation	127,190 in 17 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	4.3 MB	189 MB
STEP	18 MB	197 MB
STL	6.4 MB	183 MB
OBJ	12 MB	186 MB
Visual
GLB	2.9 MB	156 MB
OBJ	8.2 MB	157 MB

2855. gate_xnor_2in

gate_xnor_2in: stages 4 and 6 take 48% to 79% of a run. Simulation, GLB takes 3.1 s. Simulation, STEP takes 4.1 s. Simulation, STL takes 3.2 s. Simulation, OBJ takes 4.7 s. Visual, GLB takes 4.0 s. Visual, OBJ takes 5.2 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	1.2	0.2 ms	1.0	50 ms	0.2	0.2	3.1
Simulation, STEP	0.1	0.2	1.2	0.2 ms	0.9	1.2	0.2	0.2	4.1
Simulation, STL	0.1	0.3	1.2	0.4 ms	1.1	71 ms	0.2	0.2	3.2
Simulation, OBJ	0.1	0.2	1.3	0.2 ms	0.9	1.7	0.2	0.2	4.7
Visual, GLB	0.1	0.2	1.1	0.2 ms	2.1	30 ms	0.3	0.2	4.0
Visual, OBJ	0.1	0.3	1.1	0.2 ms	2.1	1.1	0.2	0.2	5.2

Board	Repo: tmarhguy/alu Board: `gate_xnor_2in.kicad_pcb`
Folder	schematics / kicad / modules / gates / gate_xnor / gate_xnor_2in
Complexity	167 / 1000 (size 132, features 35)
KESE features	through vias, filled zones
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	16, 138, 12
Triangles, simulation	325,442 in 23 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	11 MB	254 MB
STEP	47 MB	275 MB
STL	16 MB	246 MB
OBJ	32 MB	267 MB
Visual
GLB	7.2 MB	249 MB
OBJ	21 MB	246 MB

2856. gate_xor_2in

gate_xor_2in: stages 4 and 6 take 48% to 77% of a run. Simulation, GLB takes 3.0 s. Simulation, STEP takes 4.0 s. Simulation, STL takes 2.8 s. Simulation, OBJ takes 4.3 s. Visual, GLB takes 3.8 s. Visual, OBJ takes 4.5 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	1.1	0.5 ms	1.1	43 ms	0.1	0.3	3.0
Simulation, STEP	0.1	0.2	1.2	0.3 ms	1.0	1.1	0.1	0.2	4.0
Simulation, STL	0.1	0.2	1.0	0.2 ms	1.0	69 ms	0.1	0.2	2.8
Simulation, OBJ	0.1	0.2	1.1	0.2 ms	1.0	1.5	0.2	0.3	4.3
Visual, GLB	0.1	0.2	1.0	0.3 ms	1.9	28 ms	0.2	0.2	3.8
Visual, OBJ	0.1	0.2	1.0	0.3 ms	1.9	0.8	0.3	0.2	4.5

Board	Repo: tmarhguy/alu Board: `gate_xor_2in.kicad_pcb`
Folder	schematics / kicad / modules / gates / gate_xor / gate_xor_2in
Complexity	146 / 1000 (size 131, features 15)
KESE features	through vias
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	16, 120, 16
Triangles, simulation	269,400 in 22 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	8.9 MB	220 MB
STEP	35 MB	250 MB
STL	13 MB	232 MB
OBJ	26 MB	233 MB
Visual
GLB	5.7 MB	215 MB
OBJ	16 MB	216 MB

2857. RASANT2400

RASANT2400: stages 4 and 6 take 34% to 61% of a run. Simulation, GLB takes 1.1 s. Simulation, STEP takes 2.0 s. Simulation, STL takes 1.2 s. Simulation, OBJ takes 1.4 s. Visual, GLB takes 1.5 s. Visual, OBJ takes 1.8 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	99 ms	0.2	0.1 ms	0.5	12 ms	28 ms	0.2	1.1
Simulation, STEP	0.1	95 ms	0.3	0.2 ms	0.4	0.9	23 ms	0.2	2.0
Simulation, STL	0.1	0.1	0.2	0.1 ms	0.5	18 ms	29 ms	0.2	1.2
Simulation, OBJ	0.1	0.1	0.2	0.1 ms	0.4	0.3	32 ms	0.2	1.4
Visual, GLB	0.1	0.1	0.2	0.1 ms	0.7	13 ms	91 ms	0.2	1.5
Visual, OBJ	0.1	0.1	0.3	0.1 ms	0.7	0.3	96 ms	0.2	1.8

Board	Repo: tobias-dg3yev/ra-sentinel Board: `RASANT2400.kicad_pcb`
Folder	RASANT2400 / Hardware / KiCad
Complexity	131 / 1000 (size 91, features 40)
KESE features	through vias, arc tracks, copper drawings
Tested	9th November 2026
Copper layers	2
File format	KiCad 10 (20260206)
Parts, tracks, vias	0, 20, 24
Triangles, simulation	70,964 in 11 parts
Note	no components
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	2.6 MB	87 MB
STEP	5.9 MB	200 MB
STL	3.5 MB	88 MB
OBJ	7.0 MB	114 MB
Visual
GLB	2.3 MB	125 MB
OBJ	6.4 MB	125 MB

2858. RASBB

RASBB: stages 4 and 6 take 44% to 83% of a run. Simulation, GLB takes 2 min. Simulation, STEP takes 2 min. Simulation, STL takes 2 min. Simulation, OBJ takes 3 min. Visual, GLB takes 3 min. Visual, OBJ takes 4 min

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	3.7	15.0	34.1	2 ms	51.6	3.2	7.8	0.5	115.9
Simulation, STEP	3.7	13.8	33.6	2 ms	50.7	29.6	7.8	0.6	139.8
Simulation, STL	3.6	14.4	33.6	2 ms	51.7	6.2	8.0	0.6	118.0
Simulation, OBJ	3.8	14.5	34.4	2 ms	50.6	79.9	9.0	0.6	192.8
Visual, GLB	3.8	15.3	33.6	2 ms	115.2	1.2	10.8	0.4	180.4
Visual, OBJ	3.6	15.0	35.5	2 ms	116.7	37.4	11.8	0.4	220.4

Board	Repo: tobias-dg3yev/ra-sentinel Board: `RASBB.kicad_pcb`
Folder	RASBB / Hardware / Rev.A / Design
Complexity	481 / 1000 (size 346, features 135)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	8
File format	KiCad 10 (20260206)
Parts, tracks, vias	580, 11,520, 1,908
Triangles, simulation	16,234,920 in 757 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	539 MB	3.6 GB
STEP	1.7 GB	5.0 GB
STL	812 MB	3.6 GB
OBJ	1.8 GB	10 GB
Visual
GLB	256 MB	4.4 GB
OBJ	860 MB	5.6 GB

2859. RASBB

RASBB: stages 4 and 6 take 42% to 82% of a run. Simulation, GLB takes 2 min. Simulation, STEP takes 3 min. Simulation, STL takes 2 min. Simulation, OBJ takes 4 min. Visual, GLB takes 3 min. Visual, OBJ takes 4 min

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	3.9	16.7	40.3	2 ms	59.8	3.3	10.2	0.5	134.7
Simulation, STEP	3.9	16.2	39.4	2 ms	60.1	34.2	11.0	0.8	165.6
Simulation, STL	4.0	16.8	40.6	3 ms	60.3	7.0	9.7	0.7	139.2
Simulation, OBJ	3.6	15.6	35.9	2 ms	56.6	97.5	9.2	0.5	219.0
Visual, GLB	3.8	15.7	34.6	3 ms	128.7	1.5	14.6	0.4	199.4
Visual, OBJ	3.6	15.2	34.8	3 ms	129.3	41.0	13.8	0.4	238.2

Board	Repo: tobias-dg3yev/ra-sentinel Board: `RASBB.kicad_pcb`
Folder	RASBB / Hardware / Rev.B / Design
Complexity	482 / 1000 (size 347, features 135)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	8
File format	KiCad 10 (20260206)
Parts, tracks, vias	616, 12,047, 1,915
Triangles, simulation	16,458,470 in 765 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	547 MB	3.6 GB
STEP	1.7 GB	4.9 GB
STL	823 MB	3.7 GB
OBJ	1.8 GB	10 GB
Visual
GLB	260 MB	4.4 GB
OBJ	875 MB	5.7 GB

2860. RASBB

RASBB: stages 4 and 6 take 44% to 83% of a run. Simulation, GLB takes 2 min. Simulation, STEP takes 3 min. Simulation, STL takes 2 min. Simulation, OBJ takes 4 min. Visual, GLB takes 4 min. Visual, OBJ takes 5 min

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	4.0	17.8	44.0	2 ms	64.4	4.1	10.7	0.6	145.7
Simulation, STEP	4.2	17.7	43.1	4 ms	64.7	39.0	10.7	0.7	180.1
Simulation, STL	4.3	17.5	43.4	2 ms	63.8	9.3	10.7	0.7	149.7
Simulation, OBJ	4.3	17.9	43.0	2 ms	59.2	96.7	11.1	0.8	232.9
Visual, GLB	4.4	18.5	44.3	2 ms	162.4	1.8	18.4	0.6	250.4
Visual, OBJ	4.5	17.9	42.1	3 ms	154.9	51.7	17.3	0.7	289.1

Board	Repo: tobias-dg3yev/ra-sentinel Board: `RASBB.kicad_pcb`
Folder	RASBB / Hardware / Rev.C / Design
Complexity	485 / 1000 (size 350, features 135)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, stack-up, dielectric εr and tanδ
Tested	9th November 2026 to 10th November 2026
Copper layers	8
File format	KiCad 10 (20260206)
Parts, tracks, vias	689, 14,138, 2,078
Triangles, simulation	17,831,050 in 809 parts
Verifier	PASS in all six runs
Run again	Simulation, OBJ: failed in the corpus run, run again with the memory cap raised from 11 GB to 14.5 GB, and passed

File type	File size	Peak memory used
Simulation
GLB	594 MB	3.8 GB
STEP	1.9 GB	5.6 GB
STL	892 MB	3.9 GB
OBJ	2.0 GB	11 GB
Visual
GLB	289 MB	4.8 GB
OBJ	968 MB	6.2 GB

2861. RASRF

RASRF: stages 4 and 6 take 49% to 80% of a run. Simulation, GLB takes 19 s. Simulation, STEP takes 24 s. Simulation, STL takes 19 s. Simulation, OBJ takes 29 s. Visual, GLB takes 30 s. Visual, OBJ takes 38 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.9	2.1	6.5	0.9 ms	7.9	0.4	0.9	0.2	19.0
Simulation, STEP	1.0	2.3	6.5	0.8 ms	7.9	5.3	0.9	0.2	24.1
Simulation, STL	0.8	2.1	6.7	1 ms	7.5	0.7	0.9	0.3	19.0
Simulation, OBJ	0.9	2.0	6.4	0.9 ms	7.7	10.6	0.9	0.3	28.8
Visual, GLB	1.0	2.3	6.5	1.0 ms	17.2	0.3	2.1	0.2	29.6
Visual, OBJ	0.9	2.0	7.0	1.0 ms	16.9	8.2	2.7	0.2	38.0

Board	Repo: tobias-dg3yev/ra-sentinel Board: `RASRF.kicad_pcb`
Folder	RASRF2400WB / Hardware / PCB_Design
Complexity	337 / 1000 (size 217, features 120)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, stack-up, dielectric εr and tanδ, mask and silkscreen colours
Tested	9th November 2026
Copper layers	4
File format	KiCad 10 (20260206)
Parts, tracks, vias	147, 1,319, 468
Triangles, simulation	2,326,330 in 185 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	79 MB	938 MB
STEP	308 MB	1.1 GB
STL	116 MB	956 MB
OBJ	241 MB	1.5 GB
Visual
GLB	56 MB	1.1 GB
OBJ	174 MB	1.2 GB

2862. RASRF2400WBMC

RASRF2400WBMC: stages 4 and 6 take 44% to 83% of a run. Simulation, GLB takes 58 s. Simulation, STEP takes 72 s. Simulation, STL takes 59 s. Simulation, OBJ takes 2 min. Visual, GLB takes 2 min. Visual, OBJ takes 2 min

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.9	7.5	19.0	1 ms	24.8	1.1	3.0	0.4	57.6
Simulation, STEP	1.8	7.0	19.4	2 ms	25.5	14.8	3.0	0.3	72.0
Simulation, STL	1.8	7.7	18.5	2 ms	24.5	2.8	3.0	0.4	58.7
Simulation, OBJ	2.1	7.3	19.2	1 ms	24.9	42.7	3.1	0.4	99.7
Visual, GLB	2.0	7.7	20.6	2 ms	65.1	0.7	7.2	0.3	103.6
Visual, OBJ	2.2	8.4	22.1	1 ms	63.5	23.6	7.5	0.4	127.8

Board	Repo: tobias-dg3yev/ra-sentinel Board: `RASRF2400WBMC.kicad_pcb`
Folder	RASRF2400WBMC / Hardware / KiCad
Complexity	394 / 1000 (size 304, features 90)
KESE features	through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, stack-up, dielectric εr and tanδ
Tested	10th November 2026
Copper layers	6
File format	KiCad 10 (20260206)
Parts, tracks, vias	388, 4,374, 921
Triangles, simulation	6,665,854 in 375 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	223 MB	2.2 GB
STEP	737 MB	2.5 GB
STL	333 MB	2.1 GB
OBJ	723 MB	4.2 GB
Visual
GLB	124 MB	2.1 GB
OBJ	407 MB	2.7 GB

2863. pocket_sdr_v2.3

pocket_sdr_v2.3: stages 4 and 6 take 54% to 83% of a run. Simulation, GLB takes 11 s. Simulation, STEP takes 13 s. Simulation, STL takes 11 s. Simulation, OBJ takes 16 s. Visual, GLB takes 17 s. Visual, OBJ takes 20 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.0	4.8	0.3 ms	3.8	0.2	0.5	0.2	10.8
Simulation, STEP	0.3	1.0	4.9	0.3 ms	3.9	2.6	0.5	0.2	13.3
Simulation, STL	0.3	1.0	4.7	0.3 ms	3.9	0.5	0.4	0.2	11.0
Simulation, OBJ	0.3	1.0	4.6	0.2 ms	4.0	5.4	0.5	0.2	16.1
Visual, GLB	0.3	1.1	4.8	0.3 ms	8.9	0.1	1.1	0.2	16.6
Visual, OBJ	0.3	1.0	4.6	0.3 ms	8.8	3.5	1.1	0.2	19.5

Board	Repo: tomojitakasu/PocketSDR Board: `pocket_sdr_v2.3.kicad_pcb`
Folder	FE_2CH / HW / v2.3
Complexity	351 / 1000 (size 251, features 100)
KESE features	through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 7 (20221018)
Parts, tracks, vias	76, 792, 240
Triangles, simulation	1,335,824 in 94 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	46 MB	583 MB
STEP	187 MB	686 MB
STL	67 MB	523 MB
OBJ	138 MB	910 MB
Visual
GLB	30 MB	670 MB
OBJ	90 MB	688 MB

2864. v3.0

v3.0: stages 4 and 6 take 56% to 85% of a run. Simulation, GLB takes 31 s. Simulation, STEP takes 38 s. Simulation, STL takes 32 s. Simulation, OBJ takes 45 s. Visual, GLB takes 52 s. Visual, OBJ takes 65 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	3.0	13.1	0.9 ms	11.8	0.6	1.4	0.3	30.8
Simulation, STEP	0.6	3.2	13.8	0.6 ms	11.8	7.2	1.4	0.3	38.3
Simulation, STL	0.7	3.1	13.6	0.6 ms	11.8	0.9	1.4	0.3	31.7
Simulation, OBJ	0.7	3.0	13.3	0.9 ms	11.7	14.5	1.4	0.3	45.0
Visual, GLB	0.7	3.0	14.2	0.6 ms	30.1	0.3	3.4	0.3	52.0
Visual, OBJ	0.6	3.0	14.3	0.5 ms	31.7	10.5	4.1	0.3	64.6

Board	Repo: tomojitakasu/PocketSDR Board: `v3.0.kicad_pcb`
Folder	FE_4CH / HW / v3.0
Complexity	384 / 1000 (size 284, features 100)
KESE features	through vias, slotted holes, arc tracks, filled zones, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 8 (20240108)
Parts, tracks, vias	149, 2,287, 626
Triangles, simulation	3,206,818 in 200 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	111 MB	1.1 GB
STEP	459 MB	1.4 GB
STL	160 MB	1.1 GB
OBJ	345 MB	2.1 GB
Visual
GLB	73 MB	1.3 GB
OBJ	232 MB	1.6 GB

2865. div_4px2

div_4px2: stages 4 and 6 take 54% to 80% of a run. Simulation, GLB takes 21 s. Simulation, STEP takes 23 s. Simulation, STL takes 21 s. Simulation, OBJ takes 30 s. Visual, GLB takes 21 s. Visual, OBJ takes 27 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	2.8	5.9	0.7 ms	10.6	0.3	0.6	0.2	20.6
Simulation, STEP	0.3	2.7	5.9	0.1 ms	10.6	2.8	0.6	0.3	23.3
Simulation, STL	0.3	2.8	6.0	0.7 ms	10.0	0.6	0.6	0.3	20.6
Simulation, OBJ	0.3	2.8	6.0	0.5 ms	10.2	9.6	0.6	0.3	29.8
Visual, GLB	0.3	2.8	6.3	0.6 ms	10.0	0.2	1.1	0.2	20.9
Visual, OBJ	0.3	2.8	6.2	0.6 ms	10.2	6.1	1.3	0.3	27.2

Board	Repo: tomojitakasu/PocketSDR Board: `div_4px2.kicad_pcb`
Folder	FE_8CH / HW / div_4px2
Complexity	294 / 1000 (size 204, features 90)
KESE features	through vias, arc tracks, filled zones, curved board outline, stack-up, dielectric εr and tanδ
Tested	10th November 2026
Copper layers	4
File format	KiCad 8 (20240108)
Parts, tracks, vias	42, 138, 894
Triangles, simulation	1,796,100 in 40 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	59 MB	862 MB
STEP	87 MB	956 MB
STL	90 MB	858 MB
OBJ	183 MB	1.2 GB
Visual
GLB	34 MB	703 MB
OBJ	106 MB	843 MB

2866. v4.0

v4.0: stages 4 and 6 take 55% to 83% of a run. Simulation, GLB takes 62 s. Simulation, STEP takes 70 s. Simulation, STL takes 61 s. Simulation, OBJ takes 87 s. Visual, GLB takes 93 s. Visual, OBJ takes 2 min

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.1	6.7	27.5	2 ms	22.4	1.0	2.4	0.3	61.5
Simulation, STEP	1.2	6.8	26.7	1 ms	21.4	11.3	2.5	0.4	70.3
Simulation, STL	1.3	7.0	26.8	2 ms	20.8	2.1	2.5	0.3	60.8
Simulation, OBJ	1.3	6.7	27.1	2 ms	21.1	28.5	2.4	0.3	87.3
Visual, GLB	1.1	6.5	27.6	1 ms	49.9	0.6	7.3	0.3	93.4
Visual, OBJ	1.1	6.8	27.5	2 ms	49.2	18.1	7.0	0.3	109.9

Board	Repo: tomojitakasu/PocketSDR Board: `v4.0.kicad_pcb`
Folder	FE_8CH / HW / v4.0
Complexity	402 / 1000 (size 302, features 100)
KESE features	through vias, slotted holes, arc tracks, filled zones, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 8 (20240108)
Parts, tracks, vias	233, 3,065, 1,445
Triangles, simulation	5,577,956 in 260 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	191 MB	1.9 GB
STEP	669 MB	2.2 GB
STL	279 MB	2.0 GB
OBJ	602 MB	3.6 GB
Visual
GLB	120 MB	2.0 GB
OBJ	389 MB	2.6 GB

2867. v4.1

v4.1: stages 4 and 6 take 53% to 83% of a run. Simulation, GLB takes 72 s. Simulation, STEP takes 86 s. Simulation, STL takes 73 s. Simulation, OBJ takes 2 min. Visual, GLB takes 2 min. Visual, OBJ takes 2 min

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.2	8.0	31.5	2 ms	27.6	1.0	2.6	0.3	72.4
Simulation, STEP	1.2	8.4	32.0	0.9 ms	28.6	12.7	2.6	0.4	85.9
Simulation, STL	1.2	8.2	31.4	1 ms	27.0	2.0	2.6	0.3	72.8
Simulation, OBJ	1.2	8.2	31.7	1 ms	26.1	38.1	2.7	0.3	108.3
Visual, GLB	1.3	8.5	31.9	2 ms	56.6	0.6	7.4	0.3	106.5
Visual, OBJ	1.2	8.3	32.5	1 ms	55.9	23.7	7.0	0.3	128.9

Board	Repo: tomojitakasu/PocketSDR Board: `v4.1.kicad_pcb`
Folder	FE_8CH / HW / v4.1
Complexity	403 / 1000 (size 303, features 100)
KESE features	through vias, slotted holes, arc tracks, filled zones, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 8 (20240108)
Parts, tracks, vias	216, 3,080, 1,765
Triangles, simulation	6,053,476 in 262 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	206 MB	1.7 GB
STEP	673 MB	2.5 GB
STL	303 MB	1.9 GB
OBJ	651 MB	3.9 GB
Visual
GLB	128 MB	2.1 GB
OBJ	418 MB	2.8 GB

2868. Coin_Cell_Tester

Coin_Cell_Tester: stages 4 and 6 take 52% to 82% of a run. Simulation, GLB takes 19 s. Simulation, STEP takes 25 s. Simulation, STL takes 19 s. Simulation, OBJ takes 29 s. Visual, GLB takes 31 s. Visual, OBJ takes 38 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	1.8	7.9	0.8 ms	7.2	0.3	0.8	0.3	18.8
Simulation, STEP	0.6	1.7	8.1	0.9 ms	7.4	6.2	0.8	0.2	25.1
Simulation, STL	0.8	1.8	8.2	0.7 ms	7.0	0.6	0.8	0.2	19.4
Simulation, OBJ	0.8	1.7	7.6	0.7 ms	7.2	10.2	0.9	0.3	28.6
Visual, GLB	0.7	1.9	8.1	0.8 ms	17.1	0.3	2.4	0.3	30.7
Visual, OBJ	0.7	1.7	7.8	0.6 ms	15.9	8.6	2.7	0.2	37.6

Board	Repo: tomrodinger/servomotor Board: `Coin_Cell_Tester.kicad_pcb`
Folder	PCB / Coin_Cell_Tester / PCB / V1
Complexity	322 / 1000 (size 237, features 85)
KESE features	through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 6 (20211014)
Parts, tracks, vias	193, 1,281, 181
Triangles, simulation	1,879,786 in 102 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	64 MB	730 MB
STEP	339 MB	878 MB
STL	94 MB	671 MB
OBJ	195 MB	1.3 GB
Visual
GLB	52 MB	1.1 GB
OBJ	157 MB	1.2 GB

2869. Coin_Cell_Tester

Coin_Cell_Tester: stages 4 and 6 take 52% to 83% of a run. Simulation, GLB takes 18 s. Simulation, STEP takes 24 s. Simulation, STL takes 18 s. Simulation, OBJ takes 28 s. Visual, GLB takes 29 s. Visual, OBJ takes 39 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	1.8	7.5	0.7 ms	6.6	0.3	0.7	0.3	17.8
Simulation, STEP	0.7	1.8	7.6	0.6 ms	6.6	5.8	0.7	0.3	23.5
Simulation, STL	0.7	1.8	7.5	0.7 ms	6.6	0.6	0.7	0.3	18.2
Simulation, OBJ	0.7	1.8	7.8	0.6 ms	6.4	9.8	0.8	0.2	27.6
Visual, GLB	0.7	1.8	8.2	0.8 ms	15.7	0.2	1.8	0.2	28.6
Visual, OBJ	0.8	1.9	8.3	0.8 ms	16.4	8.4	2.6	0.3	38.7

Board	Repo: tomrodinger/servomotor Board: `Coin_Cell_Tester.kicad_pcb`
Folder	PCB / Coin_Cell_Tester / PCB / V2
Complexity	322 / 1000 (size 237, features 85)
KESE features	through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 6 (20211014)
Parts, tracks, vias	193, 1,255, 184
Triangles, simulation	1,916,852 in 102 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	66 MB	687 MB
STEP	349 MB	950 MB
STL	96 MB	717 MB
OBJ	200 MB	1.3 GB
Visual
GLB	53 MB	897 MB
OBJ	162 MB	1.2 GB

2870. servo_motor

servo_motor: stages 4 and 6 take 55% to 82% of a run. Simulation, GLB takes 15 s. Simulation, STEP takes 19 s. Simulation, STL takes 15 s. Simulation, OBJ takes 22 s. Visual, GLB takes 24 s. Visual, OBJ takes 30 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.6	6.4	0.6 ms	5.3	0.2	0.6	0.2	14.9
Simulation, STEP	0.6	1.8	6.8	0.6 ms	5.3	4.2	0.5	0.2	19.4
Simulation, STL	0.5	1.6	6.5	0.8 ms	5.3	0.4	0.6	0.2	15.1
Simulation, OBJ	0.6	1.7	6.7	0.5 ms	5.4	6.7	0.6	0.2	22.0
Visual, GLB	0.6	1.7	7.2	0.7 ms	12.6	0.2	1.5	0.3	24.0
Visual, OBJ	0.6	1.6	6.7	0.5 ms	13.3	5.6	1.9	0.2	29.9

Board	Repo: tomrodinger/servomotor Board: `servo_motor.kicad_pcb`
Folder	PCB / Servomotor1 / V26
Complexity	297 / 1000 (size 187, features 110)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 6 (20211014)
Parts, tracks, vias	99, 812, 233
Triangles, simulation	1,460,928 in 111 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	51 MB	585 MB
STEP	268 MB	734 MB
STL	73 MB	585 MB
OBJ	153 MB	1.0 GB
Visual
GLB	43 MB	783 MB
OBJ	129 MB	934 MB

2871. servo_motor

servo_motor: stages 4 and 6 take 52% to 83% of a run. Simulation, GLB takes 14 s. Simulation, STEP takes 18 s. Simulation, STL takes 14 s. Simulation, OBJ takes 20 s. Visual, GLB takes 20 s. Visual, OBJ takes 26 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.6	5.9	0.4 ms	5.0	0.2	0.5	0.2	14.0
Simulation, STEP	0.5	1.5	5.9	0.4 ms	5.0	4.0	0.5	0.2	17.6
Simulation, STL	0.5	1.6	5.7	0.5 ms	4.9	0.3	0.5	0.2	13.8
Simulation, OBJ	0.5	1.5	5.7	0.5 ms	4.9	7.1	0.5	0.2	20.5
Visual, GLB	0.5	1.5	5.7	0.5 ms	11.4	0.2	1.0	0.2	20.5
Visual, OBJ	0.6	1.4	5.8	0.5 ms	11.4	5.8	1.0	0.2	26.2

Board	Repo: tomrodinger/servomotor Board: `servo_motor.kicad_pcb`
Folder	PCB / Servomotor1 / V27
Complexity	297 / 1000 (size 187, features 110)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	99, 815, 233
Triangles, simulation	1,394,996 in 111 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	49 MB	555 MB
STEP	258 MB	704 MB
STL	70 MB	563 MB
OBJ	147 MB	957 MB
Visual
GLB	42 MB	742 MB
OBJ	126 MB	910 MB

2872. servo_motor

servo_motor: stages 4 and 6 take 54% to 80% of a run. Simulation, GLB takes 11 s. Simulation, STEP takes 14 s. Simulation, STL takes 11 s. Simulation, OBJ takes 16 s. Visual, GLB takes 18 s. Visual, OBJ takes 23 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.2	3.9	0.6 ms	4.2	0.2	0.5	0.2	10.6
Simulation, STEP	0.5	1.2	4.1	0.5 ms	3.9	3.1	0.4	0.3	13.5
Simulation, STL	0.5	1.2	4.1	0.7 ms	4.0	0.4	0.5	0.2	10.8
Simulation, OBJ	0.4	1.2	4.4	0.6 ms	4.3	5.2	0.5	0.2	16.2
Visual, GLB	0.5	1.2	4.3	0.7 ms	10.4	0.2	1.5	0.3	18.4
Visual, OBJ	0.4	1.2	4.3	0.7 ms	10.2	4.8	1.4	0.3	22.7

Board	Repo: tomrodinger/servomotor Board: `servo_motor.kicad_pcb`
Folder	PCB / Servomotor2 / V4
Complexity	306 / 1000 (size 186, features 120)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 6 (20211014)
Parts, tracks, vias	94, 834, 225
Triangles, simulation	1,065,306 in 97 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	38 MB	471 MB
STEP	203 MB	628 MB
STL	53 MB	503 MB
OBJ	110 MB	793 MB
Visual
GLB	33 MB	709 MB
OBJ	99 MB	748 MB

2873. servo_motor

servo_motor: stages 4 and 6 take 55% to 82% of a run. Simulation, GLB takes 10 s. Simulation, STEP takes 13 s. Simulation, STL takes 11 s. Simulation, OBJ takes 16 s. Visual, GLB takes 15 s. Visual, OBJ takes 20 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.0	3.6	0.6 ms	4.5	0.2	0.5	0.2	10.3
Simulation, STEP	0.4	1.0	3.4	0.4 ms	4.8	3.0	0.5	0.2	13.3
Simulation, STL	0.4	1.1	3.5	0.5 ms	4.6	0.3	0.4	0.2	10.7
Simulation, OBJ	0.4	1.0	3.8	0.4 ms	4.8	5.0	0.5	0.3	15.7
Visual, GLB	0.4	1.0	3.5	0.5 ms	8.8	0.1	0.9	0.3	15.1
Visual, OBJ	0.6	1.0	3.6	0.7 ms	8.7	4.5	1.1	0.2	19.8

Board	Repo: tomrodinger/servomotor Board: `servo_motor.kicad_pcb`
Folder	PCB / Servomotor2 / V5
Complexity	285 / 1000 (size 185, features 100)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	92, 834, 215
Triangles, simulation	967,280 in 89 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	34 MB	469 MB
STEP	183 MB	565 MB
STL	48 MB	459 MB
OBJ	99 MB	684 MB
Visual
GLB	30 MB	717 MB
OBJ	91 MB	636 MB

2874. servo_motor-V6

servo_motor-V6: stages 4 and 6 take 51% to 81% of a run. Simulation, GLB takes 9.7 s. Simulation, STEP takes 12 s. Simulation, STL takes 9.1 s. Simulation, OBJ takes 14 s. Visual, GLB takes 14 s. Visual, OBJ takes 18 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.1	3.6	0.8 ms	3.6	0.2	0.6	0.2	9.7
Simulation, STEP	0.5	1.0	3.6	0.4 ms	3.7	2.8	0.5	0.2	12.3
Simulation, STL	0.5	1.0	3.4	0.5 ms	3.4	0.2	0.5	0.2	9.1
Simulation, OBJ	0.5	1.0	3.4	0.4 ms	3.9	4.8	0.5	0.2	14.3
Visual, GLB	0.4	1.0	3.5	0.4 ms	7.6	0.1	0.9	0.2	13.8
Visual, OBJ	0.4	1.0	3.4	0.4 ms	7.6	4.5	1.1	0.2	18.2

Board	Repo: tomrodinger/servomotor Board: `servo_motor-V6.kicad_pcb`
Folder	PCB / Servomotor2 / V6
Complexity	286 / 1000 (size 186, features 100)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	92, 843, 214
Triangles, simulation	894,130 in 89 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	31 MB	436 MB
STEP	161 MB	522 MB
STL	45 MB	417 MB
OBJ	92 MB	637 MB
Visual
GLB	29 MB	626 MB
OBJ	86 MB	633 MB

2875. 1.0

1.0: stages 4 and 6 take 51% to 81% of a run. Simulation, GLB takes 9.4 s. Simulation, STEP takes 12 s. Simulation, STL takes 9.5 s. Simulation, OBJ takes 14 s. Visual, GLB takes 15 s. Visual, OBJ takes 18 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.0	3.6	0.4 ms	3.6	0.1	0.5	0.2	9.4
Simulation, STEP	0.4	1.0	3.7	0.3 ms	3.6	2.5	0.5	0.2	11.9
Simulation, STL	0.4	1.0	3.6	0.3 ms	3.5	0.3	0.5	0.2	9.5
Simulation, OBJ	0.4	1.0	3.6	0.6 ms	3.4	4.7	0.5	0.3	13.9
Visual, GLB	0.4	1.0	3.7	0.3 ms	8.4	0.1	1.0	0.3	14.8
Visual, OBJ	0.4	1.1	3.5	0.4 ms	8.0	4.2	1.0	0.2	18.4

Board	Repo: tomrodinger/servomotor Board: `1.0.kicad_pcb`
Folder	PCB / Servomotor3 / 1.0
Complexity	346 / 1000 (size 221, features 125)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, copper finish
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	66, 584, 261
Triangles, simulation	930,390 in 65 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	32 MB	416 MB
STEP	146 MB	518 MB
STL	47 MB	434 MB
OBJ	94 MB	656 MB
Visual
GLB	27 MB	666 MB
OBJ	81 MB	618 MB

2876. 1.2

1.2: stages 4 and 6 take 48% to 82% of a run. Simulation, GLB takes 11 s. Simulation, STEP takes 14 s. Simulation, STL takes 11 s. Simulation, OBJ takes 17 s. Visual, GLB takes 19 s. Visual, OBJ takes 22 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.3	4.5	0.4 ms	3.8	0.2	0.7	0.3	11.2
Simulation, STEP	0.5	1.2	4.4	0.4 ms	3.7	2.8	0.7	0.3	13.6
Simulation, STL	0.5	1.3	4.4	0.6 ms	3.7	0.3	0.7	0.2	11.1
Simulation, OBJ	0.6	1.2	4.4	0.4 ms	3.7	6.0	0.7	0.2	16.7
Visual, GLB	0.4	1.3	4.6	0.4 ms	10.9	0.1	1.3	0.2	18.9
Visual, OBJ	0.5	1.3	4.3	0.4 ms	10.0	4.8	1.3	0.3	22.4

Board	Repo: tomrodinger/servomotor Board: `1.2.kicad_pcb`
Folder	PCB / Servomotor3 / 1.2
Complexity	348 / 1000 (size 223, features 125)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, copper finish
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	74, 542, 308
Triangles, simulation	975,320 in 65 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	33 MB	487 MB
STEP	148 MB	558 MB
STL	49 MB	504 MB
OBJ	99 MB	696 MB
Visual
GLB	28 MB	665 MB
OBJ	84 MB	673 MB

2877. 1.3

1.3: stages 4 and 6 take 52% to 83% of a run. Simulation, GLB takes 9.8 s. Simulation, STEP takes 12 s. Simulation, STL takes 9.3 s. Simulation, OBJ takes 14 s. Visual, GLB takes 15 s. Visual, OBJ takes 19 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.0	3.8	0.4 ms	3.5	0.2	0.5	0.3	9.8
Simulation, STEP	0.4	1.1	3.8	0.5 ms	3.4	2.5	0.5	0.2	12.0
Simulation, STL	0.4	1.1	3.5	0.4 ms	3.2	0.3	0.5	0.2	9.3
Simulation, OBJ	0.4	0.9	3.9	0.2 ms	3.5	4.6	0.6	0.2	14.1
Visual, GLB	0.4	0.9	3.6	0.4 ms	9.0	0.1	1.0	0.2	15.3
Visual, OBJ	0.5	1.0	3.7	0.6 ms	9.2	3.3	1.3	0.3	19.3

Board	Repo: tomrodinger/servomotor Board: `1.3.kicad_pcb`
Folder	PCB / Servomotor3 / 1.3
Complexity	348 / 1000 (size 223, features 125)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, copper finish
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	75, 544, 308
Triangles, simulation	956,536 in 65 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	33 MB	488 MB
STEP	142 MB	549 MB
STL	48 MB	493 MB
OBJ	97 MB	681 MB
Visual
GLB	28 MB	653 MB
OBJ	83 MB	663 MB

2878. 1.5

1.5: stages 4 and 6 take 50% to 82% of a run. Simulation, GLB takes 11 s. Simulation, STEP takes 14 s. Simulation, STL takes 11 s. Simulation, OBJ takes 17 s. Visual, GLB takes 18 s. Visual, OBJ takes 23 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	1.4	4.5	0.4 ms	3.9	0.2	0.6	0.2	11.4
Simulation, STEP	0.6	1.4	4.5	0.4 ms	3.9	2.5	0.6	0.2	13.6
Simulation, STL	0.6	1.2	4.6	0.5 ms	3.9	0.3	0.6	0.2	11.4
Simulation, OBJ	0.5	1.2	4.5	0.4 ms	3.8	5.7	0.6	0.2	16.5
Visual, GLB	0.5	1.2	4.4	0.4 ms	10.5	0.2	1.0	0.2	18.0
Visual, OBJ	0.6	1.2	4.6	0.4 ms	10.1	5.5	1.1	0.2	23.4

Board	Repo: tomrodinger/servomotor Board: `1.5.kicad_pcb`
Folder	PCB / Servomotor3 / 1.5
Complexity	349 / 1000 (size 224, features 125)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, copper finish
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	75, 550, 330
Triangles, simulation	1,145,496 in 65 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	40 MB	630 MB
STEP	142 MB	656 MB
STL	57 MB	662 MB
OBJ	117 MB	824 MB
Visual
GLB	34 MB	704 MB
OBJ	103 MB	749 MB

2879. V10

V10: stages 4 and 6 take 49% to 82% of a run. Simulation, GLB takes 7.7 s. Simulation, STEP takes 10 s. Simulation, STL takes 8.2 s. Simulation, OBJ takes 12 s. Visual, GLB takes 12 s. Visual, OBJ takes 16 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.9	2.9	0.3 ms	2.8	0.1	0.5	0.2	7.7
Simulation, STEP	0.3	0.8	3.0	0.3 ms	2.8	2.4	0.4	0.2	10.0
Simulation, STL	0.3	0.9	3.0	0.3 ms	3.1	0.2	0.4	0.2	8.2
Simulation, OBJ	0.4	0.8	3.0	0.3 ms	2.9	4.2	0.4	0.2	11.9
Visual, GLB	0.4	0.8	3.0	0.3 ms	7.0	92 ms	0.7	0.2	12.1
Visual, OBJ	0.3	0.8	3.1	0.4 ms	6.8	3.7	0.8	0.2	15.8

Board	Repo: tomrodinger/servomotor Board: `V10.kicad_pcb`
Folder	PCB / Servomotor3 / V10
Complexity	344 / 1000 (size 219, features 125)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, copper finish
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	64, 576, 226
Triangles, simulation	822,874 in 60 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	28 MB	394 MB
STEP	129 MB	506 MB
STL	41 MB	407 MB
OBJ	83 MB	582 MB
Visual
GLB	24 MB	600 MB
OBJ	72 MB	601 MB

2880. V11

V11: stages 4 and 6 take 52% to 82% of a run. Simulation, GLB takes 9.8 s. Simulation, STEP takes 12 s. Simulation, STL takes 9.8 s. Simulation, OBJ takes 14 s. Visual, GLB takes 15 s. Visual, OBJ takes 19 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.0	3.9	0.4 ms	3.5	0.2	0.6	0.2	9.8
Simulation, STEP	0.4	1.1	4.0	0.3 ms	3.7	2.6	0.5	0.2	12.5
Simulation, STL	0.4	1.0	3.7	0.4 ms	3.5	0.3	0.5	0.2	9.8
Simulation, OBJ	0.4	1.0	3.8	0.4 ms	3.6	4.8	0.5	0.2	14.4
Visual, GLB	0.4	1.1	4.0	0.3 ms	8.4	0.1	0.8	0.2	15.0
Visual, OBJ	0.5	1.1	3.8	0.4 ms	8.3	4.4	1.0	0.2	19.3

Board	Repo: tomrodinger/servomotor Board: `V11.kicad_pcb`
Folder	PCB / Servomotor3 / V11
Complexity	346 / 1000 (size 221, features 125)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, copper finish
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	66, 584, 261
Triangles, simulation	930,538 in 65 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	32 MB	424 MB
STEP	146 MB	532 MB
STL	47 MB	432 MB
OBJ	94 MB	655 MB
Visual
GLB	27 MB	563 MB
OBJ	81 MB	639 MB

2881. V11

V11: stages 4 and 6 take 51% to 82% of a run. Simulation, GLB takes 8.4 s. Simulation, STEP takes 11 s. Simulation, STL takes 8.4 s. Simulation, OBJ takes 12 s. Visual, GLB takes 12 s. Visual, OBJ takes 16 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.9	3.4	0.4 ms	3.0	0.1	0.5	0.2	8.4
Simulation, STEP	0.3	0.9	3.3	0.3 ms	3.1	2.3	0.5	0.2	10.7
Simulation, STL	0.3	0.9	3.2	0.5 ms	3.1	0.2	0.4	0.2	8.4
Simulation, OBJ	0.3	0.9	3.2	0.3 ms	3.0	4.1	0.5	0.2	12.3
Visual, GLB	0.3	0.9	3.3	0.3 ms	7.0	0.1	0.6	0.2	12.4
Visual, OBJ	0.3	0.9	3.3	0.3 ms	6.7	3.5	0.6	0.2	15.5

Board	Repo: tomrodinger/servomotor Board: `V11.kicad_pcb`
Folder	PCB / Servomotor3 / V11RC1
Complexity	345 / 1000 (size 220, features 125)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, copper finish
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	64, 531, 270
Triangles, simulation	876,820 in 60 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	30 MB	412 MB
STEP	133 MB	495 MB
STL	44 MB	414 MB
OBJ	89 MB	582 MB
Visual
GLB	25 MB	545 MB
OBJ	76 MB	622 MB

2882. V11RC2

V11RC2: stages 4 and 6 take 51% to 80% of a run. Simulation, GLB takes 8.6 s. Simulation, STEP takes 11 s. Simulation, STL takes 9.2 s. Simulation, OBJ takes 13 s. Visual, GLB takes 13 s. Visual, OBJ takes 17 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.0	3.1	0.5 ms	3.4	0.2	0.4	0.2	8.6
Simulation, STEP	0.3	0.9	3.1	0.4 ms	3.3	2.4	0.4	0.3	10.8
Simulation, STL	0.4	0.9	3.6	0.5 ms	3.4	0.2	0.5	0.2	9.2
Simulation, OBJ	0.3	0.8	3.1	0.6 ms	3.4	4.2	0.5	0.3	12.8
Visual, GLB	0.3	0.9	3.2	1 ms	7.6	0.1	1.0	0.3	13.3
Visual, OBJ	0.3	0.9	3.2	0.4 ms	7.7	3.6	1.0	0.2	17.0

Board	Repo: tomrodinger/servomotor Board: `V11RC2.kicad_pcb`
Folder	PCB / Servomotor3 / V11RC2
Complexity	344 / 1000 (size 219, features 125)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, copper finish
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	63, 521, 267
Triangles, simulation	889,910 in 60 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	31 MB	410 MB
STEP	136 MB	520 MB
STL	45 MB	423 MB
OBJ	90 MB	626 MB
Visual
GLB	26 MB	612 MB
OBJ	77 MB	606 MB

2883. V11RC3

V11RC3: stages 4 and 6 take 53% to 81% of a run. Simulation, GLB takes 9.9 s. Simulation, STEP takes 12 s. Simulation, STL takes 10 s. Simulation, OBJ takes 14 s. Visual, GLB takes 15 s. Visual, OBJ takes 19 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.0	3.9	0.7 ms	3.6	0.2	0.5	0.2	9.9
Simulation, STEP	0.3	1.1	3.5	0.3 ms	3.7	2.7	0.6	0.3	12.2
Simulation, STL	0.4	1.0	4.1	0.4 ms	3.6	0.3	0.6	0.3	10.3
Simulation, OBJ	0.3	1.0	3.7	0.3 ms	3.5	4.4	0.6	0.2	13.7
Visual, GLB	0.4	0.9	3.8	0.4 ms	8.4	0.1	1.2	0.3	15.0
Visual, OBJ	0.4	1.0	3.9	0.4 ms	8.4	3.8	1.3	0.2	19.1

Board	Repo: tomrodinger/servomotor Board: `V11RC3.kicad_pcb`
Folder	PCB / Servomotor3 / V11RC3
Complexity	345 / 1000 (size 220, features 125)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, copper finish
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	64, 525, 264
Triangles, simulation	875,720 in 61 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	30 MB	406 MB
STEP	134 MB	492 MB
STL	44 MB	402 MB
OBJ	89 MB	614 MB
Visual
GLB	25 MB	590 MB
OBJ	76 MB	608 MB

2884. V11RC4

V11RC4: stages 4 and 6 take 52% to 80% of a run. Simulation, GLB takes 8.8 s. Simulation, STEP takes 12 s. Simulation, STL takes 9.6 s. Simulation, OBJ takes 13 s. Visual, GLB takes 14 s. Visual, OBJ takes 18 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.9	3.4	0.6 ms	3.3	0.1	0.5	0.3	8.8
Simulation, STEP	0.3	0.9	3.7	0.4 ms	3.5	2.6	0.4	0.2	11.7
Simulation, STL	0.3	1.0	3.7	0.5 ms	3.6	0.3	0.5	0.2	9.6
Simulation, OBJ	0.3	0.9	3.3	0.7 ms	3.5	4.2	0.5	0.2	12.9
Visual, GLB	0.3	0.9	3.3	0.5 ms	7.7	0.1	1.1	0.3	13.7
Visual, OBJ	0.3	0.9	3.3	0.7 ms	8.1	3.9	1.2	0.3	18.0

Board	Repo: tomrodinger/servomotor Board: `V11RC4.kicad_pcb`
Folder	PCB / Servomotor3 / V11RC4
Complexity	346 / 1000 (size 221, features 125)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, copper finish
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	66, 584, 261
Triangles, simulation	899,412 in 65 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	31 MB	404 MB
STEP	140 MB	529 MB
STL	45 MB	419 MB
OBJ	91 MB	630 MB
Visual
GLB	26 MB	564 MB
OBJ	78 MB	634 MB

2885. servomotorStepper-V2I1

servomotorStepper-V2I1: stages 4 and 6 take 50% to 82% of a run. Simulation, GLB takes 8.2 s. Simulation, STEP takes 11 s. Simulation, STL takes 8.1 s. Simulation, OBJ takes 13 s. Visual, GLB takes 12 s. Visual, OBJ takes 15 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	0.7	2.7	0.3 ms	3.7	0.1	0.5	0.2	8.2
Simulation, STEP	0.3	0.7	2.6	0.3 ms	3.5	2.9	0.5	0.2	10.7
Simulation, STL	0.3	0.7	2.6	0.3 ms	3.7	0.2	0.4	0.2	8.1
Simulation, OBJ	0.3	0.8	2.7	0.3 ms	3.6	4.5	0.5	0.2	12.6
Visual, GLB	0.3	0.7	2.5	0.3 ms	7.2	0.1	0.8	0.2	11.9
Visual, OBJ	0.3	0.7	2.6	0.3 ms	7.4	3.4	0.9	0.2	15.4

Board	Repo: tomrodinger/servomotor Board: `servomotorStepper-V2I1.kicad_pcb`
Folder	PCB / Servomotor3 / V2
Complexity	346 / 1000 (size 221, features 125)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, copper finish
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	65, 973, 144
Triangles, simulation	792,126 in 62 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	28 MB	433 MB
STEP	147 MB	497 MB
STL	40 MB	418 MB
OBJ	81 MB	573 MB
Visual
GLB	23 MB	591 MB
OBJ	70 MB	601 MB

2886. M3-V4

M3-V4: stages 4 and 6 take 51% to 81% of a run. Simulation, GLB takes 8.9 s. Simulation, STEP takes 12 s. Simulation, STL takes 9.4 s. Simulation, OBJ takes 13 s. Visual, GLB takes 13 s. Visual, OBJ takes 16 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	0.8	3.0	0.2 ms	3.8	0.1	0.5	0.2	8.9
Simulation, STEP	0.4	0.8	2.9	0.2 ms	3.8	3.0	0.4	0.2	11.5
Simulation, STL	0.4	0.9	3.2	0.2 ms	3.8	0.2	0.5	0.3	9.4
Simulation, OBJ	0.4	0.9	3.0	0.4 ms	3.8	4.6	0.5	0.2	13.3
Visual, GLB	0.4	0.8	2.9	0.3 ms	7.4	0.1	0.8	0.2	12.7
Visual, OBJ	0.4	0.9	2.9	0.3 ms	7.2	4.0	0.8	0.2	16.2

Board	Repo: tomrodinger/servomotor Board: `M3-V4.kicad_pcb`
Folder	PCB / Servomotor3 / V4
Complexity	347 / 1000 (size 222, features 125)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, copper finish
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	65, 1,027, 159
Triangles, simulation	872,928 in 62 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	30 MB	462 MB
STEP	158 MB	528 MB
STL	44 MB	451 MB
OBJ	89 MB	620 MB
Visual
GLB	27 MB	654 MB
OBJ	80 MB	641 MB

2887. M3-V5

M3-V5: stages 4 and 6 take 52% to 79% of a run. Simulation, GLB takes 7.6 s. Simulation, STEP takes 9.7 s. Simulation, STL takes 7.4 s. Simulation, OBJ takes 11 s. Visual, GLB takes 11 s. Visual, OBJ takes 15 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.7	2.5	0.3 ms	3.3	0.1	0.5	0.2	7.6
Simulation, STEP	0.3	0.7	2.4	0.5 ms	3.3	2.4	0.4	0.2	9.7
Simulation, STL	0.3	0.8	2.4	0.3 ms	3.2	0.2	0.4	0.2	7.4
Simulation, OBJ	0.3	0.7	2.4	0.4 ms	3.1	3.6	0.4	0.2	10.6
Visual, GLB	0.3	0.7	2.4	0.2 ms	6.7	0.1	1.2	0.2	11.5
Visual, OBJ	0.3	0.7	2.5	0.5 ms	7.0	3.0	1.0	0.2	14.7

Board	Repo: tomrodinger/servomotor Board: `M3-V5.kicad_pcb`
Folder	PCB / Servomotor3 / V5
Complexity	347 / 1000 (size 222, features 125)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, copper finish
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	65, 1,035, 165
Triangles, simulation	886,776 in 62 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	31 MB	461 MB
STEP	162 MB	504 MB
STL	44 MB	457 MB
OBJ	90 MB	626 MB
Visual
GLB	27 MB	660 MB
OBJ	82 MB	673 MB

2888. V8

V8: stages 4 and 6 take 52% to 81% of a run. Simulation, GLB takes 7.9 s. Simulation, STEP takes 11 s. Simulation, STL takes 8.0 s. Simulation, OBJ takes 12 s. Visual, GLB takes 12 s. Visual, OBJ takes 15 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.8	3.0	0.3 ms	3.0	0.1	0.4	0.2	7.9
Simulation, STEP	0.3	0.9	3.1	0.3 ms	3.2	2.4	0.4	0.2	10.6
Simulation, STL	0.3	0.9	3.0	0.3 ms	2.9	0.2	0.4	0.3	8.0
Simulation, OBJ	0.3	0.9	3.1	0.3 ms	3.1	4.0	0.4	0.2	11.9
Visual, GLB	0.3	0.9	3.1	0.3 ms	6.6	0.1	0.7	0.2	11.9
Visual, OBJ	0.3	0.9	3.0	0.3 ms	6.4	3.6	0.6	0.2	15.1

Board	Repo: tomrodinger/servomotor Board: `V8.kicad_pcb`
Folder	PCB / Servomotor3 / V8
Complexity	342 / 1000 (size 217, features 125)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, copper finish
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	64, 514, 214
Triangles, simulation	796,890 in 61 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	27 MB	389 MB
STEP	125 MB	471 MB
STL	40 MB	395 MB
OBJ	81 MB	572 MB
Visual
GLB	23 MB	534 MB
OBJ	70 MB	579 MB

2889. V9

V9: stages 4 and 6 take 53% to 81% of a run. Simulation, GLB takes 8.3 s. Simulation, STEP takes 11 s. Simulation, STL takes 8.5 s. Simulation, OBJ takes 12 s. Visual, GLB takes 14 s. Visual, OBJ takes 17 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.9	3.1	0.4 ms	3.1	0.2	0.5	0.2	8.3
Simulation, STEP	0.3	0.9	3.1	0.5 ms	3.3	2.6	0.5	0.2	10.9
Simulation, STL	0.3	0.8	3.0	0.4 ms	3.2	0.3	0.5	0.2	8.5
Simulation, OBJ	0.3	0.9	3.0	0.3 ms	3.2	3.6	0.4	0.2	11.6
Visual, GLB	0.3	0.9	3.2	0.4 ms	7.8	0.1	1.1	0.2	13.8
Visual, OBJ	0.3	0.9	3.0	0.3 ms	8.0	3.4	1.1	0.2	17.0

Board	Repo: tomrodinger/servomotor Board: `V9.kicad_pcb`
Folder	PCB / Servomotor3 / V9
Complexity	344 / 1000 (size 219, features 125)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, copper finish
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	64, 569, 225
Triangles, simulation	817,250 in 60 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	28 MB	405 MB
STEP	128 MB	500 MB
STL	41 MB	397 MB
OBJ	83 MB	615 MB
Visual
GLB	24 MB	538 MB
OBJ	72 MB	572 MB

2890. pocket-reform-keyboard

pocket-reform-keyboard: stages 4 and 6 take 54% to 84% of a run. Simulation, GLB takes 23 s. Simulation, STEP takes 30 s. Simulation, STL takes 23 s. Simulation, OBJ takes 33 s. Visual, GLB takes 37 s. Visual, OBJ takes 47 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	1.8	10.1	1 ms	8.2	0.4	1.0	0.3	22.6
Simulation, STEP	0.6	1.9	10.1	0.3 ms	8.9	6.7	1.0	0.3	29.6
Simulation, STL	0.6	1.9	9.8	0.8 ms	9.0	0.8	1.0	0.3	23.3
Simulation, OBJ	0.6	1.7	9.7	0.8 ms	8.4	11.8	0.9	0.3	33.4
Visual, GLB	0.6	1.9	9.8	0.6 ms	21.1	0.3	2.7	0.2	36.7
Visual, OBJ	0.6	1.8	9.7	0.8 ms	22.1	9.6	3.2	0.2	47.1

Board	Repo: torlye/pocket-reform Board: `pocket-reform-keyboard.kicad_pcb`
Folder	attic / pocket-reform-keyboard
Complexity	270 / 1000 (size 225, features 45)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones
Tested	9th November 2026
Copper layers	2
File format	KiCad 5 (20171130)
Parts, tracks, vias	137, 802, 110
Triangles, simulation	2,474,030 in 109 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	83 MB	1.0 GB
STEP	345 MB	1.1 GB
STL	124 MB	921 MB
OBJ	256 MB	1.6 GB
Visual
GLB	64 MB	1.1 GB
OBJ	197 MB	1.3 GB

2891. pref-display-back-d5-gold

pref-display-back-d5-gold: stages 4 and 6 take 32% to 48% of a run. Simulation, GLB takes 0.5 s. Simulation, STEP takes 0.6 s. Simulation, STL takes 0.5 s. Simulation, OBJ takes 0.6 s. Visual, GLB takes 0.6 s. Visual, OBJ takes 0.6 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	13 ms	26 ms	51 ms	0.1 ms	0.2	4 ms	25 ms	0.2	0.5
Simulation, STEP	13 ms	23 ms	52 ms	0.1 ms	0.1	0.1	24 ms	0.2	0.6
Simulation, STL	19 ms	32 ms	65 ms	0.1 ms	0.2	7 ms	25 ms	0.2	0.5
Simulation, OBJ	16 ms	26 ms	65 ms	0.1 ms	0.2	0.1	21 ms	0.2	0.6
Visual, GLB	14 ms	27 ms	65 ms	0.1 ms	0.2	5 ms	56 ms	0.2	0.6
Visual, OBJ	13 ms	26 ms	56 ms	0.1 ms	0.2	54 ms	42 ms	0.2	0.6

Board	Repo: torlye/pocket-reform Board: `pref-display-back-d5-gold.kicad_pcb`
Folder	case-plate-pcbs
Complexity	37 / 1000 (size 17, features 20)
KESE features	filled zones
Tested	9th November 2026
Copper layers	2
File format	KiCad 6 (20211014)
Parts, tracks, vias	0, 0, 0
Triangles, simulation	24,692 in 7 parts
Note	no components
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	852 kB	44 MB
STEP	4.2 MB	48 MB
STL	1.2 MB	44 MB
OBJ	2.3 MB	49 MB
Visual
GLB	464 kB	78 MB
OBJ	1.2 MB	69 MB

2892. pref-display-back-d5

Reading, start-up and exit take 41% to 60% of a run. Simulation, GLB takes 0.4 s. Simulation, STEP takes 0.5 s. Simulation, STL takes 0.4 s. Simulation, OBJ takes 0.4 s. Visual, GLB takes 0.4 s. Visual, OBJ takes 0.4 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	13 ms	21 ms	36 ms	0.1 ms	72 ms	3 ms	17 ms	0.2	0.4
Simulation, STEP	9 ms	23 ms	34 ms	0.1 ms	84 ms	89 ms	15 ms	0.2	0.5
Simulation, STL	13 ms	22 ms	39 ms	0.1 ms	83 ms	3 ms	16 ms	0.2	0.4
Simulation, OBJ	9 ms	21 ms	37 ms	0.0 ms	76 ms	53 ms	18 ms	0.2	0.4
Visual, GLB	14 ms	32 ms	45 ms	0.1 ms	0.1	2 ms	34 ms	0.2	0.4
Visual, OBJ	9 ms	24 ms	52 ms	0.1 ms	99 ms	26 ms	47 ms	0.2	0.4

Board	Repo: torlye/pocket-reform Board: `pref-display-back-d5.kicad_pcb`
Folder	case-plate-pcbs
Complexity	47 / 1000 (size 17, features 30)
KESE features	filled zones, copper drawings
Tested	9th November 2026
Copper layers	2
File format	KiCad 6 (20211014)
Parts, tracks, vias	0, 0, 0
Triangles, simulation	12,644 in 6 parts
Note	no components
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	452 kB	41 MB
STEP	2.2 MB	44 MB
STL	633 kB	41 MB
OBJ	1.2 MB	43 MB
Visual
GLB	211 kB	57 MB
OBJ	540 kB	67 MB

2893. pref-display-back-d7-gold

Reading, start-up and exit take 41% to 56% of a run. Simulation, GLB takes 0.4 s. Simulation, STEP takes 0.4 s. Simulation, STL takes 0.4 s. Simulation, OBJ takes 0.4 s. Visual, GLB takes 0.5 s. Visual, OBJ takes 0.5 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	11 ms	27 ms	38 ms	0.1 ms	93 ms	3 ms	9 ms	0.2	0.4
Simulation, STEP	11 ms	25 ms	45 ms	0.1 ms	79 ms	89 ms	10 ms	0.2	0.4
Simulation, STL	9 ms	27 ms	41 ms	0.1 ms	80 ms	5 ms	11 ms	0.2	0.4
Simulation, OBJ	11 ms	27 ms	36 ms	0.1 ms	85 ms	45 ms	10 ms	0.2	0.4
Visual, GLB	11 ms	26 ms	39 ms	0.1 ms	0.2	3 ms	31 ms	0.2	0.5
Visual, OBJ	12 ms	27 ms	38 ms	0.1 ms	0.2	38 ms	36 ms	0.2	0.5

Board	Repo: torlye/pocket-reform Board: `pref-display-back-d7-gold.kicad_pcb`
Folder	case-plate-pcbs
Complexity	82 / 1000 (size 17, features 65)
KESE features	filled zones, copper drawings, stack-up, dielectric εr and tanδ, mask and silkscreen colours
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	0, 0, 0
Triangles, simulation	12,548 in 9 parts
Note	no components
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	434 kB	41 MB
STEP	1.2 MB	43 MB
STL	628 kB	41 MB
OBJ	1.1 MB	43 MB
Visual
GLB	284 kB	57 MB
OBJ	733 kB	60 MB

2894. pref-display-front-d7

pref-display-front-d7: stages 4 and 6 take 30% to 43% of a run. Simulation, GLB takes 0.6 s. Simulation, STEP takes 0.7 s. Simulation, STL takes 0.6 s. Simulation, OBJ takes 0.7 s. Visual, GLB takes 0.6 s. Visual, OBJ takes 0.7 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	25 ms	0.1	6 ms	0.1 ms	0.2	6 ms	4 ms	0.2	0.6
Simulation, STEP	22 ms	0.1	5 ms	0.1 ms	0.2	0.1	4 ms	0.2	0.7
Simulation, STL	30 ms	0.1	6 ms	0.1 ms	0.2	9 ms	4 ms	0.2	0.6
Simulation, OBJ	23 ms	96 ms	6 ms	0.0 ms	0.2	0.2	5 ms	0.2	0.7
Visual, GLB	25 ms	0.1	9 ms	0.1 ms	0.2	4 ms	26 ms	0.2	0.6
Visual, OBJ	22 ms	0.1	5 ms	0.0 ms	0.2	0.1	31 ms	0.2	0.7

Board	Repo: torlye/pocket-reform Board: `pref-display-front-d7.kicad_pcb`
Folder	case-plate-pcbs
Complexity	27 / 1000 (size 17, features 10)
KESE features	curved board outline
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	0, 0, 0
Triangles, simulation	34,200 in 3 parts
Note	no components
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	939 kB	48 MB
STEP	1.6 MB	49 MB
STL	1.7 MB	48 MB
OBJ	3.4 MB	54 MB
Visual
GLB	889 kB	60 MB
OBJ	2.4 MB	53 MB

2895. pref-display-front

pref-display-front: stages 4 and 6 take 30% to 44% of a run. Simulation, GLB takes 0.5 s. Simulation, STEP takes 0.8 s. Simulation, STL takes 0.6 s. Simulation, OBJ takes 0.7 s. Visual, GLB takes 0.6 s. Visual, OBJ takes 0.7 s

Mode and format	1–2 read	3 resolve	4 geometry	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	22 ms	0.1	4 ms	0.2	5 ms	3 ms	0.2	0.5
Simulation, STEP	36 ms	0.1	4 ms	0.2	0.2	3 ms	0.2	0.8
Simulation, STL	22 ms	0.1	5 ms	0.2	7 ms	3 ms	0.2	0.6
Simulation, OBJ	24 ms	0.1	5 ms	0.2	0.2	3 ms	0.2	0.7
Visual, GLB	21 ms	0.1	5 ms	0.2	4 ms	27 ms	0.2	0.6
Visual, OBJ	23 ms	0.1	4 ms	0.2	0.1	28 ms	0.2	0.7

Board	Repo: torlye/pocket-reform Board: `pref-display-front.kicad_pcb`
Folder	case-plate-pcbs
Complexity	27 / 1000 (size 17, features 10)
KESE features	curved board outline
Tested	9th November 2026
Copper layers	2
File format	KiCad 6 (20211014)
Parts, tracks, vias	0, 0, 0
Triangles, simulation	34,168 in 3 parts
Note	no components
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	938 kB	48 MB
STEP	1.6 MB	49 MB
STL	1.7 MB	48 MB
OBJ	3.4 MB	56 MB
Visual
GLB	888 kB	57 MB
OBJ	2.4 MB	56 MB

2896. pref-keyboard-back-d1-fr4

Reading, start-up and exit take 35% to 57% of a run. Simulation, GLB takes 0.4 s. Simulation, STEP takes 0.6 s. Simulation, STL takes 0.5 s. Simulation, OBJ takes 0.5 s. Visual, GLB takes 0.5 s. Visual, OBJ takes 0.5 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	15 ms	37 ms	23 ms	0.0 ms	0.1	5 ms	11 ms	0.2	0.4
Simulation, STEP	22 ms	31 ms	25 ms	0.1 ms	0.1	0.1	10 ms	0.2	0.6
Simulation, STL	22 ms	37 ms	22 ms	0.1 ms	0.1	4 ms	10 ms	0.2	0.5
Simulation, OBJ	15 ms	30 ms	26 ms	0.1 ms	0.1	0.1	10 ms	0.2	0.5
Visual, GLB	13 ms	31 ms	18 ms	0.1 ms	0.1	3 ms	47 ms	0.2	0.5
Visual, OBJ	19 ms	30 ms	22 ms	0.1 ms	0.1	53 ms	47 ms	0.2	0.5

Board	Repo: torlye/pocket-reform Board: `pref-keyboard-back-d1-fr4.kicad_pcb`
Folder	case-plate-pcbs
Complexity	37 / 1000 (size 17, features 20)
KESE features	filled zones
Tested	9th November 2026
Copper layers	2
File format	KiCad 6 (20211014)
Parts, tracks, vias	0, 0, 0
Triangles, simulation	18,916 in 4 parts
Note	no components
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	637 kB	44 MB
STEP	2.2 MB	45 MB
STL	946 kB	43 MB
OBJ	1.7 MB	47 MB
Visual
GLB	391 kB	63 MB
OBJ	1.0 MB	65 MB

2897. pref-keyboard-bezel-d6

Reading, start-up and exit take 40% to 51% of a run. Simulation, GLB takes 0.4 s. Simulation, STEP takes 0.6 s. Simulation, STL takes 0.4 s. Simulation, OBJ takes 0.5 s. Visual, GLB takes 0.5 s. Visual, OBJ takes 0.6 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	14 ms	43 ms	4 ms	0.0 ms	0.2	3 ms	4 ms	0.2	0.4
Simulation, STEP	14 ms	41 ms	5 ms	0.0 ms	0.2	0.1	2 ms	0.2	0.6
Simulation, STL	18 ms	44 ms	5 ms	0.0 ms	0.2	6 ms	3 ms	0.2	0.4
Simulation, OBJ	14 ms	39 ms	4 ms	0.0 ms	0.1	0.1	3 ms	0.2	0.5
Visual, GLB	14 ms	41 ms	5 ms	0.1 ms	0.2	5 ms	36 ms	0.2	0.5
Visual, OBJ	15 ms	42 ms	5 ms	0.0 ms	0.2	98 ms	32 ms	0.2	0.6

Board	Repo: torlye/pocket-reform Board: `pref-keyboard-bezel-d6.kicad_pcb`
Folder	case-plate-pcbs
Complexity	57 / 1000 (size 17, features 40)
KESE features	curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	0, 0, 0
Triangles, simulation	17,896 in 3 parts
Note	no components
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	485 kB	42 MB
STEP	3.1 MB	45 MB
STL	895 kB	42 MB
OBJ	1.7 MB	45 MB
Visual
GLB	628 kB	57 MB
OBJ	1.7 MB	50 MB

2898. pref-keyboard-bezel

Reading, start-up and exit take 42% to 59% of a run. Simulation, GLB takes 0.4 s. Simulation, STEP takes 0.4 s. Simulation, STL takes 0.3 s. Simulation, OBJ takes 0.4 s. Visual, GLB takes 0.4 s. Visual, OBJ takes 0.5 s

Mode and format	1–2 read	3 resolve	4 geometry	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	24 ms	42 ms	4 ms	0.1	3 ms	2 ms	0.2	0.4
Simulation, STEP	19 ms	46 ms	3 ms	0.1	81 ms	2 ms	0.2	0.4
Simulation, STL	19 ms	34 ms	3 ms	97 ms	4 ms	2 ms	0.2	0.3
Simulation, OBJ	19 ms	38 ms	4 ms	97 ms	64 ms	2 ms	0.2	0.4
Visual, GLB	21 ms	35 ms	3 ms	0.1	3 ms	25 ms	0.2	0.4
Visual, OBJ	20 ms	34 ms	4 ms	0.1	62 ms	24 ms	0.2	0.5

Board	Repo: torlye/pocket-reform Board: `pref-keyboard-bezel.kicad_pcb`
Folder	case-plate-pcbs
Complexity	17 / 1000 (size 17, features 0)
Tested	9th November 2026
Copper layers	2
File format	KiCad 6 (20211014)
Parts, tracks, vias	0, 0, 0
Triangles, simulation	13,452 in 3 parts
Note	no components
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	370 kB	41 MB
STEP	2.0 MB	43 MB
STL	673 kB	42 MB
OBJ	1.3 MB	43 MB
Visual
GLB	470 kB	48 MB
OBJ	1.2 MB	49 MB

2899. pref-side-panel-empty

Reading, start-up and exit take 70% to 82% of a run. Simulation, GLB takes 0.3 s. Simulation, STEP takes 0.4 s. Simulation, STL takes 0.3 s. Simulation, OBJ takes 0.3 s. Visual, GLB takes 0.4 s. Visual, OBJ takes 0.4 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	67 ms	17 ms	13 ms	0.0 ms	22 ms	2 ms	3 ms	0.2	0.3
Simulation, STEP	75 ms	17 ms	13 ms	0.0 ms	20 ms	32 ms	3 ms	0.2	0.4
Simulation, STL	64 ms	18 ms	13 ms	0.0 ms	20 ms	2 ms	3 ms	0.2	0.3
Simulation, OBJ	64 ms	19 ms	14 ms	0.1 ms	22 ms	16 ms	3 ms	0.2	0.3
Visual, GLB	64 ms	17 ms	12 ms	0.1 ms	55 ms	2 ms	16 ms	0.2	0.4
Visual, OBJ	66 ms	19 ms	14 ms	0.0 ms	47 ms	15 ms	16 ms	0.2	0.4

Board	Repo: torlye/pocket-reform Board: `pref-side-panel-empty.kicad_pcb`
Folder	case-plate-pcbs
Complexity	17 / 1000 (size 17, features 0)
Tested	9th November 2026
Copper layers	2
File format	KiCad 6 (20211014)
Parts, tracks, vias	0, 0, 0
Triangles, simulation	2,732 in 4 parts
Note	panel, no components
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	98 kB	61 MB
STEP	225 kB	58 MB
STL	137 kB	57 MB
OBJ	261 kB	58 MB
Visual
GLB	96 kB	69 MB
OBJ	234 kB	69 MB

2900. pref-side-panel-headphones-d8

Reading, start-up and exit take 57% to 69% of a run. Simulation, GLB takes 0.2 s. Simulation, STEP takes 0.3 s. Simulation, STL takes 0.2 s. Simulation, OBJ takes 0.3 s. Visual, GLB takes 0.3 s. Visual, OBJ takes 0.3 s

Mode and format	1–2 read	3 resolve	4 geometry	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	3 ms	20 ms	10 ms	39 ms	1 ms	2 ms	0.1	0.2
Simulation, STEP	3 ms	16 ms	9 ms	39 ms	33 ms	2 ms	0.2	0.3
Simulation, STL	3 ms	15 ms	10 ms	38 ms	2 ms	2 ms	0.1	0.2
Simulation, OBJ	3 ms	17 ms	10 ms	51 ms	24 ms	2 ms	0.2	0.3
Visual, GLB	3 ms	16 ms	6 ms	54 ms	2 ms	36 ms	0.2	0.3
Visual, OBJ	3 ms	16 ms	10 ms	53 ms	23 ms	34 ms	0.2	0.3

Board	Repo: torlye/pocket-reform Board: `pref-side-panel-headphones-d8.kicad_pcb`
Folder	case-plate-pcbs
Complexity	62 / 1000 (size 17, features 45)
KESE features	curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	0, 0, 0
Triangles, simulation	6,036 in 3 parts
Note	panel, no components
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	165 kB	38 MB
STEP	780 kB	40 MB
STL	302 kB	38 MB
OBJ	564 kB	39 MB
Visual
GLB	209 kB	55 MB
OBJ	537 kB	56 MB

2901. pref-side-panel-ports-d8

Reading, start-up and exit take 43% to 58% of a run. Simulation, GLB takes 0.3 s. Simulation, STEP takes 0.4 s. Simulation, STL takes 0.4 s. Simulation, OBJ takes 0.4 s. Visual, GLB takes 0.4 s. Visual, OBJ takes 0.4 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	13 ms	30 ms	7 ms	0.0 ms	93 ms	2 ms	2 ms	0.2	0.3
Simulation, STEP	14 ms	31 ms	5 ms	0.0 ms	0.1	93 ms	2 ms	0.2	0.4
Simulation, STL	19 ms	45 ms	5 ms	0.1 ms	0.1	3 ms	2 ms	0.2	0.4
Simulation, OBJ	19 ms	34 ms	4 ms	0.1 ms	0.1	68 ms	2 ms	0.2	0.4
Visual, GLB	13 ms	30 ms	11 ms	0.0 ms	0.1	3 ms	30 ms	0.2	0.4
Visual, OBJ	14 ms	35 ms	4 ms	0.1 ms	0.1	58 ms	32 ms	0.2	0.4

Board	Repo: torlye/pocket-reform Board: `pref-side-panel-ports-d8.kicad_pcb`
Folder	case-plate-pcbs
Complexity	62 / 1000 (size 17, features 45)
KESE features	curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	0, 0, 0
Triangles, simulation	12,548 in 3 parts
Note	panel, no components
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	337 kB	41 MB
STEP	2.0 MB	43 MB
STL	628 kB	41 MB
OBJ	1.2 MB	44 MB
Visual
GLB	444 kB	54 MB
OBJ	1.2 MB	56 MB

2902. pref-side-panel-ports

Reading, start-up and exit take 43% to 64% of a run. Simulation, GLB takes 0.4 s. Simulation, STEP takes 0.5 s. Simulation, STL takes 0.4 s. Simulation, OBJ takes 0.5 s. Visual, GLB takes 0.5 s. Visual, OBJ takes 0.6 s

Mode and format	1–2 read	3 resolve	4 geometry	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	70 ms	36 ms	13 ms	96 ms	3 ms	3 ms	0.2	0.4
Simulation, STEP	75 ms	36 ms	16 ms	95 ms	83 ms	3 ms	0.2	0.5
Simulation, STL	77 ms	38 ms	12 ms	0.1	4 ms	3 ms	0.2	0.4
Simulation, OBJ	75 ms	42 ms	13 ms	0.1	82 ms	4 ms	0.2	0.5
Visual, GLB	76 ms	38 ms	13 ms	0.1	3 ms	32 ms	0.2	0.5
Visual, OBJ	72 ms	38 ms	14 ms	0.1	95 ms	31 ms	0.2	0.6

Board	Repo: torlye/pocket-reform Board: `pref-side-panel-ports.kicad_pcb`
Folder	case-plate-pcbs
Complexity	17 / 1000 (size 17, features 0)
Tested	9th November 2026
Copper layers	2
File format	KiCad 6 (20211014)
Parts, tracks, vias	0, 0, 0
Triangles, simulation	14,848 in 4 parts
Note	panel, no components
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	426 kB	61 MB
STEP	2.7 MB	64 MB
STL	743 kB	62 MB
OBJ	1.5 MB	65 MB
Visual
GLB	537 kB	86 MB
OBJ	1.4 MB	90 MB

2903. pocket-reform-charger

pocket-reform-charger: stages 4 and 6 take 55% to 79% of a run. Simulation, GLB takes 7.0 s. Simulation, STEP takes 9.5 s. Simulation, STL takes 7.2 s. Simulation, OBJ takes 10 s. Visual, GLB takes 10 s. Visual, OBJ takes 12 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.7	2.6	0.4 ms	2.7	96 ms	0.4	0.2	7.0
Simulation, STEP	0.3	0.7	2.8	0.3 ms	2.9	2.3	0.3	0.3	9.5
Simulation, STL	0.2	0.7	2.5	0.2 ms	2.8	0.3	0.4	0.2	7.2
Simulation, OBJ	0.3	0.6	2.6	0.2 ms	3.0	3.0	0.4	0.2	10.2
Visual, GLB	0.3	0.7	2.6	0.3 ms	5.4	79 ms	0.8	0.2	10.1
Visual, OBJ	0.3	0.6	2.5	0.4 ms	5.3	2.1	0.8	0.2	11.9

Board	Repo: torlye/pocket-reform Board: `pocket-reform-charger.kicad_pcb`
Folder	pocket-reform-charger
Complexity	301 / 1000 (size 226, features 75)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	67, 352, 108
Triangles, simulation	710,712 in 77 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	25 MB	373 MB
STEP	109 MB	432 MB
STL	36 MB	380 MB
OBJ	72 MB	521 MB
Visual
GLB	17 MB	483 MB
OBJ	51 MB	487 MB

2904. pocket-reform-headphones

pocket-reform-headphones: stages 4 and 6 take 47% to 74% of a run. Simulation, GLB takes 1.8 s. Simulation, STEP takes 2.5 s. Simulation, STL takes 1.7 s. Simulation, OBJ takes 2.3 s. Visual, GLB takes 2.5 s. Visual, OBJ takes 2.9 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.5	0.2 ms	0.7	22 ms	55 ms	0.2	1.8
Simulation, STEP	0.1	0.2	0.5	0.1 ms	0.7	0.8	58 ms	0.2	2.5
Simulation, STL	0.1	0.2	0.5	0.2 ms	0.7	35 ms	54 ms	0.2	1.7
Simulation, OBJ	0.1	0.2	0.5	0.2 ms	0.7	0.6	64 ms	0.2	2.3
Visual, GLB	0.1	0.2	0.5	0.1 ms	1.3	20 ms	0.1	0.2	2.5
Visual, OBJ	0.1	0.2	0.5	0.1 ms	1.3	0.5	0.1	0.2	2.9

Board	Repo: torlye/pocket-reform Board: `pocket-reform-headphones.kicad_pcb`
Folder	pocket-reform-headphones
Complexity	203 / 1000 (size 128, features 75)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	12, 71, 31
Triangles, simulation	126,004 in 25 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	4.5 MB	197 MB
STEP	22 MB	211 MB
STL	6.3 MB	197 MB
OBJ	12 MB	197 MB
Visual
GLB	3.9 MB	175 MB
OBJ	11 MB	178 MB

2905. pocket-reform-keyboard-kailh-ortho

Stages 4 and 6 take 45% to 82% of a run. Simulation, GLB takes 38 s. Simulation, STEP takes 48 s. Simulation, STL takes 39 s. Simulation, OBJ takes 63 s. Visual, GLB takes 62 s. Visual, OBJ takes 82 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.6	5.0	13.7	0.8 ms	14.8	0.8	2.0	0.3	38.2
Simulation, STEP	1.4	4.8	13.4	0.7 ms	15.0	10.9	2.0	0.3	47.7
Simulation, STL	1.4	4.7	13.4	0.8 ms	15.4	1.7	2.0	0.3	38.9
Simulation, OBJ	1.5	4.8	13.4	2 ms	15.0	26.1	2.0	0.3	63.0
Visual, GLB	1.4	4.7	13.2	0.7 ms	37.7	0.4	4.4	0.3	62.2
Visual, OBJ	1.5	4.9	13.3	0.7 ms	38.4	18.1	5.3	0.3	81.7

Board	Repo: torlye/pocket-reform Board: `pocket-reform-keyboard-kailh-ortho.kicad_pcb`
Folder	pocket-reform-keyboard-kailh-ortho
Complexity	360 / 1000 (size 270, features 90)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours
Tested	9th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	297, 2,155, 530
Triangles, simulation	4,621,726 in 199 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	155 MB	1.6 GB
STEP	575 MB	1.8 GB
STL	231 MB	1.6 GB
OBJ	489 MB	2.9 GB
Visual
GLB	104 MB	1.7 GB
OBJ	330 MB	2.1 GB

2906. pocket-reform-motherboard

pocket-reform-motherboard: stages 4 and 6 take 51% to 84% of a run. Simulation, GLB takes 2 min. Simulation, STEP takes 2 min. Simulation, STL takes 2 min. Simulation, OBJ takes 3 min. Visual, GLB takes 2 min. Visual, OBJ takes 3 min

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.6	9.9	41.0	2 ms	42.7	1.7	6.8	0.5	105.2
Simulation, STEP	2.6	10.5	42.6	2 ms	42.7	24.8	7.1	0.5	130.7
Simulation, STL	3.0	10.1	41.3	3 ms	41.0	3.7	6.6	0.4	106.1
Simulation, OBJ	2.9	10.4	41.3	2 ms	41.2	57.7	6.4	0.4	160.3
Visual, GLB	2.9	10.6	40.9	3 ms	83.1	0.8	9.0	0.4	147.7
Visual, OBJ	2.8	9.6	38.7	2 ms	84.6	33.2	9.1	0.3	178.4

Board	Repo: torlye/pocket-reform Board: `pocket-reform-motherboard.kicad_pcb`
Folder	pocket-reform-motherboard
Complexity	446 / 1000 (size 316, features 130)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours
Tested	9th November 2026
Copper layers	6
File format	KiCad 10 (20260206)
Parts, tracks, vias	412, 6,707, 1,318
Triangles, simulation	9,380,390 in 633 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	315 MB	2.4 GB
STEP	1.3 GB	3.4 GB
STL	469 MB	2.4 GB
OBJ	996 MB	5.9 GB
Visual
GLB	182 MB	2.9 GB
OBJ	592 MB	3.8 GB

2907. nref-wifi-m2

nref-wifi-m2: stages 4 and 6 take 46% to 79% of a run. Simulation, GLB takes 5.7 s. Simulation, STEP takes 7.6 s. Simulation, STL takes 5.9 s. Simulation, OBJ takes 8.8 s. Visual, GLB takes 8.3 s. Visual, OBJ takes 11 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.6	1.8	0.3 ms	2.4	0.1	0.4	0.2	5.7
Simulation, STEP	0.3	0.7	1.8	0.3 ms	2.3	1.9	0.3	0.3	7.6
Simulation, STL	0.3	0.6	1.8	0.3 ms	2.3	0.2	0.4	0.3	5.9
Simulation, OBJ	0.3	0.6	1.7	0.3 ms	2.4	3.3	0.4	0.2	8.8
Visual, GLB	0.3	0.7	1.8	0.3 ms	4.7	67 ms	0.5	0.3	8.3
Visual, OBJ	0.3	0.6	1.8	0.3 ms	4.9	2.4	0.6	0.2	10.9

Board	Repo: torlye/pocket-reform Board: `nref-wifi-m2.kicad_pcb`
Folder	pocket-reform-wifi
Complexity	279 / 1000 (size 179, features 100)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	28, 394, 129
Triangles, simulation	567,428 in 76 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	20 MB	318 MB
STEP	79 MB	382 MB
STL	28 MB	315 MB
OBJ	57 MB	439 MB
Visual
GLB	14 MB	401 MB
OBJ	42 MB	395 MB

2908. pocket-reform-wifi

pocket-reform-wifi: stages 4 and 6 take 48% to 81% of a run. Simulation, GLB takes 6.3 s. Simulation, STEP takes 8.4 s. Simulation, STL takes 6.6 s. Simulation, OBJ takes 10 s. Visual, GLB takes 9.3 s. Visual, OBJ takes 12 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.7	2.3	0.6 ms	2.4	0.1	0.4	0.2	6.3
Simulation, STEP	0.3	0.7	2.2	0.4 ms	2.5	2.1	0.4	0.2	8.4
Simulation, STL	0.3	0.7	2.3	0.3 ms	2.6	0.2	0.4	0.2	6.6
Simulation, OBJ	0.3	0.7	2.2	0.4 ms	2.6	3.7	0.4	0.2	10.2
Visual, GLB	0.3	0.7	2.2	0.4 ms	5.3	80 ms	0.5	0.2	9.3
Visual, OBJ	0.3	0.7	2.2	0.4 ms	5.0	2.5	0.7	0.2	11.6

Board	Repo: torlye/pocket-reform Board: `pocket-reform-wifi.kicad_pcb`
Folder	pocket-reform-wifi
Complexity	274 / 1000 (size 184, features 90)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, knockout text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 10 (20260206)
Parts, tracks, vias	33, 457, 161
Triangles, simulation	719,012 in 87 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	25 MB	368 MB
STEP	102 MB	438 MB
STL	36 MB	359 MB
OBJ	72 MB	522 MB
Visual
GLB	17 MB	435 MB
OBJ	52 MB	467 MB

2909. pods_panel

pods_panel: stages 4 and 6 take 53% to 82% of a run. Simulation, GLB takes 13 s. Simulation, STEP takes 17 s. Simulation, STL takes 13 s. Simulation, OBJ takes 18 s. Visual, GLB takes 21 s. Visual, OBJ takes 24 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.8	5.7	1 ms	4.6	0.2	0.6	0.2	13.4
Simulation, STEP	0.4	1.8	5.7	0.9 ms	4.7	3.2	0.6	0.2	16.6
Simulation, STL	0.3	1.6	5.8	1 ms	4.5	0.5	0.6	0.2	13.5
Simulation, OBJ	0.3	1.7	5.7	0.7 ms	4.1	5.9	0.6	0.2	18.5
Visual, GLB	0.3	1.7	5.7	1 ms	11.0	0.2	1.3	0.3	20.5
Visual, OBJ	0.4	1.6	5.8	1 ms	10.2	4.1	1.4	0.2	23.8

Board	Repo: ToyotaInfoTech/RAMN Board: `pods_panel.kicad_pcb`
Folder	hardware / build
Complexity	233 / 1000 (size 168, features 65)
KESE features	through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	50, 596, 59
Triangles, simulation	1,424,436 in 146 parts
Note	panel
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	48 MB	569 MB
STEP	206 MB	697 MB
STL	71 MB	638 MB
OBJ	146 MB	941 MB
Visual
GLB	32 MB	724 MB
OBJ	96 MB	725 MB

2910. ramn

ramn: stages 4 and 6 take 63% to 86% of a run. Simulation, GLB takes 19 s. Simulation, STEP takes 24 s. Simulation, STL takes 19 s. Simulation, OBJ takes 27 s. Visual, GLB takes 24 s. Visual, OBJ takes 31 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.2	7.5	0.8 ms	9.0	0.3	0.6	0.2	19.1
Simulation, STEP	0.3	1.2	7.4	0.9 ms	8.9	4.7	0.7	0.2	23.5
Simulation, STL	0.3	1.2	7.5	2 ms	8.9	0.5	0.6	0.2	19.4
Simulation, OBJ	0.3	1.3	7.8	1.0 ms	8.9	7.3	0.7	0.2	26.5
Visual, GLB	0.4	1.3	7.4	1 ms	13.3	0.2	1.5	0.2	24.2
Visual, OBJ	0.3	1.3	7.8	1.0 ms	14.2	5.6	1.7	0.3	31.3

Board	Repo: ToyotaInfoTech/RAMN Board: `ramn.kicad_pcb`
Folder	hardware / V1_revB / 0_ramn
Complexity	320 / 1000 (size 245, features 75)
KESE features	through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline
Tested	9th November 2026
Copper layers	2
File format	KiCad 5 (20171130)
Parts, tracks, vias	86, 1,705, 198
Triangles, simulation	1,779,576 in 184 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	60 MB	689 MB
STEP	285 MB	834 MB
STL	89 MB	708 MB
OBJ	183 MB	1.2 GB
Visual
GLB	47 MB	839 MB
OBJ	143 MB	993 MB

2911. screens

screens: stages 4 and 6 take 51% to 84% of a run. Simulation, GLB takes 4.2 s. Simulation, STEP takes 5.6 s. Simulation, STL takes 4.2 s. Simulation, OBJ takes 6.2 s. Visual, GLB takes 6.4 s. Visual, OBJ takes 7.2 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.3	1.9	0.5 ms	1.4	75 ms	0.3	0.2	4.2
Simulation, STEP	0.1	0.3	1.9	0.2 ms	1.3	1.4	0.3	0.2	5.6
Simulation, STL	0.1	0.3	1.8	0.4 ms	1.4	96 ms	0.3	0.2	4.2
Simulation, OBJ	0.1	0.3	1.8	0.5 ms	1.4	2.1	0.3	0.2	6.2
Visual, GLB	0.1	0.3	1.9	0.4 ms	3.4	42 ms	0.3	0.2	6.4
Visual, OBJ	0.1	0.3	1.9	0.3 ms	3.0	1.5	0.3	0.2	7.2

Board	Repo: ToyotaInfoTech/RAMN Board: `screens.kicad_pcb`
Folder	hardware / V1_revB / 1_screens
Complexity	182 / 1000 (size 127, features 55)
KESE features	through vias, filled zones, copper text, curved board outline
Tested	9th November 2026
Copper layers	2
File format	KiCad 5 (20171130)
Parts, tracks, vias	5, 218, 15
Triangles, simulation	435,086 in 49 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	14 MB	260 MB
STEP	60 MB	314 MB
STL	22 MB	274 MB
OBJ	43 MB	335 MB
Visual
GLB	9.4 MB	305 MB
OBJ	28 MB	309 MB

2912. chassis

chassis: stages 4 and 6 take 53% to 79% of a run. Simulation, GLB takes 3.1 s. Simulation, STEP takes 3.8 s. Simulation, STL takes 2.8 s. Simulation, OBJ takes 4.0 s. Visual, GLB takes 4.2 s. Visual, OBJ takes 4.8 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	1.2	0.3 ms	1.1	43 ms	0.2	0.3	3.1
Simulation, STEP	99 ms	0.2	1.1	0.2 ms	0.9	1.1	0.2	0.2	3.8
Simulation, STL	98 ms	0.2	1.1	0.2 ms	1.0	80 ms	0.2	0.2	2.8
Simulation, OBJ	96 ms	0.2	1.1	0.2 ms	1.0	1.2	0.2	0.2	4.0
Visual, GLB	0.2	0.2	1.2	0.3 ms	2.1	31 ms	0.3	0.2	4.2
Visual, OBJ	0.1	0.2	1.2	0.3 ms	2.0	0.8	0.2	0.2	4.8

Board	Repo: ToyotaInfoTech/RAMN Board: `chassis.kicad_pcb`
Folder	hardware / V1_revB / 2_chassis
Complexity	200 / 1000 (size 125, features 75)
KESE features	through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline
Tested	9th November 2026
Copper layers	2
File format	KiCad 5 (20171130)
Parts, tracks, vias	13, 94, 12
Triangles, simulation	320,112 in 41 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	11 MB	259 MB
STEP	45 MB	270 MB
STL	16 MB	268 MB
OBJ	32 MB	255 MB
Visual
GLB	7.1 MB	250 MB
OBJ	21 MB	246 MB

2913. powertrain

powertrain: stages 4 and 6 take 51% to 82% of a run. Simulation, GLB takes 3.4 s. Simulation, STEP takes 4.5 s. Simulation, STL takes 3.2 s. Simulation, OBJ takes 5.0 s. Visual, GLB takes 4.3 s. Visual, OBJ takes 5.5 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	1.3	0.3 ms	1.3	47 ms	0.3	0.2	3.4
Simulation, STEP	0.1	0.2	1.3	0.2 ms	1.2	1.2	0.2	0.2	4.5
Simulation, STL	0.1	0.2	1.3	0.2 ms	1.2	73 ms	0.2	0.2	3.2
Simulation, OBJ	0.1	0.2	1.4	0.2 ms	1.2	1.7	0.2	0.2	5.0
Visual, GLB	0.1	0.2	1.3	0.3 ms	2.3	34 ms	0.2	0.2	4.3
Visual, OBJ	0.1	0.2	1.3	0.3 ms	2.4	1.1	0.2	0.2	5.5

Board	Repo: ToyotaInfoTech/RAMN Board: `powertrain.kicad_pcb`
Folder	hardware / V1_revB / 3_powertrain
Complexity	190 / 1000 (size 125, features 65)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	15, 94, 8
Triangles, simulation	344,580 in 41 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	11 MB	242 MB
STEP	48 MB	284 MB
STL	17 MB	253 MB
OBJ	34 MB	248 MB
Visual
GLB	7.8 MB	265 MB
OBJ	23 MB	262 MB

2914. body

body: stages 4 and 6 take 51% to 79% of a run. Simulation, GLB takes 3.4 s. Simulation, STEP takes 4.8 s. Simulation, STL takes 3.4 s. Simulation, OBJ takes 5.2 s. Visual, GLB takes 5.1 s. Visual, OBJ takes 6.1 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.3	1.3	0.3 ms	1.2	57 ms	0.2	0.2	3.4
Simulation, STEP	0.2	0.3	1.5	0.3 ms	1.1	1.3	0.2	0.2	4.8
Simulation, STL	0.1	0.3	1.3	0.4 ms	1.2	93 ms	0.2	0.2	3.4
Simulation, OBJ	0.1	0.3	1.5	0.3 ms	1.2	1.7	0.2	0.2	5.2
Visual, GLB	0.1	0.3	1.4	0.3 ms	2.7	38 ms	0.4	0.2	5.1
Visual, OBJ	0.1	0.3	1.5	0.3 ms	2.7	1.0	0.3	0.2	6.1

Board	Repo: ToyotaInfoTech/RAMN Board: `body.kicad_pcb`
Folder	hardware / V1_revB / 4_body
Complexity	204 / 1000 (size 139, features 65)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline
Tested	9th November 2026
Copper layers	2
File format	KiCad 5 (20171130)
Parts, tracks, vias	17, 191, 24
Triangles, simulation	369,154 in 48 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	12 MB	246 MB
STEP	55 MB	295 MB
STL	18 MB	273 MB
OBJ	37 MB	300 MB
Visual
GLB	9.1 MB	287 MB
OBJ	27 MB	293 MB

2915. debugger

debugger: stages 4 and 6 take 48% to 82% of a run. Simulation, GLB takes 4.5 s. Simulation, STEP takes 6.2 s. Simulation, STL takes 4.5 s. Simulation, OBJ takes 6.9 s. Visual, GLB takes 6.3 s. Visual, OBJ takes 7.8 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.4	2.0	0.5 ms	1.5	69 ms	0.3	0.2	4.5
Simulation, STEP	0.1	0.4	2.0	0.3 ms	1.6	1.6	0.3	0.2	6.2
Simulation, STL	0.2	0.4	1.9	0.4 ms	1.4	0.1	0.3	0.2	4.5
Simulation, OBJ	0.2	0.4	1.9	0.4 ms	1.4	2.5	0.3	0.3	6.9
Visual, GLB	0.1	0.4	2.0	0.3 ms	3.2	41 ms	0.3	0.3	6.3
Visual, OBJ	0.1	0.4	2.0	0.4 ms	3.2	1.5	0.4	0.2	7.8

Board	Repo: ToyotaInfoTech/RAMN Board: `debugger.kicad_pcb`
Folder	hardware / V1_revB / 5_debugger
Complexity	159 / 1000 (size 114, features 45)
KESE features	through vias, filled zones, copper text
Tested	9th November 2026
Copper layers	2
File format	KiCad 5 (20171130)
Parts, tracks, vias	2, 164, 7
Triangles, simulation	430,318 in 40 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	14 MB	267 MB
STEP	57 MB	306 MB
STL	22 MB	269 MB
OBJ	43 MB	323 MB
Visual
GLB	8.7 MB	292 MB
OBJ	26 MB	295 MB

2916. 6-Slot-Backplane

6-Slot-Backplane: stages 4 and 6 take 52% to 83% of a run. Simulation, GLB takes 62 s. Simulation, STEP takes 75 s. Simulation, STL takes 65 s. Simulation, OBJ takes 99 s. Visual, GLB takes 90 s. Visual, OBJ takes 2 min

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	7.0	27.0	2 ms	23.9	1.1	2.6	0.3	62.5
Simulation, STEP	0.5	6.7	27.3	2 ms	23.3	14.5	2.5	0.4	75.2
Simulation, STL	0.6	6.8	27.6	2 ms	24.0	2.5	2.8	0.4	64.6
Simulation, OBJ	0.7	7.0	27.0	2 ms	24.3	37.3	2.7	0.4	99.3
Visual, GLB	0.7	7.5	29.4	3 ms	45.7	0.5	6.1	0.3	90.2
Visual, OBJ	0.8	7.4	27.0	2 ms	44.4	15.6	7.1	0.3	102.5

Board	Repo: transistorfet/retroverse Board: `6-Slot-Backplane.kicad_pcb`
Folder	components / backplane / 6-Slot-Backplane
Complexity	201 / 1000 (size 151, features 50)
KESE features	rounded, trapezoid or chamfered pads, copper drawings, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 8 (20240108)
Parts, tracks, vias	123, 52, 0
Triangles, simulation	6,834,688 in 155 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	214 MB	1.6 GB
STEP	694 MB	2.2 GB
STL	342 MB	1.6 GB
OBJ	713 MB	4.2 GB
Visual
GLB	103 MB	2.0 GB
OBJ	331 MB	2.2 GB

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