Corpus Testing 26

Corpus Page 26

Part 26 of 29 of Corpus Testing: boards 2,701 to 2,808, six runs each, one file format a run, as Corpus Testing describes.

2701. ail-LED

ail-LED: stages 4 and 6 take 41% to 72% of a run. Simulation, GLB takes 1.2 s. Simulation, STEP takes 1.9 s. Simulation, STL takes 1.2 s. Simulation, OBJ takes 1.6 s. Visual, GLB takes 1.7 s. Visual, OBJ takes 2.0 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	99 ms	83 ms	0.3	0.2 ms	0.6	18 ms	43 ms	0.2	1.2
Simulation, STEP	0.1	0.1	0.2	0.1 ms	0.6	0.7	38 ms	0.2	1.9
Simulation, STL	98 ms	78 ms	0.2	0.1 ms	0.5	29 ms	38 ms	0.2	1.2
Simulation, OBJ	92 ms	76 ms	0.2	0.1 ms	0.5	0.4	40 ms	0.2	1.6
Visual, GLB	0.1	93 ms	0.2	0.1 ms	1.0	11 ms	66 ms	0.2	1.7
Visual, OBJ	97 ms	77 ms	0.2	0.1 ms	1.1	0.3	63 ms	0.2	2.0

Board	Repo: sufst/pcb Board: `ail-LED.kicad_pcb`
Folder	ail-LED
Complexity	221 / 1000 (size 96, features 125)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	18, 8, 3
Triangles, simulation	99,858 in 27 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	3.9 MB	180 MB
STEP	17 MB	196 MB
STL	5.0 MB	183 MB
OBJ	11 MB	185 MB
Visual
GLB	2.4 MB	153 MB
OBJ	6.7 MB	157 MB

2702. ail-LED_handsolder

ail-LED_handsolder: stages 4 and 6 take 41% to 73% of a run. Simulation, GLB takes 1.2 s. Simulation, STEP takes 2.1 s. Simulation, STL takes 1.3 s. Simulation, OBJ takes 1.7 s. Visual, GLB takes 2.0 s. Visual, OBJ takes 2.2 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	76 ms	0.2	0.1 ms	0.5	20 ms	44 ms	0.2	1.2
Simulation, STEP	0.1	74 ms	0.2	0.1 ms	0.6	0.8	48 ms	0.2	2.1
Simulation, STL	99 ms	84 ms	0.2	0.1 ms	0.6	32 ms	45 ms	0.2	1.3
Simulation, OBJ	97 ms	79 ms	0.2	0.1 ms	0.5	0.5	75 ms	0.2	1.7
Visual, GLB	0.1	89 ms	0.2	0.1 ms	1.2	14 ms	88 ms	0.2	2.0
Visual, OBJ	0.1	0.1	0.2	0.1 ms	1.2	0.3	71 ms	0.2	2.2

Board	Repo: sufst/pcb Board: `ail-LED_handsolder.kicad_pcb`
Folder	ail-LED
Complexity	205 / 1000 (size 95, features 110)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	18, 7, 3
Triangles, simulation	96,088 in 27 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	3.8 MB	182 MB
STEP	16 MB	194 MB
STL	4.8 MB	182 MB
OBJ	10 MB	187 MB
Visual
GLB	2.3 MB	153 MB
OBJ	6.2 MB	154 MB

2703. ail

ail: stages 4 and 6 take 42% to 74% of a run. Simulation, GLB takes 1.9 s. Simulation, STEP takes 2.8 s. Simulation, STL takes 2.0 s. Simulation, OBJ takes 2.3 s. Visual, GLB takes 2.6 s. Visual, OBJ takes 3.3 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.1	0.5	0.3 ms	0.8	25 ms	68 ms	0.2	1.9
Simulation, STEP	0.2	0.1	0.5	0.1 ms	0.7	1.0	56 ms	0.2	2.8
Simulation, STL	0.2	0.2	0.5	0.2 ms	0.8	37 ms	60 ms	0.2	2.0
Simulation, OBJ	0.1	0.1	0.5	0.2 ms	0.7	0.6	59 ms	0.2	2.3
Visual, GLB	0.2	0.1	0.5	0.2 ms	1.4	18 ms	0.1	0.2	2.6
Visual, OBJ	0.2	0.2	0.6	0.2 ms	1.5	0.5	0.1	0.3	3.3

Board	Repo: sufst/pcb Board: `ail.kicad_pcb`
Folder	ail
Complexity	211 / 1000 (size 126, features 85)
KESE features	rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	29, 83, 0
Triangles, simulation	114,676 in 34 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	4.1 MB	199 MB
STEP	23 MB	212 MB
STL	5.7 MB	198 MB
OBJ	11 MB	198 MB
Visual
GLB	3.5 MB	172 MB
OBJ	9.5 MB	167 MB

2704. debug-board

debug-board: stages 4 and 6 take 47% to 80% of a run. Simulation, GLB takes 4.1 s. Simulation, STEP takes 5.8 s. Simulation, STL takes 4.1 s. Simulation, OBJ takes 6.1 s. Visual, GLB takes 5.8 s. Visual, OBJ takes 8.2 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.4	1.6	0.2 ms	1.4	71 ms	0.2	0.2	4.1
Simulation, STEP	0.2	0.4	1.6	0.3 ms	1.4	1.7	0.3	0.2	5.8
Simulation, STL	0.2	0.5	1.5	0.2 ms	1.4	0.1	0.3	0.2	4.1
Simulation, OBJ	0.2	0.5	1.5	0.3 ms	1.4	2.1	0.2	0.2	6.1
Visual, GLB	0.2	0.4	1.4	0.2 ms	3.3	49 ms	0.3	0.2	5.8
Visual, OBJ	0.2	0.4	1.5	0.3 ms	3.5	1.8	0.5	0.2	8.2

Board	Repo: sufst/pcb Board: `debug-board.kicad_pcb`
Folder	archive / debug-board
Complexity	311 / 1000 (size 196, features 115)
KESE features	through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	53, 279, 21
Triangles, simulation	435,016 in 66 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	15 MB	318 MB
STEP	68 MB	318 MB
STL	22 MB	313 MB
OBJ	43 MB	340 MB
Visual
GLB	11 MB	339 MB
OBJ	33 MB	339 MB

2705. latching

latching: stages 4 and 6 take 52% to 78% of a run. Simulation, GLB takes 4.0 s. Simulation, STEP takes 5.4 s. Simulation, STL takes 4.0 s. Simulation, OBJ takes 5.9 s. Visual, GLB takes 6.0 s. Visual, OBJ takes 7.8 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	1.4	0.3 ms	1.7	74 ms	0.2	0.2	4.0
Simulation, STEP	0.2	0.3	1.3	0.4 ms	1.6	1.5	0.2	0.2	5.4
Simulation, STL	0.2	0.3	1.4	0.2 ms	1.6	0.1	0.2	0.2	4.0
Simulation, OBJ	0.2	0.4	1.4	0.3 ms	1.7	1.9	0.2	0.2	5.9
Visual, GLB	0.2	0.4	1.4	0.4 ms	3.3	55 ms	0.5	0.2	6.0
Visual, OBJ	0.2	0.3	1.4	0.3 ms	3.5	1.5	0.6	0.2	7.8

Board	Repo: sufst/pcb Board: `latching.kicad_pcb`
Folder	archive / latching
Complexity	257 / 1000 (size 157, features 100)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	41, 268, 54
Triangles, simulation	470,068 in 51 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	16 MB	297 MB
STEP	74 MB	350 MB
STL	24 MB	296 MB
OBJ	47 MB	373 MB
Visual
GLB	13 MB	397 MB
OBJ	39 MB	391 MB

2706. segment

segment: stages 4 and 6 take 45% to 80% of a run. Simulation, GLB takes 8.7 s. Simulation, STEP takes 11 s. Simulation, STL takes 9.1 s. Simulation, OBJ takes 14 s. Visual, GLB takes 13 s. Visual, OBJ takes 16 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.2	3.3	0.5 ms	3.0	0.2	0.6	0.2	8.7
Simulation, STEP	0.3	1.2	3.3	1 ms	2.9	2.4	0.6	0.3	11.0
Simulation, STL	0.3	1.2	3.4	0.4 ms	3.0	0.4	0.6	0.2	9.1
Simulation, OBJ	0.3	1.3	3.5	0.4 ms	3.0	5.4	0.6	0.2	14.2
Visual, GLB	0.3	1.2	3.3	0.5 ms	7.1	83 ms	0.8	0.2	13.0
Visual, OBJ	0.3	1.3	3.4	0.4 ms	6.6	3.1	0.8	0.2	15.8

Board	Repo: sufst/pcb Board: `segment.kicad_pcb`
Folder	archive / segment
Complexity	242 / 1000 (size 157, features 85)
KESE features	rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 7 (20221018)
Parts, tracks, vias	19, 261, 0
Triangles, simulation	940,566 in 66 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	32 MB	402 MB
STEP	120 MB	447 MB
STL	47 MB	410 MB
OBJ	95 MB	649 MB
Visual
GLB	18 MB	506 MB
OBJ	54 MB	478 MB

2707. sensor-board

sensor-board: stages 4 and 6 take 51% to 82% of a run. Simulation, GLB takes 12 s. Simulation, STEP takes 16 s. Simulation, STL takes 13 s. Simulation, OBJ takes 20 s. Visual, GLB takes 17 s. Visual, OBJ takes 21 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.1	4.5	0.7 ms	4.9	0.2	0.6	0.3	12.1
Simulation, STEP	0.5	1.1	4.2	0.4 ms	5.0	4.1	0.6	0.3	15.8
Simulation, STL	0.5	1.1	4.8	0.6 ms	5.2	0.4	0.6	0.3	13.0
Simulation, OBJ	0.6	1.1	4.5	0.7 ms	5.4	7.0	0.6	0.2	19.5
Visual, GLB	0.6	1.1	4.3	0.5 ms	9.3	0.1	1.0	0.3	16.6
Visual, OBJ	0.5	1.1	4.2	0.5 ms	9.3	4.4	1.3	0.2	21.1

Board	Repo: sufst/pcb Board: `sensor-board.kicad_pcb`
Folder	archive / sensor-board
Complexity	319 / 1000 (size 234, features 85)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 8 (20240108)
Parts, tracks, vias	95, 679, 65
Triangles, simulation	1,192,408 in 126 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	41 MB	484 MB
STEP	175 MB	570 MB
STL	60 MB	489 MB
OBJ	121 MB	828 MB
Visual
GLB	26 MB	712 MB
OBJ	78 MB	706 MB

2708. strain-gauge-amp-breakout

strain-gauge-amp-breakout: stages 4 and 6 take 44% to 72% of a run. Simulation, GLB takes 1.8 s. Simulation, STEP takes 2.7 s. Simulation, STL takes 1.8 s. Simulation, OBJ takes 2.3 s. Visual, GLB takes 2.6 s. Visual, OBJ takes 3.1 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.5	0.1 ms	0.7	24 ms	63 ms	0.3	1.8
Simulation, STEP	0.1	0.2	0.5	0.1 ms	0.7	0.9	61 ms	0.2	2.7
Simulation, STL	0.1	0.1	0.5	0.1 ms	0.7	34 ms	65 ms	0.2	1.8
Simulation, OBJ	0.1	0.1	0.5	0.1 ms	0.6	0.7	69 ms	0.2	2.3
Visual, GLB	0.1	0.2	0.5	0.1 ms	1.4	20 ms	0.2	0.2	2.6
Visual, OBJ	0.1	0.2	0.5	0.1 ms	1.4	0.6	0.1	0.2	3.1

Board	Repo: sufst/pcb Board: `strain-gauge-amp-breakout.kicad_pcb`
Folder	archive / sensor-board / strain-gauge-amp-breakout
Complexity	188 / 1000 (size 103, features 85)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	10, 30, 3
Triangles, simulation	127,118 in 21 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	4.5 MB	202 MB
STEP	23 MB	206 MB
STL	6.4 MB	200 MB
OBJ	12 MB	205 MB
Visual
GLB	3.7 MB	161 MB
OBJ	10 MB	160 MB

2709. telemetry

telemetry: stages 4 and 6 take 54% to 83% of a run. Simulation, GLB takes 8.6 s. Simulation, STEP takes 11 s. Simulation, STL takes 9.1 s. Simulation, OBJ takes 13 s. Visual, GLB takes 14 s. Visual, OBJ takes 17 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.7	3.4	0.6 ms	3.4	0.2	0.5	0.2	8.6
Simulation, STEP	0.3	0.7	3.6	1 ms	3.1	2.8	0.4	0.2	11.1
Simulation, STL	0.3	0.7	3.6	0.7 ms	3.5	0.3	0.5	0.2	9.1
Simulation, OBJ	0.3	0.7	3.7	1 ms	3.3	4.2	0.5	0.2	12.9
Visual, GLB	0.2	0.7	3.5	0.6 ms	7.7	0.1	1.1	0.2	13.6
Visual, OBJ	0.3	0.7	3.8	0.8 ms	8.0	3.1	0.9	0.2	17.0

Board	Repo: sufst/pcb Board: `telemetry.kicad_pcb`
Folder	archive / telemetry
Complexity	246 / 1000 (size 161, features 85)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	44, 423, 37
Triangles, simulation	1,117,864 in 147 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	37 MB	475 MB
STEP	178 MB	595 MB
STL	56 MB	480 MB
OBJ	112 MB	797 MB
Visual
GLB	26 MB	653 MB
OBJ	79 MB	638 MB

2710. test-rig

test-rig: stages 4 and 6 take 53% to 84% of a run. Simulation, GLB takes 11 s. Simulation, STEP takes 14 s. Simulation, STL takes 11 s. Simulation, OBJ takes 17 s. Visual, GLB takes 16 s. Visual, OBJ takes 20 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	0.9	5.1	0.5 ms	3.7	0.2	0.6	0.2	11.0
Simulation, STEP	0.3	1.0	5.2	0.4 ms	3.4	2.9	0.5	0.2	13.6
Simulation, STL	0.3	0.9	5.0	0.5 ms	3.5	0.3	0.5	0.2	10.7
Simulation, OBJ	0.3	1.0	5.2	0.6 ms	3.8	5.8	0.6	0.2	16.9
Visual, GLB	0.3	1.0	5.3	0.6 ms	8.0	0.1	0.9	0.2	15.8
Visual, OBJ	0.3	0.9	5.1	0.4 ms	8.1	4.1	1.0	0.2	19.7

Board	Repo: sufst/pcb Board: `test-rig.kicad_pcb`
Folder	archive / test-rig
Complexity	264 / 1000 (size 154, features 110)
KESE features	through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	60, 259, 6
Triangles, simulation	1,130,338 in 68 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	38 MB	530 MB
STEP	174 MB	598 MB
STL	57 MB	545 MB
OBJ	114 MB	769 MB
Visual
GLB	27 MB	680 MB
OBJ	82 MB	679 MB

2711. tsal

tsal: stages 4 and 6 take 56% to 80% of a run. Simulation, GLB takes 9.7 s. Simulation, STEP takes 13 s. Simulation, STL takes 11 s. Simulation, OBJ takes 14 s. Visual, GLB takes 15 s. Visual, OBJ takes 19 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.9	3.7	0.5 ms	3.9	0.2	0.6	0.2	9.7
Simulation, STEP	0.3	0.9	3.5	0.5 ms	3.9	3.4	0.5	0.2	12.9
Simulation, STL	0.3	0.9	3.7	0.7 ms	4.6	0.4	0.5	0.2	10.6
Simulation, OBJ	0.3	0.9	3.6	0.5 ms	4.4	4.4	0.5	0.2	14.4
Visual, GLB	0.3	0.9	3.9	0.6 ms	8.3	0.2	1.4	0.2	15.1
Visual, OBJ	0.3	0.9	3.8	0.5 ms	8.2	4.2	1.2	0.3	18.9

Board	Repo: sufst/pcb Board: `tsal.kicad_pcb`
Folder	archive / tsal
Complexity	281 / 1000 (size 181, features 100)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	93, 603, 181
Triangles, simulation	1,101,330 in 93 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	38 MB	522 MB
STEP	182 MB	632 MB
STL	55 MB	529 MB
OBJ	111 MB	753 MB
Visual
GLB	32 MB	618 MB
OBJ	97 MB	707 MB

2712. batak

batak: stages 4 and 6 take 59% to 84% of a run. Simulation, GLB takes 16 s. Simulation, STEP takes 19 s. Simulation, STL takes 15 s. Simulation, OBJ takes 22 s. Visual, GLB takes 23 s. Visual, OBJ takes 28 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	1.1	7.4	0.4 ms	6.1	0.2	0.6	0.3	16.4
Simulation, STEP	0.6	1.2	6.6	0.7 ms	5.6	4.5	0.6	0.3	19.3
Simulation, STL	0.5	1.1	6.6	0.4 ms	5.7	0.4	0.7	0.3	15.1
Simulation, OBJ	0.5	1.0	7.1	0.5 ms	6.0	6.7	0.7	0.3	22.2
Visual, GLB	0.5	1.3	6.7	0.5 ms	12.6	0.1	1.4	0.3	23.0
Visual, OBJ	0.5	1.2	6.8	0.7 ms	12.5	4.7	1.6	0.2	27.6

Board	Repo: sufst/pcb Board: `batak.kicad_pcb`
Folder	batak
Complexity	309 / 1000 (size 189, features 120)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	169, 1,040, 71
Triangles, simulation	1,324,298 in 178 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	45 MB	568 MB
STEP	225 MB	670 MB
STL	66 MB	567 MB
OBJ	136 MB	915 MB
Visual
GLB	32 MB	754 MB
OBJ	96 MB	731 MB

2713. bms-interface

bms-interface: stages 4 and 6 take 48% to 79% of a run. Simulation, GLB takes 4.0 s. Simulation, STEP takes 5.5 s. Simulation, STL takes 4.1 s. Simulation, OBJ takes 6.0 s. Visual, GLB takes 5.9 s. Visual, OBJ takes 7.2 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	1.5	0.2 ms	1.4	66 ms	0.2	0.3	4.0
Simulation, STEP	0.2	0.4	1.5	0.2 ms	1.3	1.5	0.2	0.3	5.5
Simulation, STL	0.2	0.4	1.5	0.2 ms	1.4	0.1	0.2	0.3	4.1
Simulation, OBJ	0.2	0.3	1.5	0.3 ms	1.4	2.1	0.2	0.3	6.0
Visual, GLB	0.2	0.4	1.5	0.2 ms	3.1	51 ms	0.4	0.3	5.9
Visual, OBJ	0.2	0.4	1.5	0.3 ms	3.1	1.4	0.3	0.3	7.2

Board	Repo: sufst/pcb Board: `bms-interface.kicad_pcb`
Folder	bms-interface
Complexity	219 / 1000 (size 129, features 90)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	11, 88, 32
Triangles, simulation	350,714 in 15 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	12 MB	270 MB
STEP	44 MB	291 MB
STL	18 MB	253 MB
OBJ	35 MB	280 MB
Visual
GLB	8.4 MB	272 MB
OBJ	24 MB	274 MB

2714. brake-light

brake-light: stages 4 and 6 take 49% to 78% of a run. Simulation, GLB takes 3.6 s. Simulation, STEP takes 5.2 s. Simulation, STL takes 3.5 s. Simulation, OBJ takes 5.5 s. Visual, GLB takes 5.5 s. Visual, OBJ takes 6.7 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	1.1	0.2 ms	1.6	60 ms	0.2	0.2	3.6
Simulation, STEP	0.2	0.3	1.1	0.2 ms	1.6	1.6	0.2	0.2	5.2
Simulation, STL	0.2	0.3	1.0	0.2 ms	1.6	83 ms	0.2	0.2	3.5
Simulation, OBJ	0.2	0.3	1.1	0.2 ms	1.6	1.9	0.2	0.2	5.5
Visual, GLB	0.2	0.3	1.1	0.2 ms	3.2	50 ms	0.3	0.2	5.5
Visual, OBJ	0.2	0.3	1.1	0.2 ms	3.1	1.5	0.3	0.2	6.7

Board	Repo: sufst/pcb Board: `brake-light.kicad_pcb`
Folder	brake-light
Complexity	247 / 1000 (size 152, features 95)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	62, 203, 13
Triangles, simulation	372,316 in 49 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	14 MB	283 MB
STEP	68 MB	318 MB
STL	19 MB	285 MB
OBJ	39 MB	327 MB
Visual
GLB	10 MB	298 MB
OBJ	30 MB	305 MB

2715. BSPD

BSPD: stages 4 and 6 take 46% to 82% of a run. Simulation, GLB takes 8.1 s. Simulation, STEP takes 10 s. Simulation, STL takes 8.0 s. Simulation, OBJ takes 13 s. Visual, GLB takes 12 s. Visual, OBJ takes 15 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	0.8	2.8	0.3 ms	3.2	0.1	0.6	0.2	8.1
Simulation, STEP	0.4	0.7	2.7	0.2 ms	3.0	2.7	0.5	0.2	10.3
Simulation, STL	0.5	0.7	2.7	0.2 ms	3.1	0.2	0.5	0.2	8.0
Simulation, OBJ	0.4	0.8	2.8	0.3 ms	3.0	4.8	0.5	0.2	12.5
Visual, GLB	0.4	0.7	2.8	0.2 ms	6.8	93 ms	0.8	0.2	11.8
Visual, OBJ	0.4	0.7	2.8	0.2 ms	6.6	3.2	0.7	0.2	14.7

Board	Repo: sufst/pcb Board: `BSPD.kicad_pcb`
Folder	bspd
Complexity	321 / 1000 (size 181, features 140)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	68, 363, 41
Triangles, simulation	986,096 in 70 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	34 MB	415 MB
STEP	160 MB	511 MB
STL	49 MB	452 MB
OBJ	100 MB	672 MB
Visual
GLB	23 MB	562 MB
OBJ	68 MB	552 MB

2716. can-repeater

can-repeater: stages 4 and 6 take 48% to 82% of a run. Simulation, GLB takes 7.4 s. Simulation, STEP takes 10 s. Simulation, STL takes 8.0 s. Simulation, OBJ takes 11 s. Visual, GLB takes 11 s. Visual, OBJ takes 13 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	0.7	2.6	0.3 ms	2.8	0.1	0.4	0.2	7.4
Simulation, STEP	0.4	0.7	2.6	0.3 ms	3.0	2.6	0.4	0.2	10.0
Simulation, STL	0.4	0.7	2.7	0.2 ms	3.2	0.2	0.4	0.2	8.0
Simulation, OBJ	0.4	0.8	2.6	0.2 ms	2.9	4.1	0.4	0.2	11.4
Visual, GLB	0.4	0.7	2.6	0.4 ms	6.0	82 ms	0.4	0.2	10.5
Visual, OBJ	0.4	0.8	2.5	0.3 ms	5.8	2.6	0.6	0.2	12.9

Board	Repo: sufst/pcb Board: `can-repeater.kicad_pcb`
Folder	can-repeater
Complexity	362 / 1000 (size 222, features 140)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	61, 338, 74
Triangles, simulation	787,626 in 94 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	27 MB	370 MB
STEP	130 MB	444 MB
STL	39 MB	379 MB
OBJ	80 MB	554 MB
Visual
GLB	18 MB	499 MB
OBJ	55 MB	497 MB

2717. curr-amp

curr-amp: stages 4 and 6 take 50% to 77% of a run. Simulation, GLB takes 2.8 s. Simulation, STEP takes 3.7 s. Simulation, STL takes 2.7 s. Simulation, OBJ takes 3.7 s. Visual, GLB takes 3.8 s. Visual, OBJ takes 4.6 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	0.9	0.4 ms	1.0	39 ms	0.1	0.2	2.8
Simulation, STEP	0.1	0.2	0.9	0.2 ms	1.0	1.2	0.1	0.2	3.7
Simulation, STL	0.1	0.2	0.9	0.2 ms	1.0	54 ms	0.1	0.3	2.7
Simulation, OBJ	0.2	0.3	0.9	0.2 ms	1.0	1.1	0.1	0.2	3.7
Visual, GLB	0.1	0.2	0.9	0.1 ms	2.0	33 ms	0.2	0.2	3.8
Visual, OBJ	0.2	0.2	1.0	0.2 ms	2.0	0.9	0.2	0.2	4.6

Board	Repo: sufst/pcb Board: `curr-amp.kicad_pcb`
Folder	curr-amp
Complexity	238 / 1000 (size 143, features 95)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	33, 181, 11
Triangles, simulation	219,220 in 37 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	7.6 MB	224 MB
STEP	39 MB	248 MB
STL	11 MB	224 MB
OBJ	22 MB	224 MB
Visual
GLB	6.5 MB	225 MB
OBJ	19 MB	226 MB

2718. Dash-PCB

Dash-PCB: stages 4 and 6 take 51% to 83% of a run. Simulation, GLB takes 12 s. Simulation, STEP takes 15 s. Simulation, STL takes 12 s. Simulation, OBJ takes 17 s. Visual, GLB takes 18 s. Visual, OBJ takes 23 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.3	5.1	0.5 ms	3.9	0.2	0.6	0.2	11.7
Simulation, STEP	0.4	1.2	5.0	0.5 ms	3.9	3.2	0.5	0.3	14.5
Simulation, STL	0.4	1.1	4.9	0.5 ms	3.9	0.3	0.7	0.2	11.7
Simulation, OBJ	0.4	1.2	4.9	0.6 ms	3.8	6.0	0.5	0.2	17.0
Visual, GLB	0.6	1.2	5.1	0.5 ms	9.8	0.1	0.8	0.3	18.0
Visual, OBJ	0.4	1.2	5.2	0.7 ms	10.0	4.6	0.9	0.3	22.7

Board	Repo: sufst/pcb Board: `Dash-PCB.kicad_pcb`
Folder	dash
Complexity	336 / 1000 (size 211, features 125)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	60, 383, 151
Triangles, simulation	1,099,544 in 125 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	38 MB	530 MB
STEP	182 MB	584 MB
STL	55 MB	502 MB
OBJ	114 MB	798 MB
Visual
GLB	29 MB	696 MB
OBJ	86 MB	660 MB

2719. can-node

can-node: stages 4 and 6 take 47% to 78% of a run. Simulation, GLB takes 5.4 s. Simulation, STEP takes 7.0 s. Simulation, STL takes 5.4 s. Simulation, OBJ takes 7.9 s. Visual, GLB takes 8.4 s. Visual, OBJ takes 11 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.7	2.0	0.2 ms	1.8	94 ms	0.3	0.2	5.4
Simulation, STEP	0.3	0.7	2.0	0.3 ms	1.8	1.8	0.3	0.2	7.0
Simulation, STL	0.3	0.6	2.0	0.2 ms	1.8	0.2	0.3	0.2	5.4
Simulation, OBJ	0.3	0.7	1.9	0.2 ms	1.8	2.8	0.3	0.2	7.9
Visual, GLB	0.3	0.7	1.9	0.2 ms	4.7	69 ms	0.6	0.2	8.4
Visual, OBJ	0.3	0.6	2.0	0.4 ms	4.7	2.4	0.6	0.2	10.8

Board	Repo: sufst/pcb Board: `can-node.kicad_pcb`
Folder	debug-board / can-node
Complexity	320 / 1000 (size 205, features 115)
KESE features	through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	86, 337, 35
Triangles, simulation	565,364 in 78 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	20 MB	337 MB
STEP	91 MB	392 MB
STL	28 MB	315 MB
OBJ	57 MB	437 MB
Visual
GLB	16 MB	444 MB
OBJ	46 MB	403 MB

2720. Discharge

Discharge: stages 4 and 6 take 48% to 75% of a run. Simulation, GLB takes 2.1 s. Simulation, STEP takes 3.0 s. Simulation, STL takes 2.2 s. Simulation, OBJ takes 3.1 s. Visual, GLB takes 3.4 s. Visual, OBJ takes 3.6 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.7	0.1 ms	0.7	27 ms	80 ms	0.2	2.1
Simulation, STEP	0.1	0.2	0.8	0.1 ms	0.7	0.9	82 ms	0.2	3.0
Simulation, STL	0.2	0.2	0.7	0.1 ms	0.7	39 ms	0.1	0.2	2.2
Simulation, OBJ	0.1	0.2	0.8	0.1 ms	0.7	0.9	97 ms	0.2	3.1
Visual, GLB	0.1	0.3	0.9	0.2 ms	1.6	23 ms	0.1	0.2	3.4
Visual, OBJ	0.1	0.2	0.8	0.2 ms	1.5	0.6	0.1	0.2	3.6

Board	Repo: sufst/pcb Board: `Discharge.kicad_pcb`
Folder	discharge
Complexity	201 / 1000 (size 121, features 80)
KESE features	through vias, rounded, trapezoid or chamfered pads, curved board outline, knockout text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	16, 72, 5
Triangles, simulation	155,512 in 24 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	5.4 MB	199 MB
STEP	23 MB	208 MB
STL	7.8 MB	195 MB
OBJ	15 MB	200 MB
Visual
GLB	4.0 MB	171 MB
OBJ	11 MB	167 MB

2721. hv_sense

hv_sense: stages 4 and 6 take 47% to 78% of a run. Simulation, GLB takes 3.0 s. Simulation, STEP takes 4.0 s. Simulation, STL takes 2.8 s. Simulation, OBJ takes 4.5 s. Visual, GLB takes 4.3 s. Visual, OBJ takes 5.5 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.4	1.1	0.2 ms	0.9	44 ms	0.1	0.2	3.0
Simulation, STEP	0.1	0.5	1.1	0.3 ms	0.9	1.1	0.1	0.2	4.0
Simulation, STL	0.1	0.4	1.1	0.2 ms	0.9	60 ms	0.1	0.2	2.8
Simulation, OBJ	0.1	0.4	1.1	0.3 ms	1.0	1.5	0.1	0.2	4.5
Visual, GLB	0.1	0.4	1.1	0.2 ms	2.2	34 ms	0.2	0.2	4.3
Visual, OBJ	0.2	0.4	1.1	0.2 ms	2.2	1.1	0.2	0.2	5.5

Board	Repo: sufst/pcb Board: `hv_sense.kicad_pcb`
Folder	hv-sense
Complexity	250 / 1000 (size 150, features 100)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	24, 94, 104
Triangles, simulation	272,196 in 32 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	9.4 MB	227 MB
STEP	32 MB	263 MB
STL	14 MB	242 MB
OBJ	27 MB	228 MB
Visual
GLB	7.7 MB	239 MB
OBJ	22 MB	241 MB

2722. CAN_Bridge

CAN_Bridge: stages 4 and 6 take 54% to 80% of a run. Simulation, GLB takes 4.9 s. Simulation, STEP takes 6.7 s. Simulation, STL takes 5.1 s. Simulation, OBJ takes 7.0 s. Visual, GLB takes 7.1 s. Visual, OBJ takes 8.8 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.4	1.8	0.3 ms	2.0	69 ms	0.2	0.2	4.9
Simulation, STEP	0.2	0.4	1.7	0.3 ms	2.1	1.8	0.2	0.2	6.7
Simulation, STL	0.2	0.4	1.7	0.3 ms	2.1	0.1	0.3	0.2	5.1
Simulation, OBJ	0.2	0.4	1.5	0.2 ms	2.3	2.1	0.3	0.2	7.0
Visual, GLB	0.2	0.4	1.6	0.6 ms	4.1	56 ms	0.5	0.2	7.1
Visual, OBJ	0.2	0.4	1.6	0.3 ms	4.1	1.6	0.5	0.2	8.8

Board	Repo: sufst/pcb Board: `CAN_Bridge.kicad_pcb`
Folder	isolator
Complexity	294 / 1000 (size 194, features 100)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	41, 283, 32
Triangles, simulation	459,396 in 84 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	16 MB	305 MB
STEP	76 MB	350 MB
STL	23 MB	303 MB
OBJ	46 MB	368 MB
Visual
GLB	13 MB	350 MB
OBJ	37 MB	352 MB

2723. lvbms-connector

lvbms-connector: stages 4 and 6 take 44% to 64% of a run. Simulation, GLB takes 0.9 s. Simulation, STEP takes 1.3 s. Simulation, STL takes 1.0 s. Simulation, OBJ takes 1.1 s. Visual, GLB takes 1.0 s. Visual, OBJ takes 1.1 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	70 ms	48 ms	0.2	0.1 ms	0.3	8 ms	28 ms	0.2	0.9
Simulation, STEP	85 ms	57 ms	0.2	0.1 ms	0.4	0.3	35 ms	0.2	1.3
Simulation, STL	73 ms	50 ms	0.2	0.1 ms	0.4	12 ms	27 ms	0.2	1.0
Simulation, OBJ	88 ms	56 ms	0.2	0.1 ms	0.3	0.2	28 ms	0.2	1.1
Visual, GLB	90 ms	51 ms	0.2	0.1 ms	0.4	5 ms	48 ms	0.2	1.0
Visual, OBJ	82 ms	52 ms	0.2	0.1 ms	0.4	0.1	39 ms	0.2	1.1

Board	Repo: sufst/pcb Board: `lvbms-connector.kicad_pcb`
Folder	lvbms-conn
Complexity	62 / 1000 (size 32, features 30)
KESE features	rounded, trapezoid or chamfered pads, filled zones
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	3, 0, 0
Triangles, simulation	45,170 in 17 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	1.5 MB	66 MB
STEP	5.4 MB	70 MB
STL	2.3 MB	68 MB
OBJ	4.3 MB	85 MB
Visual
GLB	931 kB	99 MB
OBJ	2.5 MB	100 MB

2724. PCB - VOLTAGE TAPS

PCB - VOLTAGE TAPS: stages 4 and 6 take 56% to 83% of a run. Simulation, GLB takes 5.9 s. Simulation, STEP takes 7.4 s. Simulation, STL takes 6.0 s. Simulation, OBJ takes 8.3 s. Visual, GLB takes 7.6 s. Visual, OBJ takes 9.4 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.6	2.9	0.2 ms	1.7	73 ms	0.2	0.2	5.9
Simulation, STEP	0.2	0.5	3.0	0.2 ms	1.7	1.5	0.3	0.2	7.4
Simulation, STL	0.2	0.6	3.0	0.2 ms	1.7	0.1	0.2	0.2	6.0
Simulation, OBJ	0.2	0.5	3.0	0.3 ms	1.7	2.5	0.2	0.2	8.3
Visual, GLB	0.2	0.6	2.9	0.2 ms	3.4	46 ms	0.3	0.2	7.6
Visual, OBJ	0.2	0.6	3.0	0.2 ms	3.4	1.7	0.3	0.3	9.4

Board	Repo: sufst/pcb Board: `PCB - VOLTAGE TAPS.kicad_pcb`
Folder	PCB - VOLTAGE TAPS
Complexity	267 / 1000 (size 122, features 145)
KESE features	slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, copper drawings, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ, copper finish
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	26, 68, 0
Triangles, simulation	459,532 in 25 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	17 MB	273 MB
STEP	94 MB	325 MB
STL	23 MB	266 MB
OBJ	49 MB	374 MB
Visual
GLB	10 MB	286 MB
OBJ	30 MB	304 MB

2725. precharge

precharge: stages 4 and 6 take 42% to 77% of a run. Simulation, GLB takes 2.5 s. Simulation, STEP takes 3.6 s. Simulation, STL takes 2.6 s. Simulation, OBJ takes 4.2 s. Visual, GLB takes 4.2 s. Visual, OBJ takes 5.4 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	0.8	0.2 ms	0.8	41 ms	0.1	0.2	2.5
Simulation, STEP	0.2	0.3	0.9	0.2 ms	0.9	1.1	0.1	0.2	3.6
Simulation, STL	0.2	0.3	0.8	0.2 ms	0.9	65 ms	0.1	0.2	2.6
Simulation, OBJ	0.2	0.3	0.9	0.2 ms	0.9	1.5	0.1	0.3	4.2
Visual, GLB	0.2	0.3	0.8	0.2 ms	2.4	36 ms	0.3	0.2	4.2
Visual, OBJ	0.2	0.3	0.8	0.2 ms	2.5	1.1	0.2	0.2	5.4

Board	Repo: sufst/pcb Board: `precharge.kicad_pcb`
Folder	precharge
Complexity	221 / 1000 (size 141, features 80)
KESE features	through vias, rounded, trapezoid or chamfered pads, curved board outline, knockout text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	40, 153, 4
Triangles, simulation	243,334 in 48 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	8.3 MB	232 MB
STEP	39 MB	246 MB
STL	12 MB	236 MB
OBJ	24 MB	224 MB
Visual
GLB	6.8 MB	223 MB
OBJ	19 MB	222 MB

2726. right-sidepanel

right-sidepanel: stages 4 and 6 take 57% to 86% of a run. Simulation, GLB takes 10 s. Simulation, STEP takes 12 s. Simulation, STL takes 9.7 s. Simulation, OBJ takes 15 s. Visual, GLB takes 13 s. Visual, OBJ takes 15 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.7	4.3	0.2 ms	3.9	0.2	0.5	0.3	10.2
Simulation, STEP	0.3	0.7	4.1	0.3 ms	3.7	2.5	0.4	0.3	12.0
Simulation, STL	0.2	0.7	4.1	0.2 ms	3.8	0.2	0.4	0.3	9.7
Simulation, OBJ	0.2	0.8	4.2	0.2 ms	4.2	4.6	0.4	0.3	14.7
Visual, GLB	0.2	0.8	4.4	0.2 ms	6.8	76 ms	0.6	0.2	13.1
Visual, OBJ	0.2	0.7	4.3	0.2 ms	6.6	2.7	0.6	0.2	15.3

Board	Repo: sufst/pcb Board: `right-sidepanel.kicad_pcb`
Folder	right-sidepanel
Complexity	230 / 1000 (size 160, features 70)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	34, 122, 155
Triangles, simulation	775,100 in 39 parts
Note	panel
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	26 MB	346 MB
STEP	96 MB	441 MB
STL	39 MB	348 MB
OBJ	78 MB	581 MB
Visual
GLB	15 MB	476 MB
OBJ	44 MB	440 MB

2727. rotary-switch

rotary-switch: stages 4 and 6 take 48% to 77% of a run. Simulation, GLB takes 2.3 s. Simulation, STEP takes 3.3 s. Simulation, STL takes 2.3 s. Simulation, OBJ takes 3.3 s. Visual, GLB takes 3.5 s. Visual, OBJ takes 4.4 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.8	0.1 ms	0.8	38 ms	0.1	0.3	2.3
Simulation, STEP	0.1	0.2	0.8	0.2 ms	0.8	1.1	0.1	0.2	3.3
Simulation, STL	0.1	0.2	0.8	0.2 ms	0.9	57 ms	0.1	0.2	2.3
Simulation, OBJ	0.1	0.2	0.8	0.2 ms	0.8	1.1	0.1	0.2	3.3
Visual, GLB	0.1	0.2	0.7	0.2 ms	1.9	31 ms	0.2	0.2	3.5
Visual, OBJ	0.1	0.2	0.8	0.2 ms	2.2	0.8	0.2	0.2	4.4

Board	Repo: sufst/pcb Board: `rotary-switch.kicad_pcb`
Folder	rotary-switch
Complexity	173 / 1000 (size 108, features 65)
KESE features	rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	18, 37, 0
Triangles, simulation	222,110 in 28 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	7.6 MB	223 MB
STEP	35 MB	239 MB
STL	11 MB	224 MB
OBJ	22 MB	224 MB
Visual
GLB	5.6 MB	224 MB
OBJ	16 MB	226 MB

2728. segment-switch

segment-switch: reading, start-up and exit take 42% to 56% of a run. Simulation, GLB takes 0.5 s. Simulation, STEP takes 0.6 s. Simulation, STL takes 0.5 s. Simulation, OBJ takes 0.5 s. Visual, GLB takes 0.6 s. Visual, OBJ takes 0.6 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	63 ms	31 ms	40 ms	0.1 ms	0.1	4 ms	9 ms	0.2	0.5
Simulation, STEP	64 ms	31 ms	40 ms	0.1 ms	0.1	0.1	10 ms	0.2	0.6
Simulation, STL	73 ms	37 ms	47 ms	0.1 ms	0.1	6 ms	10 ms	0.2	0.5
Simulation, OBJ	71 ms	32 ms	41 ms	0.1 ms	0.1	68 ms	11 ms	0.2	0.5
Visual, GLB	62 ms	31 ms	44 ms	0.1 ms	0.2	3 ms	27 ms	0.2	0.6
Visual, OBJ	61 ms	30 ms	41 ms	0.1 ms	0.2	65 ms	28 ms	0.2	0.6

Board	Repo: sufst/pcb Board: `segment-switch.kicad_pcb`
Folder	segment-switch
Complexity	120 / 1000 (size 65, features 55)
KESE features	rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	2, 8, 0
Triangles, simulation	16,958 in 10 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	617 kB	61 MB
STEP	2.8 MB	64 MB
STL	849 kB	61 MB
OBJ	1.7 MB	63 MB
Visual
GLB	599 kB	87 MB
OBJ	1.6 MB	89 MB

2729. 16Ch-Sensor-Hub

16Ch-Sensor-Hub: stages 4 and 6 take 52% to 83% of a run. Simulation, GLB takes 24 s. Simulation, STEP takes 31 s. Simulation, STL takes 25 s. Simulation, OBJ takes 39 s. Visual, GLB takes 44 s. Visual, OBJ takes 55 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	2.1	8.4	0.6 ms	10.7	0.4	1.0	0.2	23.7
Simulation, STEP	0.9	2.2	9.0	0.5 ms	10.6	6.8	1.1	0.3	30.9
Simulation, STL	1.0	2.3	9.0	0.6 ms	10.9	0.6	1.1	0.2	25.1
Simulation, OBJ	0.9	2.2	9.2	0.7 ms	10.9	14.3	1.1	0.3	38.8
Visual, GLB	1.0	2.5	9.7	0.7 ms	27.0	0.3	3.3	0.3	44.2
Visual, OBJ	1.1	2.6	10.2	0.6 ms	26.8	10.6	3.6	0.3	55.2

Board	Repo: sufst/pcb Board: `16Ch-Sensor-Hub.kicad_pcb`
Folder	sensor-hub
Complexity	375 / 1000 (size 250, features 125)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	170, 906, 236
Triangles, simulation	2,375,892 in 122 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	82 MB	845 MB
STEP	389 MB	1.0 GB
STL	119 MB	824 MB
OBJ	252 MB	1.6 GB
Visual
GLB	52 MB	979 MB
OBJ	159 MB	1.2 GB

2730. 8Ch-Sensor-Hub

8Ch-Sensor-Hub: stages 4 and 6 take 51% to 81% of a run. Simulation, GLB takes 18 s. Simulation, STEP takes 25 s. Simulation, STL takes 18 s. Simulation, OBJ takes 27 s. Visual, GLB takes 24 s. Visual, OBJ takes 29 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	2.1	6.0	0.5 ms	7.5	0.3	0.8	0.4	17.8
Simulation, STEP	0.8	2.0	6.3	1 ms	8.6	5.7	0.9	0.4	24.7
Simulation, STL	0.8	2.1	5.8	0.7 ms	7.8	0.6	0.8	0.3	18.1
Simulation, OBJ	0.7	1.9	6.0	0.5 ms	7.5	9.5	0.7	0.3	26.7
Visual, GLB	0.7	1.9	5.9	0.9 ms	13.6	0.2	1.6	0.3	24.1
Visual, OBJ	0.7	1.8	5.6	0.6 ms	12.8	6.4	1.5	0.2	29.0

Board	Repo: sufst/pcb Board: `8Ch-Sensor-Hub.kicad_pcb`
Folder	sensor-hub
Complexity	364 / 1000 (size 239, features 125)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	111, 527, 186
Triangles, simulation	1,586,974 in 105 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	54 MB	620 MB
STEP	219 MB	734 MB
STL	79 MB	606 MB
OBJ	163 MB	1.1 GB
Visual
GLB	35 MB	681 MB
OBJ	106 MB	810 MB

2731. ss-relay

ss-relay: stages 4 and 6 take 45% to 65% of a run. Simulation, GLB takes 0.8 s. Simulation, STEP takes 1.2 s. Simulation, STL takes 0.9 s. Simulation, OBJ takes 1.1 s. Visual, GLB takes 1.0 s. Visual, OBJ takes 1.1 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	67 ms	43 ms	0.2	0.1 ms	0.3	7 ms	27 ms	0.2	0.8
Simulation, STEP	69 ms	44 ms	0.2	0.1 ms	0.3	0.3	35 ms	0.2	1.2
Simulation, STL	87 ms	63 ms	0.2	0.1 ms	0.3	11 ms	29 ms	0.2	0.9
Simulation, OBJ	78 ms	49 ms	0.2	0.1 ms	0.4	0.2	27 ms	0.2	1.1
Visual, GLB	74 ms	46 ms	0.2	0.1 ms	0.4	6 ms	44 ms	0.2	1.0
Visual, OBJ	76 ms	47 ms	0.2	0.1 ms	0.4	0.1	48 ms	0.2	1.1

Board	Repo: sufst/pcb Board: `ss-relay.kicad_pcb`
Folder	ss-relay
Complexity	160 / 1000 (size 90, features 70)
KESE features	custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, knockout text
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	7, 21, 0
Triangles, simulation	46,626 in 18 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	1.6 MB	69 MB
STEP	7.8 MB	75 MB
STL	2.3 MB	69 MB
OBJ	4.5 MB	79 MB
Visual
GLB	1.2 MB	104 MB
OBJ	3.2 MB	107 MB

2732. tem

tem: stages 4 and 6 take 55% to 82% of a run. Simulation, GLB takes 8.4 s. Simulation, STEP takes 10 s. Simulation, STL takes 8.0 s. Simulation, OBJ takes 11 s. Visual, GLB takes 12 s. Visual, OBJ takes 14 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.7	2.6	0.5 ms	4.0	0.1	0.3	0.2	8.4
Simulation, STEP	0.3	0.7	2.4	0.4 ms	3.5	3.0	0.3	0.2	10.4
Simulation, STL	0.3	0.7	2.5	0.4 ms	3.7	0.3	0.4	0.2	8.0
Simulation, OBJ	0.3	0.6	2.4	0.5 ms	3.8	3.6	0.4	0.2	11.3
Visual, GLB	0.3	0.6	2.5	0.4 ms	7.0	0.1	0.9	0.2	11.6
Visual, OBJ	0.3	0.7	2.5	0.6 ms	6.9	3.0	0.9	0.2	14.5

Board	Repo: sufst/pcb Board: `tem.kicad_pcb`
Folder	tem
Complexity	269 / 1000 (size 224, features 45)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	103, 756, 169
Triangles, simulation	865,058 in 60 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	30 MB	485 MB
STEP	154 MB	519 MB
STL	43 MB	488 MB
OBJ	87 MB	620 MB
Visual
GLB	25 MB	696 MB
OBJ	75 MB	651 MB

2733. trc

trc: stages 4 and 6 take 54% to 81% of a run. Simulation, GLB takes 7.9 s. Simulation, STEP takes 10 s. Simulation, STL takes 7.9 s. Simulation, OBJ takes 11 s. Visual, GLB takes 11 s. Visual, OBJ takes 14 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.7	2.7	0.5 ms	3.4	0.1	0.4	0.3	7.9
Simulation, STEP	0.3	0.7	2.7	0.4 ms	3.3	2.7	0.4	0.3	10.3
Simulation, STL	0.3	0.6	2.8	0.4 ms	3.3	0.2	0.4	0.2	7.9
Simulation, OBJ	0.2	0.6	2.6	0.8 ms	3.1	3.4	0.4	0.2	10.7
Visual, GLB	0.3	0.6	2.8	0.4 ms	6.0	94 ms	0.8	0.2	10.8
Visual, OBJ	0.3	0.6	2.8	0.4 ms	6.2	2.9	0.9	0.2	13.9

Board	Repo: sufst/pcb Board: `trc.kicad_pcb`
Folder	trc
Complexity	266 / 1000 (size 166, features 100)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	56, 364, 89
Triangles, simulation	721,698 in 71 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	25 MB	370 MB
STEP	121 MB	435 MB
STL	36 MB	372 MB
OBJ	73 MB	525 MB
Visual
GLB	20 MB	529 MB
OBJ	59 MB	540 MB

2734. tsal-latching-integrated

tsal-latching-integrated: stages 4 and 6 take 50% to 81% of a run. Simulation, GLB takes 9.4 s. Simulation, STEP takes 12 s. Simulation, STL takes 9.5 s. Simulation, OBJ takes 14 s. Visual, GLB takes 14 s. Visual, OBJ takes 17 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.0	3.5	0.4 ms	3.5	0.2	0.6	0.2	9.4
Simulation, STEP	0.4	1.0	3.7	0.3 ms	3.4	3.1	0.5	0.3	12.3
Simulation, STL	0.4	0.9	3.6	0.4 ms	3.5	0.4	0.5	0.2	9.5
Simulation, OBJ	0.4	1.0	3.6	0.4 ms	3.7	5.1	0.5	0.2	14.5
Visual, GLB	0.3	1.0	3.7	0.4 ms	7.6	0.1	1.0	0.2	13.9
Visual, OBJ	0.3	1.0	3.5	0.4 ms	7.4	3.2	0.9	0.2	16.6

Board	Repo: sufst/pcb Board: `tsal-latching-integrated.kicad_pcb`
Folder	tsal-latching-integrated
Complexity	311 / 1000 (size 186, features 125)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 8 (20240108)
Parts, tracks, vias	80, 429, 62
Triangles, simulation	1,076,692 in 77 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	37 MB	461 MB
STEP	156 MB	536 MB
STL	54 MB	456 MB
OBJ	109 MB	767 MB
Visual
GLB	24 MB	661 MB
OBJ	73 MB	602 MB

2735. tsal-led

tsal-led: stages 4 and 6 take 52% to 86% of a run. Simulation, GLB takes 9.8 s. Simulation, STEP takes 11 s. Simulation, STL takes 9.7 s. Simulation, OBJ takes 14 s. Visual, GLB takes 16 s. Visual, OBJ takes 19 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.0	3.9	0.4 ms	3.8	0.1	0.5	0.2	9.8
Simulation, STEP	0.2	0.9	3.7	0.4 ms	3.7	2.0	0.5	0.2	11.3
Simulation, STL	0.2	1.0	3.7	0.4 ms	3.6	0.4	0.6	0.2	9.7
Simulation, OBJ	0.3	0.9	3.7	0.4 ms	3.8	4.8	0.6	0.3	14.3
Visual, GLB	0.2	1.0	3.6	0.4 ms	10.4	98 ms	0.7	0.2	16.3
Visual, OBJ	0.3	1.0	4.0	0.3 ms	9.5	3.0	0.7	0.2	18.8

Board	Repo: sufst/pcb Board: `tsal-led.kicad_pcb`
Folder	tsal-led
Complexity	321 / 1000 (size 191, features 130)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours
Tested	9th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	57, 85, 316
Triangles, simulation	973,862 in 36 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	33 MB	470 MB
STEP	84 MB	544 MB
STL	49 MB	492 MB
OBJ	96 MB	637 MB
Visual
GLB	18 MB	503 MB
OBJ	54 MB	515 MB

2736. vcu

vcu: stages 4 and 6 take 51% to 85% of a run. Simulation, GLB takes 31 s. Simulation, STEP takes 41 s. Simulation, STL takes 31 s. Simulation, OBJ takes 48 s. Visual, GLB takes 48 s. Visual, OBJ takes 57 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	3.1	11.9	1 ms	13.1	0.6	1.4	0.3	31.0
Simulation, STEP	0.7	3.0	12.3	0.8 ms	13.5	9.3	1.4	0.3	40.5
Simulation, STL	0.7	3.1	11.9	1 ms	12.9	1.0	1.4	0.3	31.2
Simulation, OBJ	0.7	3.1	11.5	1 ms	13.0	17.9	1.4	0.3	47.8
Visual, GLB	0.7	3.1	12.1	1 ms	28.9	0.4	2.9	0.3	48.4
Visual, OBJ	0.6	3.0	11.5	1 ms	27.6	11.2	3.3	0.3	57.4

Board	Repo: sufst/pcb Board: `vcu.kicad_pcb`
Folder	vcu
Complexity	346 / 1000 (size 266, features 80)
KESE features	through vias, rounded, trapezoid or chamfered pads, curved board outline, knockout text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	205, 1,711, 293
Triangles, simulation	3,172,496 in 345 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	109 MB	1.0 GB
STEP	459 MB	1.3 GB
STL	159 MB	1.0 GB
OBJ	338 MB	2.1 GB
Visual
GLB	70 MB	1.3 GB
OBJ	220 MB	1.5 GB

2737. LittleSixteen

LittleSixteen: stages 4 and 6 take 55% to 87% of a run. Simulation, GLB takes 2 min. Simulation, STEP takes 3 min. Simulation, STL takes 2 min. Simulation, OBJ takes 3 min. Visual, GLB takes 4 min. Visual, OBJ takes 5 min

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	5.1	10.9	64.8	2 ms	46.3	1.9	8.6	0.4	138.0
Simulation, STEP	5.0	11.0	65.9	2 ms	46.8	30.1	8.8	0.4	168.0
Simulation, STL	5.0	10.8	63.5	2 ms	47.2	5.0	8.7	0.4	140.6
Simulation, OBJ	5.3	11.1	65.7	2 ms	46.8	67.4	8.6	0.5	205.3
Visual, GLB	5.2	10.8	64.8	2 ms	134.1	1.3	11.0	0.3	227.5
Visual, OBJ	5.0	10.8	65.8	2 ms	139.1	46.5	12.3	0.4	279.9

Board	Repo: SukkoPera/LittleSixteen Board: `LittleSixteen.kicad_pcb`
Complexity	317 / 1000 (size 227, features 90)
KESE features	through vias, custom pads, drill offsets, filled zones, copper drawings, copper text, curved board outline
Tested	9th November 2026 to 10th November 2026
Copper layers	2
File format	KiCad 5 (20171130)
Parts, tracks, vias	339, 5,995, 622
Triangles, simulation	11,236,742 in 387 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	381 MB	3.3 GB
STEP	1.9 GB	4.2 GB
STL	562 MB	3.5 GB
OBJ	1.2 GB	7.1 GB
Visual
GLB	277 MB	4.2 GB
OBJ	887 MB	5.4 GB

2738. Raemixx500

Raemixx500: stages 4 and 6 take 57% to 88% of a run. Simulation, GLB takes 3 min. Simulation, STEP takes 4 min. Simulation, STL takes 3 min. Simulation, OBJ takes 5 min. Visual, GLB takes 5 min. Visual, OBJ takes 6 min

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.8	14.6	101.2	3 ms	65.9	2.7	12.5	0.5	200.1
Simulation, STEP	3.2	14.4	96.3	4 ms	65.3	42.3	12.7	0.5	234.7
Simulation, STL	3.0	16.0	99.5	5 ms	66.1	6.5	12.4	0.5	204.0
Simulation, OBJ	3.1	14.7	94.5	3 ms	65.9	89.4	12.1	0.5	280.3
Visual, GLB	3.3	14.6	96.4	3 ms	192.1	2.1	19.6	0.4	328.5
Visual, OBJ	2.8	14.5	95.5	5 ms	188.1	57.8	18.5	0.4	377.6

Board	Repo: sukkopera/raemixx500 Board: `Raemixx500.kicad_pcb`
Complexity	362 / 1000 (size 277, features 85)
KESE features	through vias, slotted holes, rounded, trapezoid or chamfered pads, drill offsets, filled zones, copper text, curved board outline
Tested	9th November 2026
Copper layers	2
File format	KiCad 5 (20171130)
Parts, tracks, vias	362, 11,735, 902
Triangles, simulation	15,351,150 in 483 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	519 MB	4.5 GB
STEP	2.6 GB	5.6 GB
STL	768 MB	4.5 GB
OBJ	1.7 GB	9.5 GB
Visual
GLB	369 MB	5.5 GB
OBJ	1.2 GB	7.3 GB

2739. launch-heavy

launch-heavy: stages 4 and 6 take 49% to 78% of a run. Simulation, GLB takes 13 s. Simulation, STEP takes 17 s. Simulation, STL takes 15 s. Simulation, OBJ takes 19 s. Visual, GLB takes 18 s. Visual, OBJ takes 23 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	2.0	4.2	0.4 ms	5.5	0.2	0.6	0.3	13.3
Simulation, STEP	0.5	1.8	4.1	0.7 ms	5.4	4.7	0.7	0.3	17.5
Simulation, STL	0.5	2.0	4.7	0.5 ms	5.9	0.4	0.7	0.3	14.7
Simulation, OBJ	0.6	1.8	4.1	0.2 ms	5.3	6.4	0.7	0.3	19.2
Visual, GLB	0.5	1.7	4.0	0.3 ms	10.3	0.2	1.4	0.3	18.3
Visual, OBJ	0.5	1.7	3.8	0.3 ms	9.4	5.6	1.4	0.3	22.7

Board	Repo: system76/launch Board: `launch-heavy.kicad_pcb`
Folder	pcb-heavy
Complexity	285 / 1000 (size 175, features 110)
KESE features	through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper text, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 6 (20211014)
Parts, tracks, vias	64, 390, 202
Triangles, simulation	1,013,844 in 68 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	36 MB	482 MB
STEP	188 MB	615 MB
STL	51 MB	508 MB
OBJ	105 MB	716 MB
Visual
GLB	30 MB	715 MB
OBJ	91 MB	692 MB

2740. launch-iso

launch-iso: stages 4 and 6 take 48% to 79% of a run. Simulation, GLB takes 60 s. Simulation, STEP takes 76 s. Simulation, STL takes 59 s. Simulation, OBJ takes 88 s. Visual, GLB takes 2 min. Visual, OBJ takes 2 min

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.1	9.9	21.6	2 ms	22.5	1.1	2.5	0.3	60.2
Simulation, STEP	2.2	9.8	21.8	0.9 ms	22.9	16.0	2.6	0.4	75.6
Simulation, STL	2.1	9.3	20.5	2 ms	21.8	2.3	2.5	0.4	58.9
Simulation, OBJ	2.2	9.2	20.0	2 ms	22.2	31.5	2.4	0.4	87.9
Visual, GLB	2.1	9.5	20.5	2 ms	60.1	0.8	8.1	0.4	101.5
Visual, OBJ	2.1	9.6	20.2	2 ms	59.0	19.8	8.3	0.4	119.4

Board	Repo: system76/launch Board: `launch-iso.kicad_pcb`
Folder	pcb-iso
Complexity	430 / 1000 (size 285, features 145)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 6 (20211014)
Parts, tracks, vias	361, 3,521, 723
Triangles, simulation	5,928,940 in 419 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	204 MB	1.8 GB
STEP	984 MB	2.3 GB
STL	296 MB	1.9 GB
OBJ	644 MB	3.9 GB
Visual
GLB	134 MB	2.1 GB
OBJ	426 MB	2.9 GB

2741. launch-lite-iso

launch-lite-iso: stages 4 and 6 take 43% to 75% of a run. Simulation, GLB takes 29 s. Simulation, STEP takes 36 s. Simulation, STL takes 29 s. Simulation, OBJ takes 46 s. Visual, GLB takes 47 s. Visual, OBJ takes 60 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.5	5.5	8.9	0.9 ms	10.8	0.5	1.1	0.3	28.6
Simulation, STEP	1.4	5.4	8.7	0.9 ms	10.8	8.2	1.0	0.3	35.7
Simulation, STL	1.4	5.3	8.9	1.0 ms	10.7	1.0	1.1	0.3	28.6
Simulation, OBJ	1.3	5.5	9.1	1 ms	10.8	18.0	1.2	0.3	46.2
Visual, GLB	1.5	5.5	9.0	1 ms	26.6	0.4	4.3	0.3	47.4
Visual, OBJ	1.5	5.6	9.1	1 ms	26.6	12.4	4.2	0.3	59.7

Board	Repo: system76/launch Board: `launch-lite-iso.kicad_pcb`
Folder	pcb-lite-iso
Complexity	403 / 1000 (size 258, features 145)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 6 (20211014)
Parts, tracks, vias	214, 1,358, 307
Triangles, simulation	3,028,702 in 226 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	104 MB	1.1 GB
STEP	436 MB	1.3 GB
STL	151 MB	1.1 GB
OBJ	326 MB	2.0 GB
Visual
GLB	70 MB	1.2 GB
OBJ	218 MB	1.6 GB

2742. launch-lite

launch-lite: stages 4 and 6 take 41% to 73% of a run. Simulation, GLB takes 32 s. Simulation, STEP takes 41 s. Simulation, STL takes 34 s. Simulation, OBJ takes 52 s. Visual, GLB takes 53 s. Visual, OBJ takes 65 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.5	6.2	8.9	1 ms	12.6	0.6	1.2	0.4	32.4
Simulation, STEP	2.3	6.1	8.8	1 ms	12.4	9.6	1.1	0.4	40.7
Simulation, STL	2.2	6.3	9.1	1 ms	12.8	1.5	1.3	0.3	33.5
Simulation, OBJ	2.3	6.4	9.0	2 ms	12.4	20.3	1.3	0.4	52.1
Visual, GLB	2.5	6.4	9.0	0.9 ms	29.5	0.4	4.5	0.4	52.7
Visual, OBJ	2.4	6.3	9.1	1 ms	28.5	12.5	5.5	0.4	64.7

Board	Repo: system76/launch Board: `launch-lite.kicad_pcb`
Folder	pcb-lite
Complexity	388 / 1000 (size 258, features 130)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 6 (20211014)
Parts, tracks, vias	211, 1,375, 292
Triangles, simulation	3,642,802 in 223 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	126 MB	1.3 GB
STEP	668 MB	1.6 GB
STL	182 MB	1.3 GB
OBJ	395 MB	2.5 GB
Visual
GLB	74 MB	1.3 GB
OBJ	229 MB	1.7 GB

2743. launch

launch: stages 4 and 6 take 45% to 80% of a run. Simulation, GLB takes 65 s. Simulation, STEP takes 81 s. Simulation, STL takes 66 s. Simulation, OBJ takes 2 min. Visual, GLB takes 2 min. Visual, OBJ takes 2 min

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.1	11.2	24.4	1 ms	23.3	1.1	2.8	0.3	65.4
Simulation, STEP	2.1	11.0	23.8	2 ms	23.5	17.5	2.9	0.3	81.0
Simulation, STL	2.2	11.0	24.1	2 ms	23.0	2.5	2.9	0.4	65.9
Simulation, OBJ	2.1	11.0	24.0	2 ms	23.1	40.7	2.9	0.4	104.2
Visual, GLB	2.2	10.9	23.7	2 ms	63.2	0.9	7.8	0.3	109.1
Visual, OBJ	2.3	11.0	23.7	2 ms	62.6	25.9	7.2	0.3	133.0

Board	Repo: system76/launch Board: `launch.kicad_pcb`
Folder	pcb
Complexity	393 / 1000 (size 288, features 105)
KESE features	through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 7 (20221018)
Parts, tracks, vias	371, 3,494, 959
Triangles, simulation	7,010,812 in 414 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	239 MB	2.4 GB
STEP	1.0 GB	2.8 GB
STL	351 MB	2.3 GB
OBJ	758 MB	4.5 GB
Visual
GLB	160 MB	2.6 GB
OBJ	511 MB	3.3 GB

2744. nebula-io

nebula-io: stages 4 and 6 take 44% to 73% of a run. Simulation, GLB takes 1.5 s. Simulation, STEP takes 2.5 s. Simulation, STL takes 1.5 s. Simulation, OBJ takes 2.1 s. Visual, GLB takes 2.3 s. Visual, OBJ takes 2.5 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	93 ms	0.2	0.5	0.2 ms	0.5	17 ms	58 ms	0.2	1.5
Simulation, STEP	86 ms	0.2	0.5	0.1 ms	0.6	0.9	60 ms	0.2	2.5
Simulation, STL	0.1	0.2	0.5	0.2 ms	0.5	24 ms	55 ms	0.2	1.5
Simulation, OBJ	94 ms	0.2	0.5	0.1 ms	0.5	0.6	49 ms	0.3	2.1
Visual, GLB	82 ms	0.2	0.5	0.1 ms	1.2	16 ms	0.1	0.2	2.3
Visual, OBJ	86 ms	0.2	0.5	0.1 ms	1.1	0.3	95 ms	0.2	2.5

Board	Repo: system76/thelio-io-hardware Board: `nebula-io.kicad_pcb`
Folder	pcb-nebula-io
Complexity	176 / 1000 (size 96, features 80)
KESE features	rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	8, 28, 0
Triangles, simulation	104,494 in 18 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	3.7 MB	183 MB
STEP	19 MB	187 MB
STL	5.2 MB	180 MB
OBJ	10 MB	182 MB
Visual
GLB	2.4 MB	154 MB
OBJ	6.6 MB	153 MB

2745. thelio-io-sata

thelio-io-sata: stages 4 and 6 take 43% to 78% of a run. Simulation, GLB takes 3.1 s. Simulation, STEP takes 4.4 s. Simulation, STL takes 3.4 s. Simulation, OBJ takes 4.8 s. Visual, GLB takes 4.8 s. Visual, OBJ takes 5.7 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.5	0.9	0.3 ms	1.1	51 ms	0.2	0.2	3.1
Simulation, STEP	0.1	0.5	0.9	0.2 ms	1.3	1.2	0.2	0.2	4.4
Simulation, STL	0.2	0.5	1.0	0.2 ms	1.2	85 ms	0.2	0.3	3.4
Simulation, OBJ	0.1	0.5	0.9	0.2 ms	1.1	1.7	0.2	0.2	4.8
Visual, GLB	0.1	0.5	1.0	0.2 ms	2.7	33 ms	0.2	0.2	4.8
Visual, OBJ	0.1	0.5	1.0	0.3 ms	2.6	1.0	0.2	0.2	5.7

Board	Repo: system76/thelio-io-hardware Board: `thelio-io-sata.kicad_pcb`
Folder	pcb-thelio-io-sata
Complexity	244 / 1000 (size 149, features 95)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 7 (20221018)
Parts, tracks, vias	9, 61, 65
Triangles, simulation	326,692 in 31 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	11 MB	239 MB
STEP	35 MB	275 MB
STL	16 MB	239 MB
OBJ	33 MB	249 MB
Visual
GLB	6.6 MB	236 MB
OBJ	20 MB	234 MB

2746. thelio-io

thelio-io: stages 4 and 6 take 50% to 82% of a run. Simulation, GLB takes 12 s. Simulation, STEP takes 16 s. Simulation, STL takes 13 s. Simulation, OBJ takes 19 s. Visual, GLB takes 18 s. Visual, OBJ takes 21 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.5	5.3	0.3 ms	4.1	0.2	0.5	0.4	12.5
Simulation, STEP	0.4	1.5	5.4	0.5 ms	4.1	3.4	0.6	0.3	15.7
Simulation, STL	0.5	1.5	5.2	0.3 ms	4.0	0.3	0.7	0.3	12.6
Simulation, OBJ	0.7	1.5	5.5	0.4 ms	4.0	6.5	0.7	0.2	19.1
Visual, GLB	0.4	1.6	5.8	0.6 ms	9.0	0.1	1.0	0.3	18.1
Visual, OBJ	0.4	1.5	5.5	1.0 ms	8.7	3.8	1.0	0.3	21.2

Board	Repo: system76/thelio-io-hardware Board: `thelio-io.kicad_pcb`
Folder	pcb-thelio-io
Complexity	326 / 1000 (size 231, features 95)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 7 (20221018)
Parts, tracks, vias	77, 543, 93
Triangles, simulation	1,048,850 in 86 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	37 MB	452 MB
STEP	169 MB	540 MB
STL	52 MB	453 MB
OBJ	108 MB	761 MB
Visual
GLB	22 MB	583 MB
OBJ	67 MB	579 MB

2747. virgo-keyboard-test

virgo-keyboard-test: stages 4 and 6 take 51% to 79% of a run. Simulation, GLB takes 56 s. Simulation, STEP takes 71 s. Simulation, STL takes 57 s. Simulation, OBJ takes 83 s. Visual, GLB takes 88 s. Visual, OBJ takes 2 min

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.6	8.4	22.4	1 ms	19.7	1.0	2.7	0.3	56.1
Simulation, STEP	1.7	8.5	24.1	1 ms	20.0	14.1	2.6	0.4	71.4
Simulation, STL	1.6	8.4	22.7	0.9 ms	19.6	1.9	2.5	0.4	57.1
Simulation, OBJ	1.6	8.0	22.5	1 ms	20.1	28.6	2.4	0.3	83.5
Visual, GLB	1.7	8.7	23.1	2 ms	46.3	0.6	7.3	0.3	88.1
Visual, OBJ	1.6	7.8	21.2	0.9 ms	46.3	17.7	7.4	0.3	102.3

Board	Repo: system76/virgo Board: `virgo-keyboard-test.kicad_pcb`
Folder	pcb-keyboard
Complexity	390 / 1000 (size 265, features 125)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ, copper finish
Tested	9th November 2026
Copper layers	4
File format	KiCad 7 (20221018)
Parts, tracks, vias	261, 1,802, 424
Triangles, simulation	5,464,548 in 257 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	187 MB	1.6 GB
STEP	835 MB	2.1 GB
STL	273 MB	1.7 GB
OBJ	588 MB	3.6 GB
Visual
GLB	124 MB	2.0 GB
OBJ	395 MB	2.6 GB

2748. virgo-rpl-uph

virgo-rpl-uph: stages 4 and 6 take 58% to 82% of a run. Simulation, GLB takes 2 min. Simulation, STEP takes 2 min. Simulation, STL takes 2 min. Simulation, OBJ takes 3 min. Visual, GLB takes 2 min. Visual, OBJ takes 3 min

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.5	16.3	54.6	2 ms	37.8	1.3	3.3	0.4	115.3
Simulation, STEP	2.1	16.6	53.0	3 ms	38.4	24.7	3.3	0.4	138.5
Simulation, STL	2.2	17.1	50.8	3 ms	38.7	2.8	3.4	0.4	115.5
Simulation, OBJ	1.8	16.1	50.9	5 ms	38.8	42.1	3.5	0.4	153.7
Visual, GLB	1.9	15.6	52.0	3 ms	67.3	0.6	7.8	0.3	145.6
Visual, OBJ	1.9	15.3	50.7	3 ms	64.4	18.4	7.8	0.3	158.8

Board	Repo: system76/virgo Board: `virgo-rpl-uph.kicad_pcb`
Folder	pcb-rpl-uph
Complexity	429 / 1000 (size 309, features 120)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	10
File format	KiCad 7 (20221018)
Parts, tracks, vias	591, 434, 292
Triangles, simulation	7,085,540 in 1533 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	242 MB	2.7 GB
STEP	1.4 GB	3.4 GB
STL	354 MB	2.6 GB
OBJ	778 MB	4.7 GB
Visual
GLB	126 MB	2.4 GB
OBJ	404 MB	2.7 GB

2749. ZX80_Board

ZX80_Board: stages 4 and 6 take 62% to 86% of a run. Simulation, GLB takes 43 s. Simulation, STEP takes 51 s. Simulation, STL takes 43 s. Simulation, OBJ takes 57 s. Visual, GLB takes 58 s. Visual, OBJ takes 60 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.6	4.8	20.6	0.8 ms	14.0	0.4	1.1	0.3	43.0
Simulation, STEP	1.6	5.1	20.9	1 ms	14.5	7.3	1.1	0.3	50.8
Simulation, STL	1.6	4.3	20.1	0.9 ms	14.2	1.0	1.2	0.3	42.6
Simulation, OBJ	1.5	5.0	20.5	1 ms	14.4	13.7	1.2	0.3	56.5
Visual, GLB	1.7	4.8	20.7	1 ms	29.4	0.1	1.3	0.3	58.3
Visual, OBJ	1.4	4.9	19.3	3 ms	28.2	4.3	1.5	0.3	59.9

Board	Repo: TankedThomas/ZX80 Board: `ZX80_Board.kicad_pcb`
Complexity	243 / 1000 (size 178, features 65)
KESE features	through vias, filled zones, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	124, 703, 30
Triangles, simulation	2,814,382 in 144 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	99 MB	886 MB
STEP	519 MB	1.2 GB
STL	141 MB	907 MB
OBJ	306 MB	1.9 GB
Visual
GLB	32 MB	836 MB
OBJ	95 MB	835 MB

2750. ZX80_Board_Foil

ZX80_Board_Foil: stages 4 and 6 take 41% to 72% of a run. Simulation, GLB takes 11 s. Simulation, STEP takes 15 s. Simulation, STL takes 11 s. Simulation, OBJ takes 18 s. Visual, GLB takes 12 s. Visual, OBJ takes 14 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.1	1.3	1.8	0.9 ms	5.5	0.2	0.7	0.3	10.9
Simulation, STEP	1.1	1.3	1.8	0.9 ms	5.4	4.6	0.7	0.3	15.2
Simulation, STL	1.1	1.4	1.9	0.7 ms	5.7	0.3	0.7	0.2	11.1
Simulation, OBJ	1.2	1.3	1.7	0.7 ms	5.6	7.0	0.7	0.2	17.8
Visual, GLB	1.1	1.5	1.8	0.9 ms	6.9	64 ms	0.5	0.2	12.1
Visual, OBJ	1.1	1.3	1.8	1.0 ms	7.0	2.1	0.5	0.2	13.9

Board	Repo: TankedThomas/ZX80 Board: `ZX80_Board_Foil.kicad_pcb`
Complexity	37 / 1000 (size 17, features 20)
KESE features	filled zones
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	0, 0, 0
Triangles, simulation	1,185,784 in 8 parts
Note	no components
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	45 MB	600 MB
STEP	359 MB	753 MB
STL	59 MB	605 MB
OBJ	134 MB	912 MB
Visual
GLB	15 MB	463 MB
OBJ	44 MB	449 MB

2751. TAPRX-888

TAPRX-888: stages 4 and 6 take 47% to 81% of a run. Simulation, GLB takes 40 s. Simulation, STEP takes 49 s. Simulation, STL takes 41 s. Simulation, OBJ takes 67 s. Visual, GLB takes 59 s. Visual, OBJ takes 73 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.2	5.0	15.8	0.5 ms	15.1	0.7	2.2	0.3	40.3
Simulation, STEP	1.2	5.2	15.8	0.6 ms	14.9	9.2	2.0	0.3	48.5
Simulation, STL	1.1	4.8	15.7	0.6 ms	15.3	1.5	2.3	0.3	41.1
Simulation, OBJ	1.1	5.2	16.2	0.6 ms	15.7	26.4	2.3	0.3	67.1
Visual, GLB	1.1	5.3	16.5	0.6 ms	31.3	0.4	4.0	0.3	58.9
Visual, OBJ	1.1	5.0	15.7	0.6 ms	31.3	14.2	5.0	0.2	72.7

Board	Repo: TAPR/TAPRx888 Board: `TAPRX-888.kicad_pcb`
Complexity	440 / 1000 (size 290, features 150)
KESE features	through vias, microvias, rounded, trapezoid or chamfered pads, filled zones, knockout text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours
Tested	9th November 2026
Copper layers	6
File format	KiCad 10 (20260206)
Parts, tracks, vias	197, 1,782, 681
Triangles, simulation	4,663,198 in 225 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	155 MB	1.6 GB
STEP	524 MB	1.8 GB
STL	233 MB	1.6 GB
OBJ	496 MB	3.0 GB
Visual
GLB	86 MB	1.5 GB
OBJ	277 MB	1.9 GB

2752. DDR4_SoC

DDR4_SoC: stages 4 and 6 take 49% to 80% of a run. Simulation, GLB takes 35 s. Simulation, STEP takes 45 s. Simulation, STL takes 37 s. Simulation, OBJ takes 57 s. Visual, GLB takes 59 s. Visual, OBJ takes 74 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	4.5	10.1	1 ms	17.1	0.7	1.8	0.3	35.3
Simulation, STEP	0.8	4.4	10.3	1 ms	16.9	10.2	1.8	0.3	44.6
Simulation, STL	0.8	4.6	10.3	1 ms	17.4	1.7	2.0	0.3	37.0
Simulation, OBJ	0.9	4.5	10.6	1 ms	17.4	21.6	2.2	0.3	57.4
Visual, GLB	0.9	4.9	10.6	2 ms	36.4	0.5	5.5	0.3	59.0
Visual, OBJ	0.8	4.7	10.9	1 ms	36.7	14.3	6.1	0.3	74.0

Board	Repo: tatakimon/lpddr4_w_allwinner_soc Board: `DDR4_SoC.kicad_pcb`
Folder	DDR4_SoC
Complexity	442 / 1000 (size 307, features 135)
KESE features	through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	6
File format	KiCad 9 (20241229)
Parts, tracks, vias	152, 6,210, 715
Triangles, simulation	4,953,774 in 335 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	164 MB	1.5 GB
STEP	584 MB	2.0 GB
STL	248 MB	1.4 GB
OBJ	519 MB	3.1 GB
Visual
GLB	102 MB	1.7 GB
OBJ	329 MB	2.2 GB

2753. OpenInverter_20b

OpenInverter_20b: stages 4 and 6 take 51% to 84% of a run. Simulation, GLB takes 29 s. Simulation, STEP takes 35 s. Simulation, STL takes 29 s. Simulation, OBJ takes 45 s. Visual, GLB takes 39 s. Visual, OBJ takes 47 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	2.8	12.0	0.7 ms	11.0	0.5	1.7	0.3	28.8
Simulation, STEP	0.5	2.8	11.6	0.6 ms	10.8	7.6	1.5	0.3	35.1
Simulation, STL	0.5	2.8	11.9	0.8 ms	11.3	0.8	1.5	0.3	29.2
Simulation, OBJ	0.5	2.8	11.8	0.6 ms	11.1	16.5	1.6	0.3	44.5
Visual, GLB	0.5	2.9	12.1	0.7 ms	20.3	0.2	2.2	0.3	38.6
Visual, OBJ	0.5	2.6	12.0	0.7 ms	20.8	8.6	2.3	0.3	47.1

Board	Repo: teknomadix/Open_Inverter_2.0b_Kicad Board: `OpenInverter_20b.kicad_pcb`
Folder	Hardware
Complexity	223 / 1000 (size 188, features 35)
KESE features	through vias, filled zones
Tested	10th November 2026
Copper layers	4
File format	KiCad 5 (20171130)
Parts, tracks, vias	61, 744, 28
Triangles, simulation	2,691,338 in 98 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	92 MB	832 MB
STEP	405 MB	972 MB
STL	135 MB	791 MB
OBJ	284 MB	1.8 GB
Visual
GLB	49 MB	926 MB
OBJ	150 MB	1.1 GB

2754. LVPD-board

LVPD-board: stages 4 and 6 take 48% to 77% of a run. Simulation, GLB takes 1.9 s. Simulation, STEP takes 2.8 s. Simulation, STL takes 1.9 s. Simulation, OBJ takes 2.7 s. Visual, GLB takes 2.5 s. Visual, OBJ takes 2.8 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	95 ms	0.2	0.6	0.2 ms	0.7	28 ms	0.1	0.2	1.9
Simulation, STEP	91 ms	0.2	0.7	0.2 ms	0.7	0.9	0.1	0.2	2.8
Simulation, STL	97 ms	0.1	0.7	0.2 ms	0.6	36 ms	0.1	0.2	1.9
Simulation, OBJ	0.1	0.1	0.6	0.3 ms	0.7	0.8	0.1	0.2	2.7
Visual, GLB	92 ms	0.2	0.6	0.1 ms	1.3	15 ms	97 ms	0.2	2.5
Visual, OBJ	96 ms	0.1	0.6	0.1 ms	1.2	0.4	81 ms	0.2	2.8

Board	Repo: terrapin-rocket-team/srad-avionics Board: `LVPD-board.kicad_pcb`
Folder	Side_Projects / ARC / PCBs
Complexity	117 / 1000 (size 107, features 10)
KESE features	rounded, trapezoid or chamfered pads
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	7, 61, 0
Triangles, simulation	160,928 in 29 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	5.4 MB	201 MB
STEP	20 MB	209 MB
STL	8.0 MB	190 MB
OBJ	15 MB	194 MB
Visual
GLB	3.1 MB	158 MB
OBJ	8.5 MB	159 MB

2755. LVPD-board_Payload

LVPD-board_Payload: stages 4 and 6 take 52% to 82% of a run. Simulation, GLB takes 4.4 s. Simulation, STEP takes 5.5 s. Simulation, STL takes 4.1 s. Simulation, OBJ takes 6.2 s. Visual, GLB takes 5.6 s. Visual, OBJ takes 6.4 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.4	2.0	0.3 ms	1.4	62 ms	0.2	0.2	4.4
Simulation, STEP	0.1	0.4	1.8	0.3 ms	1.4	1.3	0.2	0.2	5.5
Simulation, STL	0.1	0.4	1.7	0.3 ms	1.4	0.1	0.2	0.2	4.1
Simulation, OBJ	0.1	0.4	1.8	0.5 ms	1.4	2.0	0.2	0.2	6.2
Visual, GLB	0.1	0.4	1.8	0.3 ms	2.7	33 ms	0.3	0.2	5.6
Visual, OBJ	0.1	0.4	1.8	0.3 ms	2.6	1.1	0.2	0.2	6.4

Board	Repo: terrapin-rocket-team/srad-avionics Board: `LVPD-board_Payload.kicad_pcb`
Folder	Side_Projects / ARC / PCBs / LVPD-board_Payload
Complexity	145 / 1000 (size 120, features 25)
KESE features	through vias, rounded, trapezoid or chamfered pads
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	10, 102, 2
Triangles, simulation	412,926 in 66 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	14 MB	257 MB
STEP	51 MB	299 MB
STL	21 MB	264 MB
OBJ	41 MB	323 MB
Visual
GLB	7.8 MB	277 MB
OBJ	23 MB	280 MB

2756. LVPD-board_v2

LVPD-board_v2: stages 4 and 6 take 51% to 82% of a run. Simulation, GLB takes 4.5 s. Simulation, STEP takes 6.1 s. Simulation, STL takes 4.6 s. Simulation, OBJ takes 6.6 s. Visual, GLB takes 6.5 s. Visual, OBJ takes 7.6 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.4	1.9	0.3 ms	1.5	89 ms	0.3	0.3	4.5
Simulation, STEP	0.1	0.4	2.1	0.4 ms	1.5	1.5	0.3	0.3	6.1
Simulation, STL	0.1	0.4	2.0	0.5 ms	1.4	0.1	0.3	0.2	4.6
Simulation, OBJ	0.1	0.4	1.9	0.3 ms	1.4	2.2	0.3	0.2	6.6
Visual, GLB	0.1	0.4	1.9	0.6 ms	3.4	37 ms	0.3	0.3	6.5
Visual, OBJ	0.1	0.4	2.1	0.3 ms	3.2	1.3	0.3	0.2	7.6

Board	Repo: terrapin-rocket-team/srad-avionics Board: `LVPD-board_v2.kicad_pcb`
Folder	Side_Projects / ARC / PCBs / LVPD-board_v2
Complexity	128 / 1000 (size 118, features 10)
KESE features	rounded, trapezoid or chamfered pads
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	9, 105, 0
Triangles, simulation	394,344 in 66 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	13 MB	253 MB
STEP	49 MB	293 MB
STL	20 MB	246 MB
OBJ	39 MB	310 MB
Visual
GLB	7.8 MB	276 MB
OBJ	23 MB	281 MB

2757. charge_deployment

charge_deployment: stages 4 and 6 take 44% to 69% of a run. Simulation, GLB takes 1.2 s. Simulation, STEP takes 1.9 s. Simulation, STL takes 1.2 s. Simulation, OBJ takes 1.5 s. Visual, GLB takes 1.2 s. Visual, OBJ takes 1.4 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	30 ms	70 ms	0.3	0.1 ms	0.5	11 ms	40 ms	0.2	1.2
Simulation, STEP	27 ms	67 ms	0.3	0.1 ms	0.5	0.7	42 ms	0.2	1.9
Simulation, STL	28 ms	68 ms	0.3	0.1 ms	0.6	17 ms	56 ms	0.2	1.2
Simulation, OBJ	30 ms	72 ms	0.3	0.1 ms	0.5	0.3	57 ms	0.2	1.5
Visual, GLB	31 ms	69 ms	0.3	0.1 ms	0.5	7 ms	58 ms	0.2	1.2
Visual, OBJ	26 ms	70 ms	0.3	0.1 ms	0.5	0.2	50 ms	0.2	1.4

Board	Repo: terrapin-rocket-team/srad-avionics Board: `charge_deployment.kicad_pcb`
Folder	Side_Projects / Charge Deployment / Circuits
Complexity	119 / 1000 (size 99, features 20)
KESE features	rounded, trapezoid or chamfered pads, curved board outline
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	8, 35, 0
Triangles, simulation	58,226 in 16 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	2.0 MB	49 MB
STEP	7.6 MB	156 MB
STL	2.9 MB	52 MB
OBJ	5.5 MB	64 MB
Visual
GLB	1.1 MB	75 MB
OBJ	3.1 MB	67 MB

2758. ARCH

ARCH: stages 4 and 6 take 47% to 83% of a run. Simulation, GLB takes 7.0 s. Simulation, STEP takes 9.0 s. Simulation, STL takes 7.4 s. Simulation, OBJ takes 11 s. Visual, GLB takes 11 s. Visual, OBJ takes 14 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.7	2.6	0.4 ms	2.6	0.1	0.4	0.2	7.0
Simulation, STEP	0.3	0.7	2.7	0.3 ms	2.6	2.0	0.5	0.2	9.0
Simulation, STL	0.3	0.8	2.8	0.6 ms	2.6	0.2	0.4	0.2	7.4
Simulation, OBJ	0.3	0.7	2.6	0.4 ms	2.5	4.0	0.4	0.2	10.7
Visual, GLB	0.3	0.7	2.6	0.4 ms	6.6	77 ms	0.6	0.2	11.1
Visual, OBJ	0.3	0.7	2.6	0.4 ms	6.7	2.4	0.8	0.2	13.6

Board	Repo: terrapin-rocket-team/srad-avionics Board: `ARCH.kicad_pcb`
Folder	Spaceport / PCBs / ARCH
Complexity	306 / 1000 (size 186, features 120)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	69, 402, 90
Triangles, simulation	1,008,956 in 94 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	34 MB	436 MB
STEP	135 MB	469 MB
STL	50 MB	457 MB
OBJ	102 MB	687 MB
Visual
GLB	20 MB	505 MB
OBJ	61 MB	543 MB

2759. BatteryCharger

BatteryCharger: stages 4 and 6 take 40% to 73% of a run. Simulation, GLB takes 1.1 s. Simulation, STEP takes 1.7 s. Simulation, STL takes 1.1 s. Simulation, OBJ takes 1.4 s. Visual, GLB takes 1.5 s. Visual, OBJ takes 1.7 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	85 ms	61 ms	0.2	0.1 ms	0.5	11 ms	48 ms	0.2	1.1
Simulation, STEP	82 ms	53 ms	0.2	0.1 ms	0.5	0.7	49 ms	0.2	1.7
Simulation, STL	82 ms	61 ms	0.2	0.1 ms	0.5	19 ms	42 ms	0.2	1.1
Simulation, OBJ	84 ms	60 ms	0.2	0.1 ms	0.5	0.3	47 ms	0.2	1.4
Visual, GLB	80 ms	54 ms	0.2	0.1 ms	0.9	8 ms	54 ms	0.2	1.5
Visual, OBJ	81 ms	53 ms	0.2	0.1 ms	0.8	0.2	58 ms	0.2	1.7

Board	Repo: terrapin-rocket-team/srad-avionics Board: `BatteryCharger.kicad_pcb`
Folder	Spaceport / PCBs / BatteryCharger / BatteryCharger
Complexity	155 / 1000 (size 110, features 45)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	9, 46, 6
Triangles, simulation	72,036 in 16 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	2.5 MB	175 MB
STEP	12 MB	179 MB
STL	3.6 MB	174 MB
OBJ	6.9 MB	174 MB
Visual
GLB	1.9 MB	151 MB
OBJ	5.1 MB	151 MB

2760. Blue Raven Extension

Blue Raven Extension: stages 4 and 6 take 42% to 71% of a run. Simulation, GLB takes 1.7 s. Simulation, STEP takes 2.6 s. Simulation, STL takes 1.7 s. Simulation, OBJ takes 2.3 s. Visual, GLB takes 2.3 s. Visual, OBJ takes 2.9 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.2	0.5	0.3 ms	0.6	21 ms	60 ms	0.2	1.7
Simulation, STEP	0.2	0.2	0.5	0.1 ms	0.6	0.9	64 ms	0.2	2.6
Simulation, STL	0.1	0.2	0.5	0.2 ms	0.6	33 ms	67 ms	0.2	1.7
Simulation, OBJ	0.1	0.2	0.5	0.1 ms	0.5	0.6	69 ms	0.2	2.3
Visual, GLB	0.2	0.2	0.4	0.1 ms	1.2	15 ms	0.1	0.2	2.3
Visual, OBJ	0.2	0.2	0.5	0.2 ms	1.2	0.5	0.1	0.2	2.9

Board	Repo: terrapin-rocket-team/srad-avionics Board: `Blue Raven Extension.kicad_pcb`
Folder	Spaceport / PCBs / Blue Raven Extension
Complexity	147 / 1000 (size 87, features 60)
KESE features	filled zones, curved board outline, knockout text, TrueType text
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	3, 29, 0
Triangles, simulation	129,722 in 18 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	4.4 MB	191 MB
STEP	20 MB	199 MB
STL	6.5 MB	191 MB
OBJ	13 MB	187 MB
Visual
GLB	3.3 MB	158 MB
OBJ	9.1 MB	160 MB

2761. dipole-breakout

dipole-breakout: stages 4 and 6 take 38% to 58% of a run. Simulation, GLB takes 0.6 s. Simulation, STEP takes 0.7 s. Simulation, STL takes 0.6 s. Simulation, OBJ takes 0.8 s. Visual, GLB takes 0.8 s. Visual, OBJ takes 0.8 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	12 ms	36 ms	83 ms	0.1 ms	0.2	5 ms	19 ms	0.2	0.6
Simulation, STEP	20 ms	35 ms	83 ms	0.1 ms	0.2	0.1	20 ms	0.2	0.7
Simulation, STL	16 ms	34 ms	0.1	0.2 ms	0.2	7 ms	21 ms	0.2	0.6
Simulation, OBJ	12 ms	32 ms	95 ms	0.1 ms	0.2	0.1	27 ms	0.3	0.8
Visual, GLB	14 ms	34 ms	78 ms	0.1 ms	0.4	6 ms	46 ms	0.2	0.8
Visual, OBJ	16 ms	39 ms	81 ms	0.1 ms	0.3	50 ms	35 ms	0.2	0.8

Board	Repo: terrapin-rocket-team/srad-avionics Board: `dipole-breakout.kicad_pcb`
Folder	Spaceport / PCBs / dipole-breakout
Complexity	135 / 1000 (size 80, features 55)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	3, 12, 2
Triangles, simulation	14,840 in 12 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	545 kB	41 MB
STEP	1.8 MB	42 MB
STL	743 kB	42 MB
OBJ	1.4 MB	44 MB
Visual
GLB	320 kB	55 MB
OBJ	809 kB	60 MB

2762. flight-computer

flight-computer: stages 4 and 6 take 52% to 82% of a run. Simulation, GLB takes 13 s. Simulation, STEP takes 16 s. Simulation, STL takes 13 s. Simulation, OBJ takes 19 s. Visual, GLB takes 21 s. Visual, OBJ takes 25 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.5	5.2	0.6 ms	4.5	0.2	0.6	0.2	12.8
Simulation, STEP	0.5	1.3	5.1	0.7 ms	4.7	3.7	0.6	0.2	16.2
Simulation, STL	0.4	1.4	5.1	0.6 ms	4.7	0.4	0.7	0.2	12.9
Simulation, OBJ	0.5	1.4	5.3	0.6 ms	4.7	6.5	0.7	0.2	19.3
Visual, GLB	0.5	1.4	5.3	0.6 ms	11.7	0.2	1.2	0.2	20.5
Visual, OBJ	0.4	1.4	5.4	0.5 ms	12.0	4.5	1.4	0.2	25.4

Board	Repo: terrapin-rocket-team/srad-avionics Board: `flight-computer.kicad_pcb`
Folder	Spaceport / PCBs / flight-computer / Alternate layout-2025-2026
Complexity	400 / 1000 (size 250, features 150)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 10 (20260206)
Parts, tracks, vias	96, 737, 135
Triangles, simulation	1,549,962 in 145 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	54 MB	581 MB
STEP	247 MB	692 MB
STL	78 MB	581 MB
OBJ	162 MB	1.1 GB
Visual
GLB	36 MB	770 MB
OBJ	109 MB	786 MB

2763. flight-computer

flight-computer: stages 4 and 6 take 49% to 84% of a run. Simulation, GLB takes 13 s. Simulation, STEP takes 16 s. Simulation, STL takes 13 s. Simulation, OBJ takes 20 s. Visual, GLB takes 21 s. Visual, OBJ takes 26 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.4	5.3	0.5 ms	5.0	0.2	0.6	0.2	13.4
Simulation, STEP	0.4	1.4	5.1	0.8 ms	4.8	3.8	0.7	0.2	16.3
Simulation, STL	0.5	1.4	4.9	0.6 ms	4.8	0.5	0.6	0.3	13.0
Simulation, OBJ	0.4	1.4	5.1	0.5 ms	4.8	7.6	0.6	0.2	20.1
Visual, GLB	0.5	1.4	5.2	0.7 ms	13.0	0.2	1.2	0.2	21.5
Visual, OBJ	0.5	1.3	5.2	0.6 ms	11.9	5.1	1.3	0.2	25.5

Board	Repo: terrapin-rocket-team/srad-avionics Board: `flight-computer.kicad_pcb`
Folder	Spaceport / PCBs / flight-computer / flight-computer-2025-2026
Complexity	376 / 1000 (size 256, features 120)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	117, 937, 169
Triangles, simulation	1,443,250 in 215 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	50 MB	546 MB
STEP	213 MB	626 MB
STL	72 MB	544 MB
OBJ	149 MB	992 MB
Visual
GLB	32 MB	691 MB
OBJ	97 MB	753 MB

2764. mcu-board v2

mcu-board v2: stages 4 and 6 take 49% to 80% of a run. Simulation, GLB takes 3.8 s. Simulation, STEP takes 5.0 s. Simulation, STL takes 3.8 s. Simulation, OBJ takes 5.6 s. Visual, GLB takes 5.8 s. Visual, OBJ takes 6.7 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.3	1.6	1 ms	1.3	65 ms	0.2	0.2	3.8
Simulation, STEP	0.1	0.4	1.6	0.3 ms	1.2	1.4	0.2	0.2	5.0
Simulation, STL	0.1	0.3	1.5	0.2 ms	1.2	0.1	0.2	0.2	3.8
Simulation, OBJ	0.1	0.3	1.6	0.4 ms	1.2	2.0	0.2	0.2	5.6
Visual, GLB	0.1	0.4	1.5	0.3 ms	3.2	44 ms	0.4	0.3	5.8
Visual, OBJ	0.1	0.3	1.5	0.3 ms	3.0	1.2	0.4	0.2	6.7

Board	Repo: terrapin-rocket-team/srad-avionics Board: `mcu-board v2.kicad_pcb`
Folder	Spaceport / PCBs / Gerbers / Teensy v3.0
Complexity	159 / 1000 (size 114, features 45)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	12, 61, 2
Triangles, simulation	381,418 in 60 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	12 MB	254 MB
STEP	50 MB	292 MB
STL	19 MB	257 MB
OBJ	38 MB	303 MB
Visual
GLB	7.9 MB	278 MB
OBJ	23 MB	272 MB

2765. SensorBoardNoMCU

SensorBoardNoMCU: stages 4 and 6 take 51% to 77% of a run. Simulation, GLB takes 3.6 s. Simulation, STEP takes 4.8 s. Simulation, STL takes 3.5 s. Simulation, OBJ takes 4.8 s. Visual, GLB takes 4.6 s. Visual, OBJ takes 5.7 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	1.3	0.3 ms	1.4	46 ms	0.2	0.2	3.6
Simulation, STEP	0.2	0.3	1.2	0.2 ms	1.5	1.3	0.2	0.2	4.8
Simulation, STL	0.2	0.3	1.1	0.2 ms	1.5	74 ms	0.2	0.3	3.5
Simulation, OBJ	0.2	0.4	1.1	0.2 ms	1.3	1.4	0.2	0.2	4.8
Visual, GLB	0.2	0.3	1.3	0.4 ms	2.3	36 ms	0.3	0.2	4.6
Visual, OBJ	0.2	0.3	1.2	0.3 ms	2.4	1.2	0.2	0.2	5.7

Board	Repo: terrapin-rocket-team/srad-avionics Board: `SensorBoardNoMCU.kicad_pcb`
Folder	Spaceport / PCBs / Gerbers / Teensy v3.0
Complexity	266 / 1000 (size 151, features 115)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	25, 221, 67
Triangles, simulation	259,862 in 37 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	9.0 MB	239 MB
STEP	39 MB	271 MB
STL	13 MB	241 MB
OBJ	26 MB	242 MB
Visual
GLB	7.5 MB	250 MB
OBJ	22 MB	253 MB

2766. Ground Receiver v2

Ground Receiver v2: stages 4 and 6 take 51% to 81% of a run. Simulation, GLB takes 5.3 s. Simulation, STEP takes 7.2 s. Simulation, STL takes 5.8 s. Simulation, OBJ takes 8.1 s. Visual, GLB takes 7.3 s. Visual, OBJ takes 8.8 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.5	2.3	0.4 ms	1.8	92 ms	0.4	0.2	5.3
Simulation, STEP	0.1	0.5	2.6	0.4 ms	1.8	1.6	0.4	0.2	7.2
Simulation, STL	0.1	0.5	2.7	0.4 ms	1.8	0.2	0.3	0.2	5.8
Simulation, OBJ	0.1	0.5	2.4	0.2 ms	1.7	2.8	0.4	0.2	8.1
Visual, GLB	0.1	0.5	2.4	0.3 ms	3.5	64 ms	0.5	0.2	7.3
Visual, OBJ	0.2	0.5	2.4	0.3 ms	3.4	1.6	0.5	0.2	8.8

Board	Repo: terrapin-rocket-team/srad-avionics Board: `Ground Receiver v2.kicad_pcb`
Folder	Spaceport / PCBs / Ground Reciever / Ground Reciever v2
Complexity	170 / 1000 (size 145, features 25)
KESE features	through vias, rounded, trapezoid or chamfered pads
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	19, 293, 16
Triangles, simulation	560,782 in 72 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	18 MB	298 MB
STEP	74 MB	358 MB
STL	28 MB	289 MB
OBJ	56 MB	412 MB
Visual
GLB	11 MB	371 MB
OBJ	34 MB	355 MB

2767. Ground Reciever

Ground Reciever: stages 4 and 6 take 52% to 81% of a run. Simulation, GLB takes 6.3 s. Simulation, STEP takes 7.7 s. Simulation, STL takes 6.0 s. Simulation, OBJ takes 8.9 s. Visual, GLB takes 8.9 s. Visual, OBJ takes 10 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.6	2.9	0.3 ms	1.9	99 ms	0.4	0.2	6.3
Simulation, STEP	0.2	0.6	2.7	0.3 ms	1.8	1.8	0.4	0.2	7.7
Simulation, STL	0.2	0.5	2.8	0.6 ms	1.9	0.2	0.4	0.2	6.0
Simulation, OBJ	0.2	0.6	2.7	0.3 ms	1.9	2.9	0.4	0.2	8.9
Visual, GLB	0.2	0.6	2.8	0.3 ms	4.4	68 ms	0.6	0.2	8.9
Visual, OBJ	0.2	0.6	2.5	0.4 ms	4.2	1.8	0.6	0.2	10.1

Board	Repo: terrapin-rocket-team/srad-avionics Board: `Ground Reciever.kicad_pcb`
Folder	Spaceport / PCBs / Ground Reciever
Complexity	174 / 1000 (size 149, features 25)
KESE features	through vias, rounded, trapezoid or chamfered pads
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	19, 392, 20
Triangles, simulation	612,778 in 72 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	20 MB	339 MB
STEP	86 MB	379 MB
STL	31 MB	331 MB
OBJ	61 MB	447 MB
Visual
GLB	13 MB	393 MB
OBJ	40 MB	396 MB

2768. ground-receiver

ground-receiver: stages 4 and 6 take 48% to 78% of a run. Simulation, GLB takes 8.2 s. Simulation, STEP takes 10 s. Simulation, STL takes 8.5 s. Simulation, OBJ takes 12 s. Visual, GLB takes 12 s. Visual, OBJ takes 14 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.0	3.1	0.3 ms	2.9	0.1	0.5	0.2	8.2
Simulation, STEP	0.3	1.0	3.1	0.5 ms	2.8	2.3	0.5	0.2	10.2
Simulation, STL	0.3	1.0	3.3	0.4 ms	2.8	0.3	0.5	0.3	8.5
Simulation, OBJ	0.3	1.1	3.3	0.4 ms	2.7	4.3	0.6	0.2	12.4
Visual, GLB	0.3	1.1	3.2	0.6 ms	6.0	78 ms	0.8	0.3	11.8
Visual, OBJ	0.3	0.9	3.2	0.4 ms	6.1	2.2	0.8	0.2	13.8

Board	Repo: terrapin-rocket-team/srad-avionics Board: `ground-receiver.kicad_pcb`
Folder	Spaceport / PCBs / ground-receiver
Complexity	276 / 1000 (size 181, features 95)
KESE features	through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 8 (20240108)
Parts, tracks, vias	56, 423, 43
Triangles, simulation	988,588 in 93 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	34 MB	437 MB
STEP	145 MB	494 MB
STL	49 MB	431 MB
OBJ	101 MB	713 MB
Visual
GLB	18 MB	529 MB
OBJ	54 MB	478 MB

2769. high-power-module

high-power-module: stages 4 and 6 take 45% to 79% of a run. Simulation, GLB takes 8.3 s. Simulation, STEP takes 11 s. Simulation, STL takes 8.5 s. Simulation, OBJ takes 13 s. Visual, GLB takes 13 s. Visual, OBJ takes 17 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.0	2.8	0.4 ms	3.3	0.1	0.4	0.2	8.3
Simulation, STEP	0.4	0.9	2.8	0.4 ms	3.2	2.7	0.5	0.2	10.7
Simulation, STL	0.4	1.0	2.9	0.4 ms	3.3	0.3	0.4	0.2	8.5
Simulation, OBJ	0.4	0.9	2.9	0.4 ms	3.2	5.4	0.5	0.3	13.5
Visual, GLB	0.4	0.9	2.7	0.4 ms	7.4	0.1	0.9	0.3	12.7
Visual, OBJ	0.4	1.0	2.8	0.5 ms	7.5	4.1	1.0	0.2	16.9

Board	Repo: terrapin-rocket-team/srad-avionics Board: `high-power-module.kicad_pcb`
Folder	Spaceport / PCBs / high-power-module
Complexity	343 / 1000 (size 233, features 110)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 8 (20240108)
Parts, tracks, vias	83, 566, 107
Triangles, simulation	972,140 in 95 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	33 MB	443 MB
STEP	139 MB	516 MB
STL	49 MB	438 MB
OBJ	99 MB	666 MB
Visual
GLB	24 MB	535 MB
OBJ	72 MB	601 MB

2770. LiBatteryCharger

LiBatteryCharger: stages 4 and 6 take 41% to 76% of a run. Simulation, GLB takes 1.4 s. Simulation, STEP takes 2.1 s. Simulation, STL takes 1.4 s. Simulation, OBJ takes 1.7 s. Visual, GLB takes 1.8 s. Visual, OBJ takes 2.6 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	96 ms	76 ms	0.4	0.1 ms	0.5	16 ms	61 ms	0.2	1.4
Simulation, STEP	94 ms	80 ms	0.3	0.2 ms	0.6	0.8	58 ms	0.2	2.1
Simulation, STL	0.1	82 ms	0.4	0.1 ms	0.6	23 ms	55 ms	0.2	1.4
Simulation, OBJ	97 ms	92 ms	0.3	0.1 ms	0.5	0.4	69 ms	0.2	1.7
Visual, GLB	80 ms	85 ms	0.4	0.1 ms	1.0	12 ms	73 ms	0.2	1.8
Visual, OBJ	0.2	81 ms	0.4	0.1 ms	1.2	0.5	0.1	0.2	2.6

Board	Repo: terrapin-rocket-team/srad-avionics Board: `LiBatteryCharger.kicad_pcb`
Folder	Spaceport / PCBs / LiBatteryCharger
Complexity	159 / 1000 (size 114, features 45)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	9, 58, 8
Triangles, simulation	89,894 in 17 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	3.1 MB	178 MB
STEP	15 MB	186 MB
STL	4.5 MB	172 MB
OBJ	8.6 MB	177 MB
Visual
GLB	2.2 MB	152 MB
OBJ	6.0 MB	153 MB

2771. live-video-multi-function-board

Stages 4 and 6 take 51% to 81% of a run. Simulation, GLB takes 9.4 s. Simulation, STEP takes 12 s. Simulation, STL takes 9.4 s. Simulation, OBJ takes 14 s. Visual, GLB takes 13 s. Visual, OBJ takes 16 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.1	3.8	0.5 ms	3.2	0.2	0.5	0.3	9.4
Simulation, STEP	0.4	1.2	3.8	0.6 ms	3.2	2.5	0.5	0.2	11.7
Simulation, STL	0.3	1.0	3.7	0.5 ms	3.3	0.3	0.5	0.2	9.4
Simulation, OBJ	0.3	1.1	3.6	0.4 ms	3.5	4.5	0.6	0.2	13.8
Visual, GLB	0.3	1.2	3.6	0.4 ms	7.0	84 ms	0.7	0.2	13.1
Visual, OBJ	0.3	1.1	3.8	0.6 ms	7.3	2.5	1.0	0.2	16.2

Board	Repo: terrapin-rocket-team/srad-avionics Board: `live-video-multi-function-board.kicad_pcb`
Folder	Spaceport / PCBs / live-video-multi-function-board
Complexity	275 / 1000 (size 180, features 95)
KESE features	through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 8 (20240108)
Parts, tracks, vias	59, 378, 49
Triangles, simulation	1,147,784 in 132 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	38 MB	476 MB
STEP	149 MB	530 MB
STL	57 MB	481 MB
OBJ	116 MB	795 MB
Visual
GLB	21 MB	588 MB
OBJ	64 MB	593 MB

2772. low_power_module

low_power_module: stages 4 and 6 take 48% to 82% of a run. Simulation, GLB takes 5.3 s. Simulation, STEP takes 6.8 s. Simulation, STL takes 5.3 s. Simulation, OBJ takes 7.8 s. Visual, GLB takes 7.6 s. Visual, OBJ takes 9.7 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.5	2.3	0.3 ms	1.8	86 ms	0.3	0.2	5.3
Simulation, STEP	0.2	0.5	2.1	0.3 ms	1.8	1.7	0.3	0.2	6.8
Simulation, STL	0.2	0.6	2.2	0.3 ms	1.8	0.2	0.3	0.2	5.3
Simulation, OBJ	0.2	0.6	2.1	0.3 ms	1.7	2.8	0.3	0.2	7.8
Visual, GLB	0.2	0.5	2.1	0.3 ms	4.1	60 ms	0.4	0.2	7.6
Visual, OBJ	0.2	0.5	2.2	0.2 ms	4.0	2.0	0.5	0.2	9.7

Board	Repo: terrapin-rocket-team/srad-avionics Board: `low_power_module.kicad_pcb`
Folder	Spaceport / PCBs / low_power_module
Complexity	200 / 1000 (size 155, features 45)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	49, 230, 36
Triangles, simulation	593,664 in 84 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	20 MB	320 MB
STEP	90 MB	399 MB
STL	30 MB	340 MB
OBJ	60 MB	428 MB
Visual
GLB	14 MB	399 MB
OBJ	43 MB	440 MB

2773. ESP32_BluetoothModule_TerrapinRockets

Stages 4 and 6 take 49% to 77% of a run. Simulation, GLB takes 1.9 s. Simulation, STEP takes 2.8 s. Simulation, STL takes 1.9 s. Simulation, OBJ takes 2.6 s. Visual, GLB takes 2.7 s. Visual, OBJ takes 3.3 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.1	0.6	0.2 ms	0.7	27 ms	98 ms	0.2	1.9
Simulation, STEP	0.1	0.2	0.7	0.2 ms	0.7	0.9	87 ms	0.2	2.8
Simulation, STL	0.1	0.1	0.6	0.2 ms	0.7	35 ms	87 ms	0.2	1.9
Simulation, OBJ	0.1	0.1	0.6	0.2 ms	0.7	0.7	96 ms	0.2	2.6
Visual, GLB	0.1	0.1	0.6	0.2 ms	1.5	20 ms	0.1	0.2	2.7
Visual, OBJ	0.1	0.1	0.6	0.3 ms	1.6	0.5	94 ms	0.2	3.3

Board	Repo: terrapin-rocket-team/srad-avionics Board: `ESP32_BluetoothModule_TerrapinRockets.kicad_pcb`
Folder	Spaceport / PCBs / MCU Boards / ESP32_BluetoothModule_TerrapinRockets
Complexity	163 / 1000 (size 118, features 45)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	12, 68, 7
Triangles, simulation	138,894 in 54 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	4.8 MB	189 MB
STEP	20 MB	202 MB
STL	6.9 MB	197 MB
OBJ	13 MB	197 MB
Visual
GLB	3.3 MB	157 MB
OBJ	9.3 MB	161 MB

2774. Main Board

Main Board: stages 4 and 6 take 48% to 81% of a run. Simulation, GLB takes 13 s. Simulation, STEP takes 16 s. Simulation, STL takes 13 s. Simulation, OBJ takes 19 s. Visual, GLB takes 20 s. Visual, OBJ takes 25 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.7	4.5	0.5 ms	4.9	0.3	0.6	0.3	12.7
Simulation, STEP	0.5	1.4	4.5	0.7 ms	5.0	3.9	0.6	0.3	16.3
Simulation, STL	0.5	1.4	4.5	0.8 ms	5.1	0.4	0.6	0.2	12.7
Simulation, OBJ	0.6	1.5	4.3	0.5 ms	4.7	6.7	0.5	0.2	18.5
Visual, GLB	0.5	1.4	4.4	0.6 ms	11.4	0.1	1.4	0.3	19.6
Visual, OBJ	0.5	1.6	4.7	1.0 ms	11.5	4.4	1.7	0.3	24.6

Board	Repo: terrapin-rocket-team/srad-avionics Board: `Main Board.kicad_pcb`
Folder	Spaceport / PCBs / MCU Boards / STM32 MCU Large
Complexity	367 / 1000 (size 242, features 125)
KESE features	through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 8 (20240108)
Parts, tracks, vias	87, 889, 199
Triangles, simulation	1,703,898 in 161 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	58 MB	600 MB
STEP	214 MB	741 MB
STL	85 MB	601 MB
OBJ	176 MB	1.2 GB
Visual
GLB	37 MB	711 MB
OBJ	112 MB	879 MB

2775. mcu-board

mcu-board: stages 4 and 6 take 46% to 78% of a run. Simulation, GLB takes 5.0 s. Simulation, STEP takes 6.7 s. Simulation, STL takes 5.3 s. Simulation, OBJ takes 7.8 s. Visual, GLB takes 6.5 s. Visual, OBJ takes 7.5 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.6	1.9	0.4 ms	1.7	91 ms	0.3	0.2	5.0
Simulation, STEP	0.2	0.6	1.9	0.4 ms	1.6	1.8	0.4	0.2	6.7
Simulation, STL	0.2	0.6	2.0	0.6 ms	1.8	0.2	0.4	0.3	5.3
Simulation, OBJ	0.2	0.6	1.9	0.4 ms	1.7	2.9	0.4	0.2	7.8
Visual, GLB	0.2	0.6	1.9	0.3 ms	3.2	41 ms	0.4	0.2	6.5
Visual, OBJ	0.2	0.6	1.9	0.3 ms	3.1	1.2	0.3	0.2	7.5

Board	Repo: terrapin-rocket-team/srad-avionics Board: `mcu-board.kicad_pcb`
Folder	Spaceport / PCBs / MCU Boards / Teensy MCU Board
Complexity	231 / 1000 (size 146, features 85)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 8 (20240108)
Parts, tracks, vias	17, 127, 5
Triangles, simulation	491,834 in 61 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	16 MB	258 MB
STEP	60 MB	292 MB
STL	25 MB	259 MB
OBJ	49 MB	368 MB
Visual
GLB	7.5 MB	277 MB
OBJ	22 MB	282 MB

2776. new-pa-test-board

new-pa-test-board: stages 4 and 6 take 40% to 74% of a run. Simulation, GLB takes 1.5 s. Simulation, STEP takes 2.2 s. Simulation, STL takes 1.5 s. Simulation, OBJ takes 2.0 s. Visual, GLB takes 2.1 s. Visual, OBJ takes 2.5 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.1	0.4	0.2 ms	0.6	21 ms	52 ms	0.2	1.5
Simulation, STEP	0.1	0.1	0.4	0.1 ms	0.5	0.8	51 ms	0.2	2.2
Simulation, STL	0.2	0.1	0.4	0.1 ms	0.5	25 ms	51 ms	0.3	1.5
Simulation, OBJ	0.1	0.1	0.4	0.2 ms	0.5	0.5	50 ms	0.2	2.0
Visual, GLB	0.1	0.1	0.4	0.2 ms	1.1	18 ms	92 ms	0.2	2.1
Visual, OBJ	0.1	0.1	0.4	0.1 ms	1.1	0.5	82 ms	0.2	2.5

Board	Repo: terrapin-rocket-team/srad-avionics Board: `new-pa-test-board.kicad_pcb`
Folder	Spaceport / PCBs / new-pa-test-board
Complexity	228 / 1000 (size 118, features 110)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	15, 27, 16
Triangles, simulation	113,532 in 21 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	4.0 MB	185 MB
STEP	19 MB	192 MB
STL	5.7 MB	189 MB
OBJ	11 MB	182 MB
Visual
GLB	3.0 MB	158 MB
OBJ	8.3 MB	158 MB

2777. pa-test-board

pa-test-board: stages 4 and 6 take 50% to 80% of a run. Simulation, GLB takes 2.1 s. Simulation, STEP takes 3.1 s. Simulation, STL takes 2.3 s. Simulation, OBJ takes 3.2 s. Visual, GLB takes 3.1 s. Visual, OBJ takes 3.6 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.7	0.1 ms	0.8	30 ms	90 ms	0.2	2.1
Simulation, STEP	0.1	0.2	0.8	0.2 ms	0.8	1.0	88 ms	0.2	3.1
Simulation, STL	0.1	0.2	0.8	0.2 ms	0.9	51 ms	88 ms	0.2	2.3
Simulation, OBJ	0.1	0.2	0.8	0.2 ms	0.8	1.0	94 ms	0.2	3.2
Visual, GLB	0.1	0.2	0.7	0.2 ms	1.7	19 ms	0.1	0.2	3.1
Visual, OBJ	0.1	0.1	0.8	0.2 ms	1.6	0.5	0.1	0.2	3.6

Board	Repo: terrapin-rocket-team/srad-avionics Board: `pa-test-board.kicad_pcb`
Folder	Spaceport / PCBs / pa-test-board
Complexity	212 / 1000 (size 137, features 75)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	26, 126, 15
Triangles, simulation	197,652 in 27 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	7.0 MB	218 MB
STEP	33 MB	228 MB
STL	9.9 MB	212 MB
OBJ	20 MB	213 MB
Visual
GLB	4.6 MB	202 MB
OBJ	13 MB	199 MB

2778. power-delivery-board

power-delivery-board: stages 4 and 6 take 48% to 81% of a run. Simulation, GLB takes 5.3 s. Simulation, STEP takes 7.3 s. Simulation, STL takes 5.1 s. Simulation, OBJ takes 7.8 s. Visual, GLB takes 7.3 s. Visual, OBJ takes 8.9 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.5	1.9	0.3 ms	2.2	90 ms	0.3	0.2	5.3
Simulation, STEP	0.2	0.5	1.8	0.3 ms	2.3	1.9	0.3	0.3	7.3
Simulation, STL	0.2	0.5	1.7	0.3 ms	2.0	0.2	0.3	0.3	5.1
Simulation, OBJ	0.2	0.5	1.8	0.2 ms	2.0	2.8	0.3	0.3	7.8
Visual, GLB	0.2	0.5	1.8	0.3 ms	4.1	49 ms	0.4	0.3	7.3
Visual, OBJ	0.2	0.4	1.7	0.2 ms	4.1	1.7	0.4	0.3	8.9

Board	Repo: terrapin-rocket-team/srad-avionics Board: `power-delivery-board.kicad_pcb`
Folder	Spaceport / PCBs / power-delivery-board / power-delivery-board
Complexity	273 / 1000 (size 178, features 95)
KESE features	through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 8 (20240108)
Parts, tracks, vias	60, 297, 51
Triangles, simulation	476,606 in 66 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	16 MB	268 MB
STEP	70 MB	313 MB
STL	24 MB	270 MB
OBJ	48 MB	321 MB
Visual
GLB	9.7 MB	288 MB
OBJ	28 MB	290 MB

2779. RF4463F30-test-board

RF4463F30-test-board: stages 4 and 6 take 45% to 76% of a run. Simulation, GLB takes 2.2 s. Simulation, STEP takes 3.0 s. Simulation, STL takes 2.1 s. Simulation, OBJ takes 3.2 s. Visual, GLB takes 3.3 s. Visual, OBJ takes 3.9 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.2	0.7	0.2 ms	0.8	32 ms	91 ms	0.2	2.2
Simulation, STEP	0.2	0.2	0.7	0.1 ms	0.8	0.9	88 ms	0.2	3.0
Simulation, STL	0.1	0.2	0.7	0.1 ms	0.8	43 ms	92 ms	0.2	2.1
Simulation, OBJ	0.1	0.2	0.7	0.2 ms	0.8	1.1	94 ms	0.2	3.2
Visual, GLB	0.2	0.2	0.7	0.2 ms	1.7	26 ms	0.2	0.2	3.3
Visual, OBJ	0.2	0.2	0.7	0.1 ms	1.7	0.8	0.1	0.2	3.9

Board	Repo: terrapin-rocket-team/srad-avionics Board: `RF4463F30-test-board.kicad_pcb`
Folder	Spaceport / PCBs / RF4463F30-test-board
Complexity	211 / 1000 (size 126, features 85)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	14, 85, 16
Triangles, simulation	189,326 in 32 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	6.6 MB	208 MB
STEP	32 MB	230 MB
STL	9.5 MB	206 MB
OBJ	19 MB	215 MB
Visual
GLB	5.7 MB	216 MB
OBJ	16 MB	214 MB

2780. Screw Switch

Screw Switch: stages 4 and 6 take 48% to 63% of a run. Simulation, GLB takes 0.7 s. Simulation, STEP takes 0.8 s. Simulation, STL takes 0.6 s. Simulation, OBJ takes 0.8 s. Visual, GLB takes 0.7 s. Visual, OBJ takes 0.8 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	7 ms	37 ms	0.1	0.1 ms	0.3	6 ms	22 ms	0.2	0.7
Simulation, STEP	7 ms	39 ms	0.1	0.1 ms	0.3	0.2	24 ms	0.2	0.8
Simulation, STL	6 ms	33 ms	0.1	0.1 ms	0.3	8 ms	22 ms	0.2	0.6
Simulation, OBJ	7 ms	40 ms	0.1	0.1 ms	0.3	0.1	29 ms	0.2	0.8
Visual, GLB	7 ms	35 ms	0.1	0.1 ms	0.3	4 ms	45 ms	0.2	0.7
Visual, OBJ	7 ms	37 ms	93 ms	0.1 ms	0.4	69 ms	36 ms	0.2	0.8

Board	Repo: terrapin-rocket-team/srad-avionics Board: `Screw Switch.kicad_pcb`
Folder	Spaceport / PCBs / Screw Switch
Complexity	90 / 1000 (size 70, features 20)
KESE features	copper drawings, curved board outline
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	4, 8, 0
Triangles, simulation	33,832 in 12 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	1.2 MB	44 MB
STEP	5.3 MB	47 MB
STL	1.7 MB	45 MB
OBJ	3.1 MB	51 MB
Visual
GLB	597 kB	64 MB
OBJ	1.6 MB	58 MB

2781. high-range-IMU

high-range-IMU: stages 4 and 6 take 45% to 65% of a run. Simulation, GLB takes 1.1 s. Simulation, STEP takes 1.5 s. Simulation, STL takes 1.1 s. Simulation, OBJ takes 1.3 s. Visual, GLB takes 1.2 s. Visual, OBJ takes 1.3 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	90 ms	57 ms	0.2	0.1 ms	0.5	9 ms	41 ms	0.2	1.1
Simulation, STEP	0.1	61 ms	0.2	0.1 ms	0.5	0.4	39 ms	0.2	1.5
Simulation, STL	91 ms	58 ms	0.2	0.1 ms	0.5	13 ms	33 ms	0.2	1.1
Simulation, OBJ	91 ms	60 ms	0.2	0.1 ms	0.4	0.2	36 ms	0.2	1.3
Visual, GLB	89 ms	68 ms	0.2	0.2 ms	0.6	7 ms	49 ms	0.2	1.2
Visual, OBJ	89 ms	57 ms	0.2	0.1 ms	0.5	0.2	49 ms	0.2	1.3

Board	Repo: terrapin-rocket-team/srad-avionics Board: `high-range-IMU.kicad_pcb`
Folder	Spaceport / PCBs / Sensor Boards / high-range-IMU
Complexity	156 / 1000 (size 101, features 55)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline
Tested	9th November 2026
Copper layers	2
File format	KiCad 9 (20241229)
Parts, tracks, vias	5, 44, 2
Triangles, simulation	45,474 in 19 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	1.6 MB	68 MB
STEP	7.1 MB	72 MB
STL	2.3 MB	69 MB
OBJ	4.4 MB	78 MB
Visual
GLB	1.2 MB	102 MB
OBJ	3.4 MB	96 MB

2782. PatchAntennaBreakout

PatchAntennaBreakout: stages 4 and 6 take 44% to 60% of a run. Simulation, GLB takes 0.8 s. Simulation, STEP takes 1.0 s. Simulation, STL takes 0.8 s. Simulation, OBJ takes 0.9 s. Visual, GLB takes 0.9 s. Visual, OBJ takes 1.0 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	77 ms	53 ms	0.1	0.1 ms	0.3	7 ms	24 ms	0.2	0.8
Simulation, STEP	72 ms	53 ms	0.1	0.1 ms	0.3	0.2	39 ms	0.2	1.0
Simulation, STL	70 ms	56 ms	0.1	0.1 ms	0.3	9 ms	23 ms	0.2	0.8
Simulation, OBJ	71 ms	54 ms	0.1	0.1 ms	0.3	0.2	21 ms	0.2	0.9
Visual, GLB	72 ms	51 ms	0.1	0.1 ms	0.4	6 ms	42 ms	0.2	0.9
Visual, OBJ	67 ms	53 ms	0.1	0.1 ms	0.4	0.1	44 ms	0.2	1.0

Board	Repo: terrapin-rocket-team/srad-avionics Board: `PatchAntennaBreakout.kicad_pcb`
Folder	Spaceport / PCBs / Sensor Boards / PatchAntennaBreakout
Complexity	170 / 1000 (size 95, features 75)
KESE features	through vias, filled zones, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	2, 1, 19
Triangles, simulation	40,898 in 10 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	1.4 MB	69 MB
STEP	4.6 MB	73 MB
STL	2.0 MB	70 MB
OBJ	3.9 MB	80 MB
Visual
GLB	1.2 MB	92 MB
OBJ	3.3 MB	103 MB

2783. SensorBoardNoMCU

SensorBoardNoMCU: stages 4 and 6 take 43% to 73% of a run. Simulation, GLB takes 1.7 s. Simulation, STEP takes 2.5 s. Simulation, STL takes 1.7 s. Simulation, OBJ takes 2.3 s. Visual, GLB takes 2.3 s. Visual, OBJ takes 2.8 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.4	0.2 ms	0.6	24 ms	79 ms	0.2	1.7
Simulation, STEP	0.1	0.2	0.5	0.1 ms	0.6	0.8	88 ms	0.2	2.5
Simulation, STL	0.1	0.2	0.5	0.1 ms	0.6	38 ms	76 ms	0.2	1.7
Simulation, OBJ	0.1	0.2	0.5	0.1 ms	0.6	0.7	93 ms	0.2	2.3
Visual, GLB	0.1	0.2	0.4	0.1 ms	1.2	16 ms	0.1	0.2	2.3
Visual, OBJ	0.1	0.2	0.5	0.2 ms	1.3	0.5	0.1	0.2	2.8

Board	Repo: terrapin-rocket-team/srad-avionics Board: `SensorBoardNoMCU.kicad_pcb`
Folder	Spaceport / PCBs / Sensor Boards / SensorBoardAirbrake
Complexity	255 / 1000 (size 140, features 115)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 10 (20260206)
Parts, tracks, vias	12, 92, 11
Triangles, simulation	138,354 in 23 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	4.9 MB	205 MB
STEP	22 MB	213 MB
STL	6.9 MB	203 MB
OBJ	14 MB	206 MB
Visual
GLB	3.5 MB	166 MB
OBJ	9.9 MB	164 MB

2784. SensorBoardNoMCU

SensorBoardNoMCU: stages 4 and 6 take 47% to 75% of a run. Simulation, GLB takes 2.3 s. Simulation, STEP takes 3.2 s. Simulation, STL takes 2.3 s. Simulation, OBJ takes 3.2 s. Visual, GLB takes 3.2 s. Visual, OBJ takes 3.8 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.2	0.7	0.1 ms	0.9	31 ms	88 ms	0.2	2.3
Simulation, STEP	0.2	0.2	0.6	0.2 ms	0.9	1.0	93 ms	0.3	3.2
Simulation, STL	0.2	0.2	0.6	0.2 ms	0.9	50 ms	96 ms	0.2	2.3
Simulation, OBJ	0.2	0.2	0.6	0.3 ms	0.9	1.0	0.1	0.2	3.2
Visual, GLB	0.2	0.2	0.7	0.2 ms	1.7	27 ms	0.2	0.2	3.2
Visual, OBJ	0.2	0.2	0.6	0.2 ms	1.8	0.7	0.2	0.2	3.8

Board	Repo: terrapin-rocket-team/srad-avionics Board: `SensorBoardNoMCU.kicad_pcb`
Folder	Spaceport / PCBs / Sensor Boards / SensorBoardPatch
Complexity	260 / 1000 (size 145, features 115)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	23, 227, 25
Triangles, simulation	201,870 in 37 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	7.1 MB	231 MB
STEP	36 MB	245 MB
STL	10 MB	229 MB
OBJ	20 MB	232 MB
Visual
GLB	6.3 MB	227 MB
OBJ	18 MB	225 MB

2785. SensorBoard

SensorBoard: stages 4 and 6 take 45% to 79% of a run. Simulation, GLB takes 7.8 s. Simulation, STEP takes 8.2 s. Simulation, STL takes 6.2 s. Simulation, OBJ takes 9.8 s. Visual, GLB takes 8.9 s. Visual, OBJ takes 11 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.0	3.1	0.4 ms	2.4	92 ms	0.4	0.3	7.8
Simulation, STEP	0.3	0.7	2.1	0.3 ms	2.3	2.1	0.3	0.3	8.2
Simulation, STL	0.3	0.6	2.1	0.5 ms	2.3	0.2	0.4	0.3	6.2
Simulation, OBJ	0.3	0.7	2.2	0.3 ms	2.3	3.8	0.3	0.2	9.8
Visual, GLB	0.3	0.7	2.2	0.4 ms	4.8	75 ms	0.5	0.3	8.9
Visual, OBJ	0.3	0.7	2.1	0.3 ms	5.0	2.4	0.7	0.3	11.4

Board	Repo: terrapin-rocket-team/srad-avionics Board: `SensorBoard.kicad_pcb`
Folder	Spaceport / PCBs / Sensor Boards / SensorBoardSTM32
Complexity	306 / 1000 (size 221, features 85)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 8 (20240108)
Parts, tracks, vias	47, 460, 58
Triangles, simulation	654,322 in 80 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	22 MB	331 MB
STEP	92 MB	409 MB
STL	33 MB	335 MB
OBJ	66 MB	492 MB
Visual
GLB	16 MB	472 MB
OBJ	48 MB	413 MB

2786. Unified_Board

Unified_Board: stages 4 and 6 take 47% to 81% of a run. Simulation, GLB takes 7.4 s. Simulation, STEP takes 10 s. Simulation, STL takes 7.4 s. Simulation, OBJ takes 12 s. Visual, GLB takes 11 s. Visual, OBJ takes 13 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.9	3.1	0.5 ms	2.3	0.1	0.5	0.2	7.4
Simulation, STEP	0.3	0.9	3.6	0.6 ms	2.6	2.1	0.4	0.2	10.0
Simulation, STL	0.3	0.9	3.1	0.5 ms	2.4	0.2	0.4	0.2	7.4
Simulation, OBJ	0.3	1.0	3.2	0.7 ms	2.4	4.4	0.4	0.2	11.9
Visual, GLB	0.3	0.9	3.1	0.4 ms	5.6	80 ms	0.5	0.2	10.7
Visual, OBJ	0.3	0.9	3.0	0.4 ms	5.6	2.6	0.7	0.3	13.3

Board	Repo: terrapin-rocket-team/srad-avionics Board: `Unified_Board.kicad_pcb`
Folder	Spaceport / PCBs / Unified Board / Unified_Board
Complexity	300 / 1000 (size 225, features 75)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ
Tested	10th November 2026
Copper layers	4
File format	KiCad 7 (20221018)
Parts, tracks, vias	47, 409, 26
Triangles, simulation	865,554 in 102 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	29 MB	393 MB
STEP	114 MB	464 MB
STL	43 MB	397 MB
OBJ	88 MB	614 MB
Visual
GLB	18 MB	535 MB
OBJ	55 MB	507 MB

2787. CM4_MATX

CM4_MATX: stages 4 and 6 take 47% to 84% of a run. Simulation, GLB takes 46 s. Simulation, STEP takes 54 s. Simulation, STL takes 46 s. Simulation, OBJ takes 77 s. Visual, GLB takes 61 s. Visual, OBJ takes 72 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	5.1	19.6	2 ms	17.0	0.9	2.0	0.3	45.6
Simulation, STEP	0.8	4.9	18.0	2 ms	16.9	11.4	2.0	0.3	54.2
Simulation, STL	0.7	4.8	18.4	2 ms	17.8	1.6	2.1	0.3	45.7
Simulation, OBJ	0.8	4.8	18.2	2 ms	17.9	32.9	2.2	0.3	77.1
Visual, GLB	0.7	4.8	17.9	2 ms	33.5	0.4	3.4	0.2	61.0
Visual, OBJ	0.8	4.8	17.9	2 ms	32.3	13.2	3.2	0.3	72.3

Board	Repo: TheGuyDanish/CM4_MATX Board: `CM4_MATX.kicad_pcb`
Folder	KiCad
Complexity	178 / 1000 (size 138, features 40)
KESE features	rounded, trapezoid or chamfered pads, filled zones, curved board outline
Tested	9th November 2026
Copper layers	4
File format	KiCad 5 (20171130)
Parts, tracks, vias	207, 0, 0
Triangles, simulation	5,118,422 in 613 parts
Note	mostly unrouted
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	169 MB	1.4 GB
STEP	517 MB	1.7 GB
STL	256 MB	1.3 GB
OBJ	550 MB	3.3 GB
Visual
GLB	86 MB	1.5 GB
OBJ	272 MB	1.8 GB

2788. cpu010

cpu010: stages 4 and 6 take 50% to 85% of a run. Simulation, GLB takes 5 min. Simulation, STEP takes 6 min. Simulation, STL takes 6 min. Simulation, OBJ takes 8 min. Visual, GLB takes 8 min. Visual, OBJ takes 10 min

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	6.5	28.6	133.2	18 ms	101.6	5.9	15.4	1.0	292.2
Simulation, STEP	6.3	26.8	134.8	4 ms	117.5	81.9	16.7	0.9	384.8
Simulation, STL	7.3	28.8	145.7	5 ms	132.2	15.8	18.4	1.2	349.4
Simulation, OBJ	6.1	25.9	126.4	3 ms	116.3	191.2	21.3	2.0	489.3
Visual, GLB	6.3	25.2	117.0	3 ms	289.6	3.3	34.5	0.6	476.5
Visual, OBJ	6.4	26.5	125.8	3 ms	294.3	93.1	35.2	0.7	581.8

Board	Repo: thorpej/pg68k Board: `cpu010.kicad_pcb`
Folder	cpu010 / design-files
Complexity	398 / 1000 (size 308, features 90)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, TrueType text, stack-up, dielectric εr and tanδ
Tested	9th November 2026 to 11th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	260, 10,422, 2,690
Triangles, simulation	26,264,430 in 658 parts
Verifier	PASS in all six runs
Run again	Simulation, OBJ: failed in the corpus run, run again with no memory cap and no time limit (swap added to a 16 GB machine), and passed

File type	File size	Peak memory used
Simulation
GLB	889 MB	6.4 GB
STEP	3.4 GB	8.2 GB
STL	1.3 GB	6.0 GB
OBJ	2.9 GB	17 GB
Visual
GLB	521 MB	8.0 GB
OBJ	1.7 GB	11 GB

2789. cpu030

cpu030: stages 4 and 6 take 43% to 84% of a run. Simulation, GLB takes 3 min. Simulation, STEP takes 3 min. Simulation, STL takes 3 min. Simulation, OBJ takes 5 min. Visual, GLB takes 4 min. Visual, OBJ takes 5 min

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	4.2	18.8	61.0	3 ms	61.8	4.4	10.7	0.6	161.4
Simulation, STEP	4.1	18.7	61.9	3 ms	62.1	44.1	10.6	0.6	202.2
Simulation, STL	4.1	19.0	64.2	2 ms	63.1	9.3	10.0	0.5	170.4
Simulation, OBJ	4.3	19.5	63.7	5 ms	63.9	135.9	10.5	0.7	298.6
Visual, GLB	4.3	19.2	63.5	2 ms	151.6	1.6	16.4	0.5	257.1
Visual, OBJ	4.0	18.7	63.9	4 ms	152.8	61.8	15.9	0.5	317.6

Board	Repo: thorpej/pg68k Board: `cpu030.kicad_pcb`
Folder	cpu030 / design-files
Complexity	403 / 1000 (size 313, features 90)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, TrueType text, stack-up, dielectric εr and tanδ
Tested	9th November 2026 to 10th November 2026
Copper layers	6
File format	KiCad 9 (20241229)
Parts, tracks, vias	227, 9,174, 1,472
Triangles, simulation	18,435,500 in 555 parts
Verifier	PASS in all six runs
Run again	Simulation, OBJ: failed in the corpus run, run again with the memory cap raised from 11 GB to 14.5 GB, and passed

File type	File size	Peak memory used
Simulation
GLB	616 MB	4.0 GB
STEP	2.1 GB	5.3 GB
STL	922 MB	3.8 GB
OBJ	2.0 GB	12 GB
Visual
GLB	304 MB	5.0 GB
OBJ	994 MB	6.5 GB

2790. nqvme_template

nqvme_template: stages 4 and 6 take 49% to 80% of a run. Simulation, GLB takes 6.8 s. Simulation, STEP takes 8.8 s. Simulation, STL takes 7.1 s. Simulation, OBJ takes 10 s. Visual, GLB takes 9.7 s. Visual, OBJ takes 11 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.8	2.7	0.6 ms	2.4	0.1	0.5	0.3	6.8
Simulation, STEP	0.1	0.7	2.9	0.9 ms	2.3	2.0	0.5	0.3	8.8
Simulation, STL	0.1	0.8	2.8	0.9 ms	2.4	0.2	0.5	0.2	7.1
Simulation, OBJ	0.1	0.7	2.7	0.6 ms	2.3	3.8	0.4	0.2	10.2
Visual, GLB	0.1	0.8	2.7	0.6 ms	5.1	56 ms	0.7	0.2	9.7
Visual, OBJ	0.1	0.9	2.8	0.6 ms	4.9	1.7	0.8	0.3	11.4

Board	Repo: thorpej/pg68k Board: `nqvme_template.kicad_pcb`
Folder	nqvme_template / design-files
Complexity	98 / 1000 (size 58, features 40)
KESE features	rounded, trapezoid or chamfered pads, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	9, 0, 0
Triangles, simulation	790,980 in 115 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	25 MB	327 MB
STEP	68 MB	390 MB
STL	40 MB	324 MB
OBJ	80 MB	563 MB
Visual
GLB	13 MB	425 MB
OBJ	38 MB	430 MB

2791. Apple2Card

Apple2Card: stages 4 and 6 take 53% to 86% of a run. Simulation, GLB takes 21 s. Simulation, STEP takes 26 s. Simulation, STL takes 21 s. Simulation, OBJ takes 32 s. Visual, GLB takes 30 s. Visual, OBJ takes 38 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.9	10.0	0.8 ms	7.0	0.3	1.0	0.2	20.9
Simulation, STEP	0.5	1.9	10.0	0.7 ms	7.0	5.6	1.0	0.3	26.1
Simulation, STL	0.5	1.9	10.0	1 ms	7.1	0.5	1.0	0.2	21.2
Simulation, OBJ	0.5	2.0	10.1	0.7 ms	7.2	11.4	1.1	0.2	32.4
Visual, GLB	0.5	1.9	10.2	0.7 ms	15.7	0.2	1.5	0.2	30.4
Visual, OBJ	0.5	1.9	10.5	1 ms	16.1	7.7	1.5	0.2	38.4

Board	Repo: ThorstenBr/Apple2Card Board: `Apple2Card.kicad_pcb`
Folder	Apple2Card
Complexity	258 / 1000 (size 183, features 75)
KESE features	through vias, filled zones, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 6 (20211014)
Parts, tracks, vias	77, 1,251, 48
Triangles, simulation	2,203,334 in 140 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	75 MB	791 MB
STEP	329 MB	941 MB
STL	110 MB	782 MB
OBJ	229 MB	1.5 GB
Visual
GLB	50 MB	918 MB
OBJ	152 MB	1.1 GB

2792. Apple2Card

Apple2Card: stages 4 and 6 take 53% to 85% of a run. Simulation, GLB takes 15 s. Simulation, STEP takes 20 s. Simulation, STL takes 15 s. Simulation, OBJ takes 23 s. Visual, GLB takes 22 s. Visual, OBJ takes 28 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.3	6.9	1 ms	5.4	0.2	0.7	0.2	15.1
Simulation, STEP	0.4	1.3	6.5	0.8 ms	5.8	4.7	0.7	0.2	19.6
Simulation, STL	0.4	1.3	6.7	0.8 ms	5.6	0.5	0.8	0.2	15.4
Simulation, OBJ	0.4	1.3	6.8	1 ms	5.6	8.3	0.7	0.2	23.2
Visual, GLB	0.4	1.3	6.7	0.8 ms	12.2	0.2	1.2	0.3	22.2
Visual, OBJ	0.4	1.2	6.5	1 ms	12.2	6.4	1.4	0.2	28.4

Board	Repo: ThorstenBr/Apple2Card Board: `Apple2Card.kicad_pcb`
Folder	Apple2Card_x44
Complexity	299 / 1000 (size 224, features 75)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	75, 977, 184
Triangles, simulation	1,599,832 in 148 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	54 MB	640 MB
STEP	256 MB	797 MB
STL	80 MB	612 MB
OBJ	164 MB	1.1 GB
Visual
GLB	41 MB	923 MB
OBJ	126 MB	986 MB

2793. TFGPS01

TFGPS01: stages 4 and 6 take 53% to 84% of a run. Simulation, GLB takes 12 s. Simulation, STEP takes 15 s. Simulation, STL takes 12 s. Simulation, OBJ takes 17 s. Visual, GLB takes 16 s. Visual, OBJ takes 20 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.2	5.3	0.4 ms	3.8	0.2	0.5	0.2	11.5
Simulation, STEP	0.4	1.2	5.4	0.4 ms	3.9	3.1	0.5	0.3	14.8
Simulation, STL	0.4	1.1	5.5	0.4 ms	4.0	0.4	0.5	0.2	12.0
Simulation, OBJ	0.3	1.2	5.2	0.4 ms	3.8	5.9	0.5	0.3	17.2
Visual, GLB	0.3	1.2	5.4	0.6 ms	7.9	0.1	0.7	0.2	15.8
Visual, OBJ	0.4	1.1	5.3	0.4 ms	7.9	4.0	0.8	0.2	19.6

Board	Repo: ThunderFly-aerospace/TFGPS01 Board: `TFGPS01.kicad_pcb`
Folder	hw / sch_pcb
Complexity	350 / 1000 (size 195, features 155)
KESE features	through vias, microvias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours
Tested	9th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	70, 508, 202
Triangles, simulation	1,120,590 in 81 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	38 MB	536 MB
STEP	171 MB	610 MB
STL	56 MB	543 MB
OBJ	116 MB	774 MB
Visual
GLB	25 MB	621 MB
OBJ	77 MB	626 MB

2794. tigard

tigard: stages 4 and 6 take 55% to 85% of a run. Simulation, GLB takes 23 s. Simulation, STEP takes 27 s. Simulation, STL takes 22 s. Simulation, OBJ takes 31 s. Visual, GLB takes 27 s. Visual, OBJ takes 34 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	1.8	10.5	0.6 ms	8.1	0.3	1.0	0.2	22.6
Simulation, STEP	0.5	1.9	10.2	0.4 ms	7.8	5.5	0.9	0.3	27.1
Simulation, STL	0.5	1.8	10.2	0.4 ms	7.8	0.6	0.9	0.3	22.2
Simulation, OBJ	0.5	1.7	9.8	0.3 ms	7.5	10.7	1.0	0.2	31.4
Visual, GLB	0.5	1.7	9.5	0.4 ms	13.5	0.2	1.4	0.2	27.1
Visual, OBJ	0.5	1.7	9.5	0.4 ms	13.3	7.1	1.2	0.3	33.6

Board	Repo: tigard-tools/tigard Board: `tigard.kicad_pcb`
Complexity	329 / 1000 (size 239, features 90)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline
Tested	9th November 2026
Copper layers	4
File format	KiCad 5 (20171130)
Parts, tracks, vias	84, 823, 148
Triangles, simulation	2,056,614 in 99 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	72 MB	834 MB
STEP	349 MB	895 MB
STL	103 MB	744 MB
OBJ	218 MB	1.4 GB
Visual
GLB	48 MB	963 MB
OBJ	145 MB	1.0 GB

2795. HDMI2USB

HDMI2USB: stages 4 and 6 take 45% to 88% of a run. Simulation, GLB takes 3 min. Simulation, STEP takes 3 min. Simulation, STL takes 3 min. Simulation, OBJ takes 6 min. Visual, GLB takes 5 min. Visual, OBJ takes 5 min

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.2	15.2	59.3	2 ms	61.9	3.5	10.0	0.6	152.7
Simulation, STEP	2.1	15.2	58.8	2 ms	62.5	30.2	10.2	0.6	179.7
Simulation, STL	2.1	15.8	59.3	2 ms	61.9	7.6	10.5	0.5	157.7
Simulation, OBJ	3.3	20.2	73.3	1 ms	77.4	147.2	12.1	0.6	334.1
Visual, GLB	2.3	16.4	62.8	2 ms	192.4	1.1	14.1	0.4	289.5
Visual, OBJ	2.1	15.5	60.2	2 ms	196.3	34.8	13.6	0.4	322.9

Board	Repo: timvideos/HDMI2USB-numato-opsis-hardware Board: `HDMI2USB.kicad_pcb`
Folder	board
Complexity	395 / 1000 (size 350, features 45)
KESE features	through vias, slotted holes, filled zones
Tested	9th November 2026 to 10th November 2026
Copper layers	10
File format	KiCad 3 (3)
Parts, tracks, vias	521, 14,026, 1,490
Triangles, simulation	17,762,300 in 499 parts
Verifier	PASS in all six runs
Run again	Simulation, OBJ: failed in the corpus run, run again with the memory cap raised from 11 GB to 14.5 GB, and passed

File type	File size	Peak memory used
Simulation
GLB	610 MB	3.1 GB
STEP	1.9 GB	4.8 GB
STL	888 MB	3.5 GB
OBJ	2.0 GB	11 GB
Visual
GLB	239 MB	4.1 GB
OBJ	800 MB	5.1 GB

2796. ethernet-extension-poe

ethernet-extension-poe: stages 4 and 6 take 43% to 77% of a run. Simulation, GLB takes 9.4 s. Simulation, STEP takes 11 s. Simulation, STL takes 9.7 s. Simulation, OBJ takes 14 s. Visual, GLB takes 15 s. Visual, OBJ takes 18 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.3	2.8	0.7 ms	3.7	0.3	0.6	0.2	9.4
Simulation, STEP	0.5	1.3	2.5	0.6 ms	3.6	2.6	0.6	0.3	11.4
Simulation, STL	0.5	1.6	2.6	0.9 ms	3.9	0.4	0.5	0.2	9.7
Simulation, OBJ	0.5	1.4	2.5	0.6 ms	3.6	5.5	0.5	0.2	14.3
Visual, GLB	0.5	1.5	2.6	0.9 ms	8.8	0.1	1.0	0.2	14.7
Visual, OBJ	0.5	1.4	2.6	0.6 ms	9.2	3.5	1.0	0.3	18.4

Board	Repo: Tinkerforge/ethernet-extension Board: `ethernet-extension-poe.kicad_pcb`
Folder	hardware / poe
Complexity	300 / 1000 (size 255, features 45)
KESE features	through vias, filled zones, curved board outline
Tested	9th November 2026
Copper layers	4
File format	KiCad 4 (4)
Parts, tracks, vias	106, 1,924, 345
Triangles, simulation	1,240,232 in 142 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	42 MB	537 MB
STEP	137 MB	599 MB
STL	62 MB	537 MB
OBJ	130 MB	852 MB
Visual
GLB	27 MB	666 MB
OBJ	86 MB	721 MB

2797. ethernet-extension-wopoe

ethernet-extension-wopoe: stages 4 and 6 take 50% to 78% of a run. Simulation, GLB takes 7.3 s. Simulation, STEP takes 9.5 s. Simulation, STL takes 7.0 s. Simulation, OBJ takes 9.5 s. Visual, GLB takes 12 s. Visual, OBJ takes 15 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	0.7	2.0	0.5 ms	3.0	0.1	0.6	0.2	7.3
Simulation, STEP	0.6	0.8	2.0	0.5 ms	3.0	2.5	0.5	0.2	9.5
Simulation, STL	0.6	0.8	2.0	0.5 ms	2.8	0.2	0.5	0.2	7.0
Simulation, OBJ	0.5	0.7	1.9	0.5 ms	2.8	2.9	0.4	0.2	9.5
Visual, GLB	0.6	0.8	1.9	0.6 ms	7.2	0.1	0.9	0.2	11.7
Visual, OBJ	0.5	0.8	1.9	0.4 ms	7.1	3.1	1.0	0.2	14.6

Board	Repo: Tinkerforge/ethernet-extension Board: `ethernet-extension-wopoe.kicad_pcb`
Folder	hardware / wo_poe
Complexity	268 / 1000 (size 223, features 45)
KESE features	through vias, filled zones, curved board outline
Tested	9th November 2026
Copper layers	2
File format	KiCad 6 (20211014)
Parts, tracks, vias	58, 1,029, 222
Triangles, simulation	668,918 in 103 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	23 MB	466 MB
STEP	102 MB	475 MB
STL	33 MB	461 MB
OBJ	69 MB	500 MB
Visual
GLB	21 MB	519 MB
OBJ	66 MB	582 MB

2798. evse-v4

evse-v4: stages 4 and 6 take 47% to 81% of a run. Simulation, GLB takes 14 s. Simulation, STEP takes 18 s. Simulation, STL takes 15 s. Simulation, OBJ takes 24 s. Visual, GLB takes 22 s. Visual, OBJ takes 28 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	2.0	4.8	0.7 ms	5.7	0.3	0.8	0.3	14.4
Simulation, STEP	0.4	1.9	5.1	0.7 ms	5.9	3.8	0.8	0.2	18.1
Simulation, STL	0.4	1.9	5.4	0.7 ms	6.1	0.5	0.8	0.2	15.3
Simulation, OBJ	0.4	2.1	5.2	0.7 ms	5.9	9.0	0.7	0.3	23.7
Visual, GLB	0.5	1.9	4.9	1 ms	12.9	0.2	1.5	0.2	22.2
Visual, OBJ	0.5	1.9	5.2	0.8 ms	13.0	5.3	1.6	0.3	27.8

Board	Repo: tinkerforge/evse-v4-bricklet Board: `evse-v4.kicad_pcb`
Folder	hardware
Complexity	353 / 1000 (size 258, features 95)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	167, 1,676, 312
Triangles, simulation	1,930,076 in 136 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	64 MB	661 MB
STEP	220 MB	839 MB
STL	97 MB	660 MB
OBJ	201 MB	1.3 GB
Visual
GLB	38 MB	751 MB
OBJ	118 MB	911 MB

2799. evse-v4b

evse-v4b: stages 4 and 6 take 45% to 80% of a run. Simulation, GLB takes 15 s. Simulation, STEP takes 19 s. Simulation, STL takes 16 s. Simulation, OBJ takes 25 s. Visual, GLB takes 22 s. Visual, OBJ takes 29 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	2.2	5.3	0.8 ms	6.1	0.3	0.9	0.2	15.4
Simulation, STEP	0.5	2.3	5.0	0.6 ms	6.2	4.3	0.8	0.3	19.4
Simulation, STL	0.4	2.2	5.3	0.6 ms	6.3	0.6	0.9	0.3	15.9
Simulation, OBJ	0.5	2.1	5.1	0.6 ms	6.1	10.2	0.8	0.2	25.1
Visual, GLB	0.5	2.1	5.1	0.6 ms	12.7	0.2	1.5	0.2	22.3
Visual, OBJ	0.5	2.1	5.1	0.7 ms	12.9	6.1	1.6	0.2	28.5

Board	Repo: tinkerforge/evse-v4-bricklet Board: `evse-v4b.kicad_pcb`
Folder	hardware / variant-b / evse-v4b
Complexity	343 / 1000 (size 258, features 85)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	167, 1,682, 308
Triangles, simulation	1,941,680 in 137 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	65 MB	691 MB
STEP	220 MB	858 MB
STL	97 MB	690 MB
OBJ	202 MB	1.3 GB
Visual
GLB	38 MB	782 MB
OBJ	119 MB	916 MB

2800. red

red: stages 4 and 6 take 41% to 79% of a run. Simulation, GLB takes 34 s. Simulation, STEP takes 41 s. Simulation, STL takes 33 s. Simulation, OBJ takes 58 s. Visual, GLB takes 49 s. Visual, OBJ takes 59 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.1	5.7	9.2	2 ms	14.8	0.8	2.0	0.3	33.9
Simulation, STEP	1.2	5.3	9.0	1 ms	14.1	9.3	1.9	0.3	41.0
Simulation, STL	1.2	5.4	8.8	2 ms	14.0	1.4	1.8	0.3	32.8
Simulation, OBJ	1.2	5.7	9.2	2 ms	14.2	24.9	2.1	0.4	57.6
Visual, GLB	1.1	5.4	9.0	2 ms	29.4	0.3	3.3	0.3	48.8
Visual, OBJ	1.1	5.1	8.4	2 ms	28.2	12.4	3.7	0.3	59.2

Board	Repo: Tinkerforge/red-brick Board: `red.kicad_pcb`
Folder	hardware
Complexity	366 / 1000 (size 311, features 55)
KESE features	through vias, slotted holes, filled zones, curved board outline
Tested	9th November 2026
Copper layers	6
File format	KiCad 4 (4)
Parts, tracks, vias	180, 8,041, 754
Triangles, simulation	4,307,386 in 319 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	147 MB	1.1 GB
STEP	444 MB	1.6 GB
STL	215 MB	1.2 GB
OBJ	465 MB	2.7 GB
Visual
GLB	73 MB	1.4 GB
OBJ	249 MB	1.6 GB

2801. TinyFPGA-BX

TinyFPGA-BX: stages 4 and 6 take 50% to 83% of a run. Simulation, GLB takes 7.8 s. Simulation, STEP takes 9.2 s. Simulation, STL takes 7.5 s. Simulation, OBJ takes 11 s. Visual, GLB takes 10 s. Visual, OBJ takes 13 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.7	3.4	0.4 ms	2.6	0.1	0.4	0.2	7.8
Simulation, STEP	0.2	0.7	3.1	0.4 ms	2.5	2.1	0.4	0.2	9.2
Simulation, STL	0.2	0.7	3.2	0.4 ms	2.5	0.2	0.4	0.2	7.5
Simulation, OBJ	0.2	0.7	3.2	0.5 ms	2.4	4.0	0.4	0.2	11.2
Visual, GLB	0.2	0.7	3.1	0.3 ms	5.5	75 ms	0.5	0.2	10.3
Visual, OBJ	0.2	0.7	3.2	0.4 ms	5.7	2.6	0.7	0.3	13.4

Board	Repo: tinyfpga/TinyFPGA-BX Board: `TinyFPGA-BX.kicad_pcb`
Folder	board
Complexity	223 / 1000 (size 188, features 35)
KESE features	through vias, filled zones
Tested	9th November 2026
Copper layers	4
File format	KiCad 4 (4)
Parts, tracks, vias	41, 822, 77
Triangles, simulation	723,140 in 83 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	25 MB	360 MB
STEP	104 MB	399 MB
STL	36 MB	352 MB
OBJ	74 MB	525 MB
Visual
GLB	15 MB	391 MB
OBJ	46 MB	383 MB

2802. caravel-breakout-fpga-ICE40UP5K-TT3

Stages 4 and 6 take 53% to 80% of a run. Simulation, GLB takes 13 s. Simulation, STEP takes 15 s. Simulation, STL takes 12 s. Simulation, OBJ takes 17 s. Visual, GLB takes 19 s. Visual, OBJ takes 24 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	1.3	4.4	0.6 ms	5.4	0.2	0.5	0.3	12.7
Simulation, STEP	0.5	1.3	4.3	0.6 ms	4.8	3.7	0.6	0.2	15.4
Simulation, STL	0.5	1.4	4.2	0.7 ms	5.1	0.4	0.6	0.3	12.5
Simulation, OBJ	0.5	1.4	4.5	0.7 ms	4.8	5.5	0.5	0.2	17.4
Visual, GLB	0.5	1.3	4.4	1 ms	10.8	0.2	1.5	0.2	19.0
Visual, OBJ	0.5	1.3	4.3	0.6 ms	10.8	5.0	1.7	0.2	24.0

Board	Repo: TinyTapeout/breakout-pcb Board: `caravel-breakout-fpga-ICE40UP5K-TT3.kicad_pcb`
Folder	ASIC-simulator / tt03-fpga-ICE40UP5k
Complexity	319 / 1000 (size 219, features 100)
KESE features	through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours
Tested	9th November 2026
Copper layers	2
File format	KiCad 7 (20221018)
Parts, tracks, vias	78, 734, 127
Triangles, simulation	1,226,884 in 105 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	43 MB	573 MB
STEP	223 MB	684 MB
STL	61 MB	565 MB
OBJ	127 MB	859 MB
Visual
GLB	39 MB	832 MB
OBJ	116 MB	839 MB

2803. breakout-fpga-ICE40UP5K

breakout-fpga-ICE40UP5K: stages 4 and 6 take 50% to 80% of a run. Simulation, GLB takes 18 s. Simulation, STEP takes 21 s. Simulation, STL takes 16 s. Simulation, OBJ takes 24 s. Visual, GLB takes 26 s. Visual, OBJ takes 33 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.0	2.1	6.5	1 ms	7.3	0.3	0.9	0.3	18.4
Simulation, STEP	0.8	2.1	6.2	0.8 ms	6.4	4.5	0.7	0.3	21.1
Simulation, STL	0.8	1.9	5.4	0.8 ms	6.4	0.5	0.8	0.3	16.1
Simulation, OBJ	0.8	1.9	5.4	0.7 ms	6.4	7.9	0.8	0.3	23.6
Visual, GLB	0.7	1.9	5.6	0.8 ms	15.7	0.2	2.1	0.3	26.5
Visual, OBJ	0.8	1.8	5.6	0.9 ms	15.5	6.4	2.2	0.3	32.6

Board	Repo: TinyTapeout/breakout-pcb Board: `breakout-fpga-ICE40UP5K.kicad_pcb`
Folder	ASIC-simulator / tt04-fpga-ICE40UP5k
Complexity	361 / 1000 (size 236, features 125)
KESE features	through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ
Tested	9th November 2026
Copper layers	4
File format	KiCad 8 (20240108)
Parts, tracks, vias	81, 732, 127
Triangles, simulation	1,557,710 in 110 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	54 MB	755 MB
STEP	263 MB	806 MB
STL	78 MB	719 MB
OBJ	163 MB	1.1 GB
Visual
GLB	44 MB	756 MB
OBJ	133 MB	950 MB

2804. tt06-fpga-ICE40UP5k

tt06-fpga-ICE40UP5k: stages 4 and 6 take 55% to 80% of a run. Simulation, GLB takes 16 s. Simulation, STEP takes 20 s. Simulation, STL takes 16 s. Simulation, OBJ takes 22 s. Visual, GLB takes 24 s. Visual, OBJ takes 30 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	2.1	7.5	0.3 ms	4.6	0.2	0.7	0.2	16.0
Simulation, STEP	0.8	2.2	7.6	0.3 ms	4.5	3.8	0.6	0.2	19.7
Simulation, STL	0.7	1.9	7.7	0.3 ms	4.8	0.4	0.7	0.2	16.4
Simulation, OBJ	0.8	2.3	7.7	0.3 ms	4.6	6.1	0.7	0.2	22.5
Visual, GLB	0.8	2.2	7.6	0.3 ms	11.8	0.2	1.4	0.2	24.2
Visual, OBJ	0.9	2.3	8.2	0.3 ms	12.0	5.2	1.5	0.3	30.3

Board	Repo: TinyTapeout/breakout-pcb Board: `tt06-fpga-ICE40UP5k.kicad_pcb`
Folder	ASIC-simulator / tt06-fpga-ICE40UP5k
Complexity	348 / 1000 (size 228, features 120)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ, mask and silkscreen colours
Tested	9th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	42, 621, 146
Triangles, simulation	1,365,290 in 87 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	49 MB	672 MB
STEP	238 MB	779 MB
STL	68 MB	661 MB
OBJ	145 MB	1000 MB
Visual
GLB	40 MB	841 MB
OBJ	121 MB	881 MB

2805. ttdbv3-fpga-ICE40UP5k

ttdbv3-fpga-ICE40UP5k: stages 4 and 6 take 53% to 79% of a run. Simulation, GLB takes 15 s. Simulation, STEP takes 18 s. Simulation, STL takes 15 s. Simulation, OBJ takes 21 s. Visual, GLB takes 23 s. Visual, OBJ takes 28 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	1.8	6.4	0.3 ms	4.5	0.2	0.7	0.3	14.7
Simulation, STEP	0.8	1.9	6.9	0.5 ms	4.5	3.3	0.8	0.2	18.3
Simulation, STL	0.8	2.0	6.5	0.3 ms	4.5	0.3	0.8	0.2	15.1
Simulation, OBJ	0.8	1.8	6.5	0.4 ms	4.7	6.5	0.7	0.2	21.4
Visual, GLB	0.8	2.1	6.6	0.4 ms	11.8	0.2	1.5	0.2	23.3
Visual, OBJ	0.8	2.2	6.6	0.3 ms	11.7	5.2	1.7	0.2	28.4

Board	Repo: TinyTapeout/breakout-pcb Board: `ttdbv3-fpga-ICE40UP5k.kicad_pcb`
Folder	ASIC-simulator / ttdbv3-fpga-ICE40UP5k
Complexity	353 / 1000 (size 233, features 120)
KESE features	through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ, mask and silkscreen colours
Tested	9th November 2026
Copper layers	4
File format	KiCad 9 (20241229)
Parts, tracks, vias	41, 924, 169
Triangles, simulation	1,380,220 in 92 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	49 MB	670 MB
STEP	233 MB	712 MB
STL	69 MB	690 MB
OBJ	146 MB	992 MB
Visual
GLB	38 MB	797 MB
OBJ	115 MB	863 MB

2806. breakout-dip-gf

breakout-dip-gf: stages 4 and 6 take 50% to 79% of a run. Simulation, GLB takes 9.9 s. Simulation, STEP takes 12 s. Simulation, STL takes 9.4 s. Simulation, OBJ takes 14 s. Visual, GLB takes 15 s. Visual, OBJ takes 19 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	1.0	3.4	0.6 ms	3.8	0.2	0.6	0.2	9.9
Simulation, STEP	0.6	1.0	3.5	0.5 ms	3.5	2.9	0.5	0.2	12.2
Simulation, STL	0.5	0.9	3.2	0.5 ms	3.6	0.4	0.6	0.3	9.4
Simulation, OBJ	0.6	0.9	3.4	0.3 ms	3.5	4.8	0.5	0.2	13.9
Visual, GLB	0.6	0.9	3.5	0.6 ms	8.5	0.2	1.3	0.2	15.2
Visual, OBJ	0.6	0.9	3.5	0.5 ms	8.4	3.8	1.2	0.2	18.5

Board	Repo: TinyTapeout/breakout-pcb Board: `breakout-dip-gf.kicad_pcb`
Folder	breakout-dip-gf
Complexity	386 / 1000 (size 231, features 155)
KESE features	through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ, mask and silkscreen colours
Tested	9th November 2026
Copper layers	4
File format	KiCad 10 (20260206)
Parts, tracks, vias	35, 1,067, 104
Triangles, simulation	1,104,480 in 110 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	38 MB	459 MB
STEP	176 MB	552 MB
STL	55 MB	462 MB
OBJ	113 MB	765 MB
Visual
GLB	27 MB	656 MB
OBJ	81 MB	645 MB

2807. breakout-ihp-qfn

breakout-ihp-qfn: stages 4 and 6 take 49% to 81% of a run. Simulation, GLB takes 11 s. Simulation, STEP takes 14 s. Simulation, STL takes 11 s. Simulation, OBJ takes 17 s. Visual, GLB takes 18 s. Visual, OBJ takes 21 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.2	3.7	0.4 ms	4.2	0.2	0.6	0.2	10.7
Simulation, STEP	0.6	1.2	3.8	0.5 ms	4.1	3.0	0.5	0.3	13.5
Simulation, STL	0.6	1.3	3.8	0.3 ms	4.2	0.4	0.6	0.3	11.1
Simulation, OBJ	0.5	1.2	4.0	0.3 ms	4.3	6.0	0.6	0.3	16.9
Visual, GLB	0.6	1.0	3.6	0.4 ms	10.6	0.2	1.3	0.2	17.5
Visual, OBJ	0.6	1.1	3.6	0.4 ms	10.1	4.4	1.2	0.3	21.3

Board	Repo: TinyTapeout/breakout-pcb Board: `breakout-ihp-qfn.kicad_pcb`
Folder	breakout-ihp-qfn
Complexity	378 / 1000 (size 233, features 145)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ, mask and silkscreen colours
Tested	9th November 2026
Copper layers	4
File format	KiCad 10 (20260206)
Parts, tracks, vias	37, 1,034, 182
Triangles, simulation	1,229,514 in 101 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	43 MB	533 MB
STEP	176 MB	628 MB
STL	61 MB	516 MB
OBJ	128 MB	845 MB
Visual
GLB	32 MB	709 MB
OBJ	96 MB	733 MB

2808. breakout-qfn

breakout-qfn: stages 4 and 6 take 53% to 83% of a run. Simulation, GLB takes 14 s. Simulation, STEP takes 17 s. Simulation, STL takes 13 s. Simulation, OBJ takes 19 s. Visual, GLB takes 20 s. Visual, OBJ takes 24 s

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	1.4	5.4	0.8 ms	5.1	0.2	0.6	0.3	13.6
Simulation, STEP	0.7	1.4	5.5	0.5 ms	4.6	4.0	0.5	0.2	17.0
Simulation, STL	0.6	1.5	5.0	0.7 ms	5.1	0.4	0.6	0.2	13.3
Simulation, OBJ	0.6	1.5	5.2	0.5 ms	5.1	6.1	0.5	0.3	19.4
Visual, GLB	0.6	1.3	5.0	0.4 ms	11.3	0.2	1.1	0.2	19.7
Visual, OBJ	0.6	1.4	4.5	0.5 ms	11.3	5.0	1.1	0.2	24.1

Board	Repo: TinyTapeout/breakout-pcb Board: `breakout-qfn.kicad_pcb`
Folder	breakout-qfn
Complexity	323 / 1000 (size 213, features 110)
KESE features	through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, TrueType text
Tested	9th November 2026
Copper layers	2
File format	KiCad 8 (20240108)
Parts, tracks, vias	44, 802, 118
Triangles, simulation	1,272,222 in 77 parts
Verifier	PASS in all six runs

File type	File size	Peak memory used
Simulation
GLB	45 MB	617 MB
STEP	254 MB	742 MB
STL	64 MB	604 MB
OBJ	132 MB	871 MB
Visual
GLB	39 MB	823 MB
OBJ	117 MB	840 MB

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