Corpus Testing 25

Corpus Page 25

Part 25 of 29 of Corpus Testing: every board of these projects, six runs each, one file format a run, as Corpus Testing describes.

25.1 SparkPNT_GPSDO_panelized

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.3	4.9	21.4	2 ms	16.9	0.9	2.5	0.3	48.3
Simulation, STEP	1.4	4.6	22.1	2 ms	16.3	11.5	2.4	0.3	58.5
Simulation, STL	1.3	4.8	22.0	4 ms	17.2	2.0	2.3	0.4	50.0
Simulation, OBJ	1.4	4.9	21.7	0.7 ms	16.2	23.3	2.6	0.3	70.3
Visual, GLB	1.4	5.2	22.2	2 ms	39.0	0.5	5.2	0.3	73.7
Visual, OBJ	1.5	4.9	21.5	5 ms	38.2	14.6	5.8	0.3	86.9

Board Repo: sparkfun/sparkfun_gnssdo Board: SparkPNT_GPSDO_panelized.kicad_pcb Folder Hardware / GNSSDO / Production Complexity 408 / 1000 (size 283, features 125) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 232, 2,036, 692 Triangles, simulation 4,628,930 in 261 parts Note panel Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 160 MB 1.4 GB STEP 685 MB 1.9 GB STL 231 MB 1.4 GB OBJ 496 MB 3.1 GB Visual GLB 99 MB 1.7 GB OBJ 312 MB 2.1 GB

25.2 SparkPNT_GPSDO

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.5	4.8	21.4	0.7 ms	15.6	0.7	2.2	0.3	46.5
Simulation, STEP	1.5	4.7	21.2	1 ms	15.4	10.6	2.0	0.3	55.7
Simulation, STL	1.4	4.6	21.3	0.7 ms	15.8	1.3	2.1	0.3	46.9
Simulation, OBJ	1.5	4.7	21.1	1 ms	15.5	24.8	2.1	0.3	70.0
Visual, GLB	1.4	4.7	21.7	0.7 ms	34.3	0.4	3.4	0.3	66.3
Visual, OBJ	1.4	4.7	21.6	0.8 ms	34.5	15.1	3.3	0.3	80.9

Board Repo: sparkfun/sparkfun_gnssdo Board: SparkPNT_GPSDO.kicad_pcb Folder Hardware / GNSSDO Complexity 408 / 1000 (size 283, features 125) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 232, 2,036, 692 Triangles, simulation 4,617,486 in 261 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 160 MB 1.4 GB STEP 682 MB 1.8 GB STL 231 MB 1.4 GB OBJ 494 MB 3.0 GB Visual GLB 99 MB 1.7 GB OBJ 311 MB 2.2 GB

25.3 SparkPNT_GNSSDO_Plus_panelized

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.6	6.2	22.1	2 ms	26.7	0.8	2.5	0.3	60.2
Simulation, STEP	1.7	6.1	22.1	1 ms	26.6	12.6	2.5	0.3	71.9
Simulation, STL	1.6	6.0	22.0	1 ms	26.2	1.5	2.4	0.3	60.2
Simulation, OBJ	1.6	6.0	21.4	0.9 ms	26.8	27.9	2.4	0.3	86.3
Visual, GLB	1.7	6.1	21.5	2 ms	39.8	0.5	4.8	0.3	74.7
Visual, OBJ	1.7	6.2	21.8	1 ms	40.0	17.7	4.5	0.3	92.1

Board Repo: sparkfun/sparkfun_gnssdo Board: SparkPNT_GNSSDO_Plus_panelized.kicad_pcb Folder Hardware / GNSSDO_Plus / Production Complexity 430 / 1000 (size 290, features 140) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 295, 2,557, 880 Triangles, simulation 5,206,738 in 314 parts Note panel Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 178 MB 1.6 GB STEP 723 MB 2.1 GB STL 260 MB 1.6 GB OBJ 552 MB 3.4 GB Visual GLB 115 MB 1.9 GB OBJ 366 MB 2.4 GB

25.4 SparkPNT_GNSSDO_Plus

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.6	6.4	22.3	1 ms	28.4	0.8	2.5	0.4	62.6
Simulation, STEP	1.7	6.1	21.9	0.8 ms	29.3	13.7	2.4	0.3	75.4
Simulation, STL	1.7	6.5	22.2	1 ms	30.6	1.8	2.7	0.3	65.8
Simulation, OBJ	1.6	6.2	22.8	2 ms	30.1	31.3	2.5	0.3	94.8
Visual, GLB	1.7	5.9	21.9	0.9 ms	45.8	0.5	6.0	0.3	82.1
Visual, OBJ	1.7	6.0	21.3	1.0 ms	42.3	18.0	6.4	0.3	96.0

Board Repo: sparkfun/sparkfun_gnssdo Board: SparkPNT_GNSSDO_Plus.kicad_pcb Folder Hardware / GNSSDO_Plus Complexity 430 / 1000 (size 290, features 140) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 295, 2,557, 880 Triangles, simulation 5,196,270 in 314 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 177 MB 1.6 GB STEP 721 MB 2.1 GB STL 260 MB 1.6 GB OBJ 551 MB 3.4 GB Visual GLB 114 MB 1.9 GB OBJ 365 MB 2.4 GB

25.5 SparkFun_Thing_Plus_ESP32-S3_panelized

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	5.0	14.1	49.7	1.0 ms	59.0	2.4	6.3	0.5	136.9
Simulation, STEP	4.9	13.9	48.2	1.0 ms	58.1	37.6	7.0	0.5	170.2
Simulation, STL	5.1	13.9	49.1	0.8 ms	60.0	5.6	6.9	0.6	141.1
Simulation, OBJ	4.9	13.8	49.2	1 ms	57.9	88.1	6.0	0.5	220.5
Visual, GLB	5.0	12.8	47.3	0.9 ms	125.0	1.6	15.7	0.5	207.9
Visual, OBJ	4.9	13.2	46.5	1 ms	129.0	55.7	15.0	0.5	264.6

Board Repo: sparkfun/SparkFun_Thing_Plus_ESP32-S3 Board: SparkFun_Thing_Plus_ESP32-S3_panelized.kicad_pcb Folder Hardware / Production Complexity 400 / 1000 (size 260, features 140) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 648, 9,624, 1,560 Triangles, simulation 13,717,750 in 86 parts Note panel Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 478 MB 3.4 GB STEP 2.3 GB 4.9 GB STL 686 MB 3.5 GB OBJ 1.5 GB 9.0 GB Visual GLB 330 MB 5.0 GB OBJ 1.1 GB 6.4 GB

25.6 SparkFun_Thing_Plus_ESP32-S3

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	0.9	2.5	0.5 ms	3.3	0.2	0.5	0.3	8.2
Simulation, STEP	0.4	1.1	2.7	0.7 ms	3.4	2.7	0.6	0.2	11.1
Simulation, STL	0.4	1.0	2.5	0.5 ms	3.6	0.3	0.5	0.2	8.6
Simulation, OBJ	0.4	1.0	2.7	0.9 ms	3.3	4.8	0.5	0.3	13.1
Visual, GLB	0.3	0.9	2.8	0.4 ms	7.8	0.1	1.1	0.2	13.2
Visual, OBJ	0.4	0.9	2.3	0.6 ms	7.8	4.0	0.9	0.2	16.6

Board Repo: sparkfun/SparkFun_Thing_Plus_ESP32-S3 Board: SparkFun_Thing_Plus_ESP32-S3.kicad_pcb Folder Hardware Complexity 333 / 1000 (size 193, features 140) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 54, 800, 130 Triangles, simulation 1,078,334 in 86 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 37 MB 460 MB STEP 167 MB 552 MB STL 54 MB 446 MB OBJ 110 MB 749 MB Visual GLB 26 MB 608 MB OBJ 79 MB 615 MB

25.7 MAP Card

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	88 ms	95 ms	0.3	0.2 ms	0.5	14 ms	41 ms	0.3	1.3
Simulation, STEP	89 ms	93 ms	0.3	0.1 ms	0.6	0.8	38 ms	0.2	2.1
Simulation, STL	83 ms	80 ms	0.3	0.1 ms	0.5	19 ms	41 ms	0.2	1.2
Simulation, OBJ	84 ms	90 ms	0.3	0.1 ms	0.5	0.4	44 ms	0.2	1.6
Visual, GLB	87 ms	86 ms	0.3	0.1 ms	1.1	16 ms	76 ms	0.2	1.9
Visual, OBJ	84 ms	88 ms	0.3	0.1 ms	1.1	0.3	65 ms	0.2	2.1

Board Repo: speeduino/hardware Board: MAP Card.kicad_pcb Folder DropBear / MAP Card / v0.2 Complexity 155 / 1000 (size 100, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 6, 29, 5 Triangles, simulation 68,062 in 21 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 2.4 MB 170 MB STEP 13 MB 181 MB STL 3.4 MB 177 MB OBJ 6.7 MB 174 MB Visual GLB 2.0 MB 153 MB OBJ 5.7 MB 154 MB

25.8 MAP Card

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	84 ms	0.2	0.1 ms	0.4	10 ms	33 ms	0.2	1.1
Simulation, STEP	66 ms	75 ms	0.2	0.1 ms	0.4	0.7	32 ms	0.2	1.8
Simulation, STL	74 ms	67 ms	0.2	0.1 ms	0.4	17 ms	31 ms	0.2	1.1
Simulation, OBJ	78 ms	68 ms	0.2	0.2 ms	0.5	0.3	34 ms	0.2	1.4
Visual, GLB	76 ms	75 ms	0.2	0.1 ms	1.0	8 ms	51 ms	0.2	1.6
Visual, OBJ	82 ms	77 ms	0.2	0.1 ms	0.9	0.2	60 ms	0.2	1.8

Board Repo: speeduino/hardware Board: MAP Card.kicad_pcb Folder DropBear / MAP Card / v0.3 Complexity 184 / 1000 (size 99, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 6, 25, 5 Triangles, simulation 61,804 in 21 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 2.2 MB 171 MB STEP 12 MB 175 MB STL 3.1 MB 174 MB OBJ 6.2 MB 170 MB Visual GLB 1.8 MB 153 MB OBJ 5.1 MB 152 MB

25.9 DropBear

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	3.5	18.9	1 ms	13.0	0.5	1.5	0.3	38.5
Simulation, STEP	0.9	3.6	18.8	1 ms	12.5	8.2	1.4	0.3	45.6
Simulation, STL	0.8	3.5	18.9	1 ms	12.9	0.9	1.5	0.3	38.8
Simulation, OBJ	0.8	3.3	18.8	1 ms	13.3	15.5	1.5	0.3	53.6
Visual, GLB	0.8	3.5	18.8	0.7 ms	26.4	0.3	2.2	0.2	52.2
Visual, OBJ	0.8	3.4	18.8	2 ms	25.9	11.1	2.2	0.3	62.6

Board Repo: speeduino/hardware Board: DropBear.kicad_pcb Folder DropBear / V1.1 Complexity 367 / 1000 (size 257, features 110) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 187, 2,130, 417 Triangles, simulation 2,877,926 in 282 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 101 MB 1.0 GB STEP 544 MB 1.3 GB STL 144 MB 993 MB OBJ 309 MB 2.0 GB Visual GLB 72 MB 1.3 GB OBJ 222 MB 1.6 GB

25.10 DropBear

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	2.4	11.6	1.0 ms	11.5	0.4	1.2	0.3	28.0
Simulation, STEP	0.7	2.2	12.3	1 ms	11.6	7.8	1.3	0.3	36.1
Simulation, STL	0.7	2.3	12.0	0.8 ms	12.0	0.9	1.3	0.3	29.4
Simulation, OBJ	0.7	2.2	12.5	0.7 ms	11.9	12.6	1.3	0.3	41.4
Visual, GLB	0.9	2.5	12.4	0.9 ms	26.2	0.3	3.3	0.3	45.9
Visual, OBJ	0.8	2.4	12.8	1 ms	26.3	9.9	4.0	0.3	56.4

Board Repo: speeduino/hardware Board: DropBear.kicad_pcb Folder DropBear / V2 Complexity 347 / 1000 (size 252, features 95) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 196, 1,873, 400 Triangles, simulation 2,619,384 in 260 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 90 MB 930 MB STEP 447 MB 1.2 GB STL 131 MB 926 MB OBJ 277 MB 1.7 GB Visual GLB 71 MB 1.2 GB OBJ 219 MB 1.5 GB

25.11 48-pin breakout

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.5	2.9	0.3 ms	1.8	87 ms	0.3	0.2	5.9
Simulation, STEP	0.2	0.6	2.8	0.3 ms	1.8	1.8	0.3	0.2	7.6
Simulation, STL	0.2	0.5	2.7	0.3 ms	2.0	0.1	0.3	0.2	6.1
Simulation, OBJ	0.2	0.5	2.9	0.3 ms	1.8	3.1	0.3	0.2	9.0
Visual, GLB	0.2	0.5	2.9	0.3 ms	4.0	52 ms	0.4	0.2	8.2
Visual, OBJ	0.2	0.5	2.8	0.3 ms	4.1	1.7	0.4	0.2	10.0

Board Repo: speeduino/hardware Board: 48-pin breakout.kicad_pcb Folder PNPs / Miata NA6 / Latest / 48-pin breakout Complexity 148 / 1000 (size 113, features 35) KESE features through vias, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 4, 111, 4 Triangles, simulation 609,954 in 56 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 21 MB 315 MB STEP 99 MB 359 MB STL 31 MB 311 MB OBJ 62 MB 446 MB Visual GLB 12 MB 356 MB OBJ 37 MB 355 MB

25.12 NA6 v1.3

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.9	3.7	22.7	1 ms	15.7	0.7	2.0	0.5	46.2
Simulation, STEP	0.8	3.9	24.5	0.7 ms	14.9	10.3	1.8	0.3	56.6
Simulation, STL	0.8	3.4	24.6	0.7 ms	14.0	1.1	1.9	0.3	46.0
Simulation, OBJ	0.7	3.7	21.6	0.6 ms	12.8	20.9	1.6	0.3	61.8
Visual, GLB	0.7	3.6	23.8	0.6 ms	27.4	0.4	3.3	0.3	59.4
Visual, OBJ	0.7	3.4	22.7	0.9 ms	23.5	12.4	4.2	0.3	67.3

Board Repo: speeduino/hardware Board: NA6 v1.3.kicad_pcb Folder PNPs / Miata NA6 / Latest Complexity 300 / 1000 (size 230, features 70) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 146, 1,019, 130 Triangles, simulation 2,797,794 in 233 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 97 MB 880 MB STEP 517 MB 1.2 GB STL 140 MB 979 MB OBJ 298 MB 1.9 GB Visual GLB 60 MB 1.0 GB OBJ 184 MB 1.3 GB

25.13 NA6

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	3.3	21.7	0.8 ms	15.3	0.6	1.8	0.3	43.6
Simulation, STEP	0.7	3.2	21.7	1 ms	12.9	9.3	1.7	0.4	49.9
Simulation, STL	0.6	3.3	21.3	0.6 ms	13.4	1.2	1.7	0.3	41.7
Simulation, OBJ	0.7	3.2	21.1	0.7 ms	13.1	17.3	1.9	0.3	57.6
Visual, GLB	0.7	3.4	21.4	0.7 ms	25.8	0.3	2.9	0.3	54.8
Visual, OBJ	0.7	2.9	19.6	0.8 ms	24.4	10.8	3.1	0.3	61.8

Board Repo: speeduino/hardware Board: NA6.kicad_pcb Folder PNPs / Miata NA6 / Prior versions / v1.2 Complexity 298 / 1000 (size 228, features 70) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 141, 963, 107 Triangles, simulation 2,917,634 in 234 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 100 MB 1.1 GB STEP 516 MB 1.2 GB STL 146 MB 1.0 GB OBJ 309 MB 2.0 GB Visual GLB 65 MB 1.2 GB OBJ 199 MB 1.4 GB

25.14 Screw terminal interface

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.3	1.3	0.3 ms	1.1	62 ms	0.2	0.2	3.2
Simulation, STEP	0.1	0.3	1.4	0.2 ms	1.0	1.1	0.2	0.2	4.3
Simulation, STL	0.1	0.3	1.4	0.4 ms	1.0	66 ms	0.2	0.2	3.3
Simulation, OBJ	0.1	0.3	1.3	0.4 ms	1.1	1.4	0.2	0.2	4.6
Visual, GLB	0.1	0.3	1.3	0.3 ms	1.7	20 ms	0.2	0.2	3.8
Visual, OBJ	0.1	0.3	1.4	0.6 ms	1.8	0.6	0.3	0.2	4.6

Board Repo: speeduino/hardware Board: Screw terminal interface.kicad_pcb Folder v0.4 / Interface boards / Screw terminals Complexity 95 / 1000 (size 95, features 0) Tested 9th November 2026 Copper layers 2 File format KiCad 4 (4) Parts, tracks, vias 7, 29, 0 Triangles, simulation 292,454 in 53 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 9.7 MB 222 MB STEP 44 MB 256 MB STL 15 MB 222 MB OBJ 29 MB 250 MB Visual GLB 4.5 MB 255 MB OBJ 13 MB 276 MB

25.15 v0.4.4d

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	4.6	23.0	0.7 ms	13.9	0.6	1.9	0.3	45.0
Simulation, STEP	0.6	4.8	23.9	0.7 ms	13.8	10.4	2.0	0.3	55.8
Simulation, STL	0.7	5.0	24.0	0.9 ms	14.5	1.4	2.0	0.4	48.0
Simulation, OBJ	0.8	4.8	24.2	0.9 ms	14.7	18.2	1.9	0.3	64.9
Visual, GLB	0.7	4.6	23.8	0.6 ms	30.6	0.4	4.1	0.3	64.5
Visual, OBJ	0.7	5.0	24.5	1 ms	30.5	11.6	4.4	0.3	77.2

Board Repo: speeduino/hardware Board: v0.4.4d.kicad_pcb Folder v0.4 / SMD / Latest Complexity 262 / 1000 (size 192, features 70) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 147, 1,055, 178 Triangles, simulation 3,530,694 in 196 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 122 MB 1.2 GB STEP 641 MB 1.3 GB STL 177 MB 1.2 GB OBJ 376 MB 2.3 GB Visual GLB 80 MB 1.3 GB OBJ 249 MB 1.6 GB

25.16 v0.4.4b

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	3.9	22.1	1.0 ms	12.7	0.5	1.8	0.3	41.7
Simulation, STEP	0.7	3.8	22.1	1 ms	12.7	9.3	1.6	0.3	50.6
Simulation, STL	0.6	4.0	21.0	0.8 ms	12.2	1.1	1.5	0.3	40.9
Simulation, OBJ	0.8	3.9	21.1	0.7 ms	12.2	16.1	1.7	0.3	56.1
Visual, GLB	0.6	3.9	21.5	0.6 ms	25.8	0.3	3.7	0.2	56.1
Visual, OBJ	0.6	4.0	21.7	0.9 ms	26.5	10.8	4.2	0.3	68.0

Board Repo: speeduino/hardware Board: v0.4.4b.kicad_pcb Folder v0.4 / SMD / Prior Versions / 0.4.4b Complexity 233 / 1000 (size 188, features 45) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 143, 990, 89 Triangles, simulation 3,391,558 in 194 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 117 MB 1.2 GB STEP 631 MB 1.4 GB STL 170 MB 1.1 GB OBJ 361 MB 2.2 GB Visual GLB 76 MB 1.3 GB OBJ 234 MB 1.6 GB

25.17 v0.4.4c

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	4.1	21.4	0.6 ms	12.8	0.6	1.6	0.3	41.3
Simulation, STEP	0.7	4.1	20.9	0.6 ms	12.0	9.4	1.6	0.3	48.9
Simulation, STL	0.7	4.2	22.0	0.7 ms	12.9	1.3	1.7	0.3	43.1
Simulation, OBJ	0.7	4.2	21.4	0.9 ms	12.9	16.7	1.9	0.3	58.2
Visual, GLB	0.6	4.3	22.0	0.8 ms	28.2	0.3	3.9	0.3	59.7
Visual, OBJ	0.7	4.4	21.1	0.7 ms	26.2	10.1	4.0	0.3	66.8

Board Repo: speeduino/hardware Board: v0.4.4c.kicad_pcb Folder v0.4 / SMD / Prior Versions / 0.4.4c Complexity 259 / 1000 (size 189, features 70) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 148, 1,038, 113 Triangles, simulation 3,484,966 in 196 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 120 MB 1.3 GB STEP 640 MB 1.4 GB STL 174 MB 1.3 GB OBJ 371 MB 2.3 GB Visual GLB 78 MB 1.3 GB OBJ 243 MB 1.7 GB

25.18 v0.4.3d

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	3.5	20.1	0.8 ms	13.2	0.6	2.0	0.3	40.4
Simulation, STEP	0.6	3.5	19.7	0.6 ms	12.9	9.7	1.9	0.3	48.6
Simulation, STL	0.7	3.5	19.8	0.9 ms	13.1	1.1	2.0	0.3	40.5
Simulation, OBJ	0.6	3.5	19.6	0.9 ms	13.2	19.7	2.0	0.3	58.8
Visual, GLB	0.6	3.5	19.5	0.5 ms	27.4	0.3	2.4	0.2	53.9
Visual, OBJ	0.6	3.5	19.6	0.6 ms	28.6	12.6	3.1	0.2	68.3

Board Repo: speeduino/hardware Board: v0.4.3d.kicad_pcb Folder v0.4 / THT / Latest Complexity 258 / 1000 (size 188, features 70) KESE features through vias, custom pads, drill offsets, filled zones, copper drawings Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 133, 989, 124 Triangles, simulation 3,718,100 in 174 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 128 MB 1.1 GB STEP 622 MB 1.4 GB STL 186 MB 1.1 GB OBJ 396 MB 2.4 GB Visual GLB 80 MB 1.3 GB OBJ 250 MB 1.7 GB

25.19 VR-Conditioner-MAX9926+reg

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	1.0	0.2 ms	0.8	46 ms	0.1	0.2	2.4
Simulation, STEP	0.1	0.2	1.0	0.2 ms	0.8	0.9	0.1	0.2	3.2
Simulation, STL	0.1	0.2	1.0	0.2 ms	0.7	51 ms	0.1	0.2	2.4
Simulation, OBJ	0.1	0.2	0.9	0.1 ms	0.8	0.9	0.1	0.2	3.2
Visual, GLB	0.1	0.2	1.0	0.2 ms	1.7	26 ms	0.3	0.2	3.6
Visual, OBJ	0.1	0.2	1.0	0.2 ms	1.8	0.7	0.2	0.2	4.2

Board Repo: speeduino/hardware Board: VR-Conditioner-MAX9926+reg.kicad_pcb Folder VR Conditioner / Latest Complexity 193 / 1000 (size 138, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 18, 209, 6 Triangles, simulation 241,764 in 28 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 8.6 MB 222 MB STEP 44 MB 237 MB STL 12 MB 219 MB OBJ 25 MB 216 MB Visual GLB 6.1 MB 213 MB OBJ 18 MB 199 MB

25.20 DubaiXTClone

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.5	11.4	49.6	2 ms	51.1	3.3	8.2	0.5	126.6
Simulation, STEP	2.7	13.9	53.6	2 ms	56.1	34.7	7.0	0.6	168.7
Simulation, STL	2.6	12.1	53.6	2 ms	52.4	7.0	8.4	0.5	136.6
Simulation, OBJ	2.7	13.3	53.6	2 ms	57.6	98.3	7.0	0.4	232.9
Visual, GLB	2.6	11.9	49.9	2 ms	104.3	1.2	12.1	0.4	182.5
Visual, OBJ	2.7	11.9	48.8	2 ms	104.6	39.8	12.3	0.4	220.6

Board Repo: spencer-uk/DubaiXTClone Board: DubaiXTClone.kicad_pcb Complexity 360 / 1000 (size 240, features 120) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text, TrueType text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 144, 9,528, 536 Triangles, simulation 14,240,612 in 407 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 481 MB 3.1 GB STEP 1.7 GB 4.3 GB STL 712 MB 3.1 GB OBJ 1.5 GB 8.8 GB Visual GLB 225 MB 3.7 GB OBJ 734 MB 4.8 GB

25.21 cm5-carrier

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.0	2.7	0.7 ms	2.2	0.1	0.4	0.3	7.1
Simulation, STEP	0.4	0.9	2.6	0.6 ms	2.2	2.0	0.4	0.2	8.7
Simulation, STL	0.5	0.9	2.8	0.7 ms	2.2	0.2	0.3	0.2	7.1
Simulation, OBJ	0.5	0.9	2.6	0.6 ms	2.1	2.9	0.3	0.2	9.5
Visual, GLB	0.5	0.9	2.6	0.9 ms	6.5	83 ms	0.6	0.2	11.4
Visual, OBJ	0.5	1.0	2.8	0.7 ms	7.0	1.9	0.6	0.3	14.1

Board Repo: spirit-org/spirit Board: cm5-carrier.kicad_pcb Folder EDA-kicad Complexity 362 / 1000 (size 232, features 130) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 123, 243, 43 Triangles, simulation 708,064 in 381 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 25 MB 355 MB STEP 104 MB 425 MB STL 35 MB 355 MB OBJ 75 MB 556 MB Visual GLB 17 MB 432 MB OBJ 50 MB 453 MB

25.22 motherboard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	8.3	20.9	127.5	6 ms	94.0	4.7	22.3	1.4	279.2
Simulation, STEP	7.5	23.2	113.5	3 ms	74.7	45.9	15.1	0.7	280.6
Simulation, STL	6.1	18.1	102.4	2 ms	70.5	7.1	15.1	0.7	220.0
Simulation, OBJ	5.4	15.7	103.9	3 ms	80.4	102.5	15.7	0.7	324.2
Visual, GLB	5.7	15.7	103.4	3 ms	226.2	2.1	20.0	0.8	373.9
Visual, OBJ	5.6	15.5	101.3	2 ms	208.6	66.1	16.7	0.4	414.2

Board Repo: sporniket/kicad-conversions--atari-260-520-st-motherboard--c070231 Board: motherboard.kicad_pcb Complexity 371 / 1000 (size 286, features 85) KESE features through vias, slotted holes, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 331, 13,570, 1,159 Triangles, simulation 14,594,790 in 433 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 491 MB 3.9 GB STEP 2.5 GB 5.4 GB STL 730 MB 4.1 GB OBJ 1.6 GB 9.2 GB Visual GLB 332 MB 5.2 GB OBJ 1.1 GB 6.8 GB

25.23 motherboard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	9.7	28.3	176.2	8 ms	145.6	10.6	34.3	1.7	406.4
Simulation, STEP	9.6	28.1	186.8	5 ms	149.6	97.3	38.5	1.4	511.3
Simulation, STL	7.2	24.3	154.5	5 ms	110.9	17.4	26.9	0.8	342.0
Simulation, OBJ									exceeded 11 GB on a 15 GB machine (stopped there, not a KESE failure); it will be run again on a machine with more memory
Visual, GLB	7.2	24.0	153.5	4 ms	324.4	2.2	33.6	0.6	545.6
Visual, OBJ	8.0	25.4	154.5	4 ms	332.0	76.7	29.7	0.7	626.9

Board Repo: sporniket/kicad-conversions--atari-ste-motherboard--c300780-001 Board: motherboard.kicad_pcb Complexity 383 / 1000 (size 318, features 65) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, drill offsets, filled zones Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 554, 12,443, 1,817 Triangles, simulation 27,423,068 in 747 parts Verifier Simulation, OBJ: exceeded 11 GB on a 15 GB machine (stopped there, not a KESE failure); it will be run again on a machine with more memory

File type File size Peak memory used Simulation GLB 925 MB 5.9 GB STEP 3.7 GB 8.3 GB STL 1.4 GB 5.5 GB OBJ – 11 GB Visual GLB 453 MB 7.2 GB OBJ 1.5 GB 9.5 GB

25.24 leaf

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.3	4.5	11.7	1 ms	19.6	0.6	1.8	0.3	39.8
Simulation, STEP	1.1	5.0	11.7	1 ms	19.0	11.4	1.8	0.3	50.3
Simulation, STL	1.0	4.5	11.9	2 ms	18.6	1.3	1.7	0.3	39.4
Simulation, OBJ	1.1	4.6	11.7	1 ms	19.4	19.5	1.7	0.3	58.3
Visual, GLB	1.0	4.7	11.5	2 ms	40.9	0.4	4.2	0.3	63.0
Visual, OBJ	1.2	4.8	12.2	2 ms	41.5	14.6	5.2	0.3	79.9

Board Repo: sprhawk/leaf-rv1126 Board: leaf.kicad_pcb Complexity 418 / 1000 (size 313, features 105) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, copper drawings, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 6 File format KiCad 8 (20240108) Parts, tracks, vias 285, 4,899, 266 Triangles, simulation 4,149,684 in 578 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 138 MB 1.3 GB STEP 661 MB 1.7 GB STL 208 MB 1.4 GB OBJ 438 MB 2.7 GB Visual GLB 103 MB 1.7 GB OBJ 327 MB 2.1 GB

25.25 leaf-minipcie

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	2.4	5.8	1 ms	8.4	0.4	1.0	0.3	18.8
Simulation, STEP	0.7	2.5	5.9	1 ms	8.4	6.2	1.1	0.2	25.0
Simulation, STL	0.7	2.3	6.0	1 ms	8.5	0.9	1.0	0.3	19.6
Simulation, OBJ	0.7	2.3	6.2	1 ms	8.7	13.9	1.1	0.3	33.2
Visual, GLB	0.7	2.5	5.8	1 ms	22.9	0.3	2.7	0.2	35.1
Visual, OBJ	0.7	2.5	5.9	1 ms	23.2	9.6	2.9	0.2	45.0

Board Repo: sprhawk/leaf-rv1126 Board: leaf-minipcie.kicad_pcb Folder minipcie Complexity 371 / 1000 (size 281, features 90) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, copper drawings, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 6 File format KiCad 7 (20221018) Parts, tracks, vias 270, 369, 173 Triangles, simulation 2,581,276 in 515 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 85 MB 922 MB STEP 374 MB 1.0 GB STL 129 MB 1.0 GB OBJ 270 MB 1.7 GB Visual GLB 58 MB 1.1 GB OBJ 183 MB 1.2 GB

25.26 hadbadge2019

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.0	5.7	19.0	0.8 ms	18.6	0.9	2.3	0.3	47.7
Simulation, STEP	1.1	5.4	19.3	2 ms	18.2	10.9	2.3	0.3	57.4
Simulation, STL	0.9	5.4	18.5	1 ms	18.4	1.5	2.5	0.3	47.3
Simulation, OBJ	1.1	5.4	18.6	1 ms	18.2	23.0	2.7	0.3	69.1
Visual, GLB	1.0	5.7	19.6	1 ms	37.9	0.4	4.4	0.3	69.3
Visual, OBJ	1.0	5.5	18.9	1 ms	35.1	15.1	4.0	0.3	79.8

Board Repo: Spritetm/hadbadge2019_pcb Board: hadbadge2019.kicad_pcb Complexity 366 / 1000 (size 281, features 85) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, drill offsets, filled zones, copper text, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 184, 3,746, 393 Triangles, simulation 3,996,450 in 324 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 141 MB 1.1 GB STEP 659 MB 1.5 GB STL 200 MB 1.1 GB OBJ 437 MB 2.6 GB Visual GLB 90 MB 1.5 GB OBJ 285 MB 1.9 GB

25.27 beepy

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.4	5.1	0.5 ms	5.6	0.2	0.6	0.2	13.7
Simulation, STEP	0.5	1.4	5.1	0.4 ms	5.8	4.6	0.6	0.2	18.2
Simulation, STL	0.5	1.5	5.2	0.5 ms	5.6	0.4	0.6	0.2	14.0
Simulation, OBJ	0.5	1.3	5.1	0.6 ms	5.8	7.5	0.7	0.2	21.0
Visual, GLB	0.5	1.4	5.0	0.5 ms	12.1	0.2	1.1	0.2	20.5
Visual, OBJ	0.5	1.4	5.0	0.6 ms	12.5	5.3	1.6	0.2	26.5

Board Repo: sqfmi/beepy-hardware Board: beepy.kicad_pcb Folder KiCad Complexity 377 / 1000 (size 247, features 130) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 95, 1,444, 157 Triangles, simulation 1,517,110 in 125 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 52 MB 612 MB STEP 239 MB 685 MB STL 76 MB 601 MB OBJ 157 MB 1.0 GB Visual GLB 35 MB 749 MB OBJ 108 MB 828 MB

25.28 Watchy

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	0.8	4.3	0.3 ms	3.1	0.2	0.5	0.3	9.5
Simulation, STEP	0.4	0.8	4.1	0.3 ms	3.0	2.5	0.4	0.3	11.5
Simulation, STL	0.3	0.8	4.3	0.3 ms	3.1	0.2	0.4	0.3	9.5
Simulation, OBJ	0.3	0.8	4.4	0.3 ms	3.1	4.6	0.4	0.2	13.9
Visual, GLB	0.3	0.8	4.3	0.3 ms	6.4	80 ms	0.6	0.3	12.7
Visual, OBJ	0.3	0.9	4.2	0.4 ms	6.8	3.0	0.8	0.3	16.2

Board Repo: sqfmi/watchy-hardware Board: Watchy.kicad_pcb Complexity 344 / 1000 (size 234, features 110) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 75, 697, 108 Triangles, simulation 784,726 in 97 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 27 MB 404 MB STEP 121 MB 471 MB STL 39 MB 395 MB OBJ 81 MB 575 MB Visual GLB 16 MB 433 MB OBJ 49 MB 440 MB

25.29 inteli210AT

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.0	4.0	0.3 ms	4.2	0.2	0.4	0.2	10.2
Simulation, STEP	0.3	1.0	4.0	0.3 ms	4.1	2.5	0.4	0.2	12.6
Simulation, STL	0.3	1.0	3.8	0.3 ms	4.3	0.3	0.5	0.3	10.5
Simulation, OBJ	0.3	1.0	4.0	0.5 ms	4.0	4.8	0.4	0.2	14.7
Visual, GLB	0.3	0.9	3.8	0.3 ms	6.7	81 ms	0.7	0.3	12.8
Visual, OBJ	0.3	1.0	3.9	0.3 ms	6.8	3.2	0.8	0.2	16.1

Board Repo: ssmiao/intel-i210-network-card Board: inteli210AT.kicad_pcb Folder PCBV3.0 Complexity 309 / 1000 (size 244, features 65) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 52, 2,120, 111 Triangles, simulation 959,846 in 71 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 33 MB 424 MB STEP 150 MB 525 MB STL 48 MB 433 MB OBJ 98 MB 687 MB Visual GLB 20 MB 533 MB OBJ 59 MB 547 MB

25.30 V1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.6	1.7	0.3 ms	1.9	0.1	0.3	0.3	5.0
Simulation, STEP	0.2	0.5	1.7	0.2 ms	1.8	1.5	0.2	0.2	6.2
Simulation, STL	0.2	0.5	1.7	0.3 ms	1.7	0.1	0.3	0.2	4.6
Simulation, OBJ	0.2	0.5	1.6	0.3 ms	1.7	2.2	0.3	0.2	6.7
Visual, GLB	0.2	0.6	1.8	0.3 ms	4.0	60 ms	0.5	0.2	7.4
Visual, OBJ	0.2	0.5	1.7	0.4 ms	4.0	1.7	0.7	0.2	9.1

Board Repo: ssmiao/intel-i210-network-card Board: V1.kicad_pcb Folder PCBV3.0 / reference / OCP2PCIe-master / OCP2PCIe-H-F-4 / OCP2PCIe-H-F-4-V0.1Beta Complexity 214 / 1000 (size 149, features 65) KESE features through vias, rounded, trapezoid or chamfered pads, drill offsets, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 12, 286, 95 Triangles, simulation 483,816 in 79 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 17 MB 288 MB STEP 72 MB 353 MB STL 24 MB 299 MB OBJ 50 MB 385 MB Visual GLB 13 MB 348 MB OBJ 38 MB 357 MB

25.31 V1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.5	1.8	0.2 ms	1.6	80 ms	0.3	0.2	4.7
Simulation, STEP	0.2	0.5	1.6	0.3 ms	1.6	1.5	0.2	0.2	5.9
Simulation, STL	0.2	0.5	1.6	0.2 ms	1.6	0.1	0.2	0.2	4.5
Simulation, OBJ	0.2	0.5	1.6	0.2 ms	1.7	2.4	0.2	0.2	6.8
Visual, GLB	0.2	0.5	1.6	0.5 ms	3.9	78 ms	0.5	0.2	7.0
Visual, OBJ	0.2	0.5	1.7	0.2 ms	3.9	1.9	0.5	0.2	8.9

Board Repo: ssmiao/intel-i210-network-card Board: V1.kicad_pcb Folder PCBV3.0 / reference / OCP2PCIe-master / OCP2PCIe-H-F-4 / OCP2PCIe-H-F-4-V1.0Beta Complexity 213 / 1000 (size 148, features 65) KESE features through vias, rounded, trapezoid or chamfered pads, drill offsets, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 12, 273, 92 Triangles, simulation 484,314 in 81 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 17 MB 290 MB STEP 72 MB 348 MB STL 24 MB 294 MB OBJ 50 MB 386 MB Visual GLB 13 MB 344 MB OBJ 38 MB 347 MB

25.32 v1-cut10x10

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.7	2.0	0.3 ms	2.1	98 ms	0.3	0.2	5.6
Simulation, STEP	0.2	0.6	2.1	0.3 ms	2.1	2.1	0.3	0.2	7.7
Simulation, STL	0.3	0.7	2.2	0.4 ms	2.2	0.2	0.3	0.2	6.1
Simulation, OBJ	0.3	0.7	2.1	0.2 ms	2.3	2.9	0.3	0.3	8.9
Visual, GLB	0.3	0.7	2.1	0.3 ms	5.0	77 ms	0.5	0.2	8.8
Visual, OBJ	0.3	0.7	2.4	0.3 ms	5.5	2.4	0.6	0.2	12.1

Board Repo: ssmiao/intel-i210-network-card Board: v1-cut10x10.kicad_pcb Folder PCBV3.0 / reference / OCP2PCIe-master / OCP2PCIe-H-F-4 / OCP2PCIe-H-F-4-V1.1Beta Complexity 215 / 1000 (size 150, features 65) KESE features through vias, rounded, trapezoid or chamfered pads, drill offsets, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 12, 349, 97 Triangles, simulation 509,670 in 81 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 18 MB 300 MB STEP 78 MB 361 MB STL 25 MB 303 MB OBJ 52 MB 406 MB Visual GLB 14 MB 355 MB OBJ 41 MB 373 MB

25.33 V1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.6	1.7	0.3 ms	1.8	70 ms	0.2	0.2	4.8
Simulation, STEP	0.2	0.5	1.8	0.3 ms	1.8	1.5	0.2	0.2	6.2
Simulation, STL	0.2	0.5	1.8	0.2 ms	1.8	0.1	0.2	0.2	4.9
Simulation, OBJ	0.2	0.5	1.8	0.2 ms	1.8	2.6	0.2	0.2	7.3
Visual, GLB	0.2	0.6	1.7	0.2 ms	3.8	56 ms	0.4	0.2	7.0
Visual, OBJ	0.2	0.5	1.7	0.3 ms	3.9	2.0	0.5	0.2	9.0

Board Repo: ssmiao/intel-i210-network-card Board: V1.kicad_pcb Folder PCBV3.0 / reference / OCP2PCIe-master / OCP2PCIe-H-F-4 / OCP2PCIe-H-F-4-V1.1Beta Complexity 215 / 1000 (size 150, features 65) KESE features through vias, rounded, trapezoid or chamfered pads, drill offsets, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 12, 349, 97 Triangles, simulation 513,356 in 81 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 18 MB 307 MB STEP 79 MB 370 MB STL 26 MB 312 MB OBJ 53 MB 344 MB Visual GLB 14 MB 363 MB OBJ 41 MB 367 MB

25.34 V1-cut10x10

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.8	3.1	0.4 ms	2.5	0.1	0.4	0.2	7.4
Simulation, STEP	0.3	0.8	3.1	0.3 ms	2.6	1.9	0.4	0.2	9.3
Simulation, STL	0.2	0.8	3.0	0.6 ms	2.8	0.2	0.4	0.2	7.7
Simulation, OBJ	0.2	0.9	3.0	0.3 ms	2.5	3.7	0.4	0.3	11.0
Visual, GLB	0.3	0.9	3.3	0.5 ms	5.5	75 ms	0.5	0.3	10.8
Visual, OBJ	0.3	1.0	3.0	0.3 ms	6.1	3.0	0.8	0.3	14.3

Board Repo: ssmiao/intel-i210-network-card Board: V1-cut10x10.kicad_pcb Folder PCBV3.0 / reference / OCP2PCIe-master / OCP2PCIe-H-F-4 / OCP2PCIe-H-F-4-V2.0Beta Complexity 230 / 1000 (size 155, features 75) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, drill offsets, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 10, 361, 195 Triangles, simulation 599,728 in 82 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 21 MB 330 MB STEP 82 MB 397 MB STL 30 MB 327 MB OBJ 61 MB 456 MB Visual GLB 16 MB 388 MB OBJ 46 MB 399 MB

25.35 V1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.8	2.9	0.4 ms	2.1	96 ms	0.3	0.2	6.6
Simulation, STEP	0.2	0.7	2.9	0.3 ms	2.1	1.6	0.3	0.2	8.1
Simulation, STL	0.2	0.8	2.9	0.4 ms	2.1	0.1	0.3	0.2	6.6
Simulation, OBJ	0.2	0.7	2.8	0.3 ms	2.1	3.2	0.4	0.2	9.6
Visual, GLB	0.2	0.7	2.9	0.4 ms	4.4	66 ms	0.4	0.2	8.9
Visual, OBJ	0.2	0.7	3.0	0.5 ms	4.4	2.4	0.7	0.2	11.6

Board Repo: ssmiao/intel-i210-network-card Board: V1.kicad_pcb Folder PCBV3.0 / reference / OCP2PCIe-master / OCP2PCIe-H-F-4 / OCP2PCIe-H-F-4-V2.0Beta Complexity 230 / 1000 (size 155, features 75) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, drill offsets, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 10, 361, 195 Triangles, simulation 606,444 in 82 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 21 MB 327 MB STEP 83 MB 411 MB STL 30 MB 326 MB OBJ 62 MB 451 MB Visual GLB 16 MB 392 MB OBJ 47 MB 407 MB

25.36 m5-pantilt

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.6	2.8	0.2 ms	1.9	86 ms	0.3	0.2	6.1
Simulation, STEP	0.2	0.6	2.6	0.3 ms	1.9	1.9	0.3	0.2	7.7
Simulation, STL	0.2	0.6	2.6	0.2 ms	1.9	0.1	0.3	0.2	6.0
Simulation, OBJ	0.3	0.6	2.7	0.2 ms	1.9	3.2	0.3	0.2	9.1
Visual, GLB	0.3	0.6	2.5	0.2 ms	4.6	71 ms	0.4	0.2	8.7
Visual, OBJ	0.2	0.6	2.6	0.2 ms	4.7	2.6	0.5	0.2	11.5

Board Repo: stack-chan/stack-chan Board: m5-pantilt.kicad_pcb Folder schematics / m5-pantilt Complexity 217 / 1000 (size 162, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 37, 285, 114 Triangles, simulation 565,966 in 53 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 20 MB 343 MB STEP 101 MB 371 MB STL 28 MB 359 MB OBJ 58 MB 379 MB Visual GLB 16 MB 399 MB OBJ 47 MB 412 MB

25.37 aerolotl_av

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.1	3.5	13.5	1 ms	16.2	0.5	1.8	0.3	36.9
Simulation, STEP	1.0	3.7	13.6	0.5 ms	16.0	9.6	1.7	0.3	45.8
Simulation, STL	1.1	3.6	13.5	0.9 ms	16.5	1.0	1.8	0.2	37.7
Simulation, OBJ	1.0	3.6	13.5	0.4 ms	16.5	18.7	1.9	0.3	55.3
Visual, GLB	1.0	3.7	13.3	1.0 ms	28.4	0.3	3.8	0.3	50.8
Visual, OBJ	1.0	3.6	13.1	0.5 ms	28.7	12.3	4.0	0.3	63.1

Board Repo: stanford-ssi/aerolotl_av Board: aerolotl_av.kicad_pcb Complexity 359 / 1000 (size 264, features 95) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 10 (20260206) Parts, tracks, vias 163, 1,889, 639 Triangles, simulation 3,503,362 in 181 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 119 MB 1.1 GB STEP 465 MB 1.5 GB STL 175 MB 1.1 GB OBJ 375 MB 2.3 GB Visual GLB 79 MB 1.4 GB OBJ 253 MB 1.7 GB

25.38 aerolotl

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	1.5	5.2	0.8 ms	4.5	0.2	0.5	0.3	12.8
Simulation, STEP	0.5	1.3	5.3	0.8 ms	4.4	3.6	0.5	0.3	15.9
Simulation, STL	0.5	1.4	5.4	0.9 ms	4.3	0.3	0.5	0.3	12.6
Simulation, OBJ	0.5	1.4	5.1	0.6 ms	4.1	5.7	0.5	0.3	17.5
Visual, GLB	0.5	1.3	5.4	0.5 ms	10.5	0.1	1.0	0.2	19.0
Visual, OBJ	0.5	1.3	4.9	0.5 ms	10.0	4.7	1.2	0.2	22.9

Board Repo: stanford-ssi/aerolotl_kicad Board: aerolotl.kicad_pcb Complexity 189 / 1000 (size 129, features 60) KESE features slotted holes, rounded, trapezoid or chamfered pads, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 10 (20260206) Parts, tracks, vias 173, 0, 0 Triangles, simulation 982,128 in 184 parts Note mostly unrouted Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 34 MB 476 MB STEP 140 MB 603 MB STL 49 MB 474 MB OBJ 103 MB 747 MB Visual GLB 28 MB 600 MB OBJ 84 MB 684 MB

25.39 battery_pcb

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	0.9	3.6	0.4 ms	2.8	0.1	0.4	0.2	8.5
Simulation, STEP	0.4	0.9	3.5	0.4 ms	2.7	2.4	0.4	0.2	10.5
Simulation, STL	0.4	0.9	3.6	0.4 ms	2.7	0.2	0.4	0.2	8.4
Simulation, OBJ	0.4	0.9	3.6	0.6 ms	2.9	4.4	0.4	0.2	12.9
Visual, GLB	0.4	0.9	3.5	0.5 ms	6.5	94 ms	0.6	0.2	12.2
Visual, OBJ	0.4	0.9	3.5	0.3 ms	6.6	3.4	0.6	0.2	15.6

Board Repo: stanford-ssi/aerolotl_kicad Board: battery_pcb.kicad_pcb Folder BatteryPCB Complexity 239 / 1000 (size 159, features 80) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 10 (20260206) Parts, tracks, vias 42, 126, 123 Triangles, simulation 797,334 in 67 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 27 MB 384 MB STEP 126 MB 470 MB STL 40 MB 381 MB OBJ 81 MB 571 MB Visual GLB 21 MB 533 MB OBJ 63 MB 536 MB

25.40 battery_pcb_30pin

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.7	2.8	0.6 ms	2.4	0.1	0.4	0.2	6.9
Simulation, STEP	0.3	0.8	2.7	0.4 ms	2.3	2.1	0.3	0.2	8.7
Simulation, STL	0.3	0.7	2.7	0.4 ms	2.4	0.2	0.3	0.2	6.9
Simulation, OBJ	0.3	0.7	2.7	0.4 ms	2.4	3.2	0.3	0.2	9.8
Visual, GLB	0.3	0.7	2.7	0.4 ms	5.6	82 ms	0.6	0.2	10.3
Visual, OBJ	0.3	0.7	2.8	1 ms	5.6	2.5	0.8	0.2	12.9

Board Repo: stanford-ssi/aerolotl_kicad Board: battery_pcb_30pin.kicad_pcb Folder BatteryPCB_30pin Complexity 240 / 1000 (size 160, features 80) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 10 (20260206) Parts, tracks, vias 42, 153, 122 Triangles, simulation 788,398 in 60 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 27 MB 389 MB STEP 127 MB 464 MB STL 39 MB 397 MB OBJ 80 MB 580 MB Visual GLB 21 MB 485 MB OBJ 63 MB 489 MB

25.41 seed_user_1224

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.6	1.9	0.4 ms	1.7	82 ms	0.3	0.2	4.9
Simulation, STEP	0.2	0.6	2.0	0.3 ms	1.8	1.6	0.3	0.2	6.5
Simulation, STL	0.2	0.5	2.0	0.4 ms	1.7	0.1	0.3	0.2	5.0
Simulation, OBJ	0.2	0.6	2.0	0.3 ms	1.8	2.6	0.3	0.2	7.5
Visual, GLB	0.2	0.6	2.0	0.4 ms	4.3	61 ms	0.6	0.2	7.8
Visual, OBJ	0.2	0.5	1.9	0.6 ms	4.2	1.9	0.6	0.2	9.7

Board Repo: stanford-ssi/aerolotl_kicad Board: seed_user_1224.kicad_pcb Folder BatteryPCB_30pin / tools / layoutA Complexity 213 / 1000 (size 158, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 10 (20260206) Parts, tracks, vias 35, 89, 147 Triangles, simulation 636,314 in 65 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 21 MB 371 MB STEP 81 MB 410 MB STL 32 MB 342 MB OBJ 63 MB 462 MB Visual GLB 16 MB 431 MB OBJ 49 MB 428 MB

25.42 motor_board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.9	3.0	16.1	0.5 ms	12.6	0.5	1.4	0.3	34.8
Simulation, STEP	0.9	3.0	16.0	0.9 ms	13.0	7.9	1.3	0.2	42.4
Simulation, STL	0.8	3.0	16.8	0.5 ms	13.0	1.2	1.4	0.3	36.6
Simulation, OBJ	0.9	3.1	17.1	0.5 ms	13.2	17.9	1.5	0.3	54.0
Visual, GLB	0.9	3.2	17.1	0.5 ms	28.3	0.3	2.5	0.3	52.4
Visual, OBJ	0.8	3.2	16.9	0.5 ms	27.6	10.6	2.6	0.2	62.1

Board Repo: stanford-ssi/samwise-avionics Board: motor_board.kicad_pcb Folder ADCS / ADCS-motors-v1-samwise Complexity 359 / 1000 (size 259, features 100) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 161, 1,571, 412 Triangles, simulation 3,264,640 in 197 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 114 MB 1.1 GB STEP 523 MB 1.3 GB STL 163 MB 1.1 GB OBJ 356 MB 2.2 GB Visual GLB 70 MB 1.3 GB OBJ 221 MB 1.6 GB

25.43 ADCS_board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.0	3.6	20.4	1 ms	14.2	0.6	1.7	0.3	41.8
Simulation, STEP	0.9	3.8	20.4	0.9 ms	14.6	9.3	1.9	0.3	51.2
Simulation, STL	1.1	3.4	20.0	1 ms	14.8	1.1	1.9	0.3	42.6
Simulation, OBJ	1.0	3.6	20.1	1 ms	14.6	17.5	1.9	0.4	59.1
Visual, GLB	1.0	3.5	21.4	2 ms	30.0	0.3	4.3	0.2	60.9
Visual, OBJ	1.0	3.7	20.6	1 ms	31.7	11.2	4.4	0.3	72.8

Board Repo: stanford-ssi/samwise-avionics Board: ADCS_board.kicad_pcb Folder ADCS / ADCS-v1-samwise Complexity 393 / 1000 (size 268, features 125) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 188, 1,511, 471 Triangles, simulation 3,615,090 in 210 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 128 MB 1.2 GB STEP 600 MB 1.5 GB STL 181 MB 1.2 GB OBJ 397 MB 2.5 GB Visual GLB 83 MB 1.4 GB OBJ 263 MB 1.8 GB

25.44 batteryboard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.7	3.0	0.2 ms	1.8	93 ms	0.3	0.2	6.4
Simulation, STEP	0.3	0.7	2.7	0.2 ms	1.8	1.9	0.3	0.2	8.0
Simulation, STL	0.4	0.7	2.9	0.2 ms	1.9	0.2	0.3	0.3	6.6
Simulation, OBJ	0.3	0.7	2.8	0.2 ms	1.8	3.5	0.3	0.2	9.6
Visual, GLB	0.3	0.8	2.7	0.2 ms	4.1	92 ms	0.5	0.2	8.8
Visual, OBJ	0.4	0.8	3.2	0.2 ms	4.4	2.3	0.6	0.2	11.8

Board Repo: stanford-ssi/samwise-avionics Board: batteryboard.kicad_pcb Folder BatteryBoard / batteryboard-v02.3 Complexity 270 / 1000 (size 180, features 90) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 30, 596, 61 Triangles, simulation 635,618 in 36 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 23 MB 369 MB STEP 109 MB 391 MB STL 32 MB 368 MB OBJ 66 MB 497 MB Visual GLB 15 MB 392 MB OBJ 45 MB 407 MB

25.45 FlexDeploySidePanels

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	1.6	4.6	0.4 ms	4.7	0.2	0.6	0.2	12.7
Simulation, STEP	0.8	1.6	4.5	0.4 ms	4.6	3.8	0.6	0.2	16.0
Simulation, STL	0.7	1.6	4.5	0.4 ms	4.4	0.3	0.6	0.2	12.4
Simulation, OBJ	0.7	1.6	4.5	0.4 ms	4.4	7.7	0.6	0.2	19.9
Visual, GLB	0.7	1.7	4.5	0.3 ms	8.3	0.1	1.0	0.3	16.6
Visual, OBJ	0.8	1.7	4.6	0.5 ms	8.6	4.2	1.3	0.2	21.4

Board Repo: stanford-ssi/samwise-avionics Board: FlexDeploySidePanels.kicad_pcb Folder FlexDeploySidePanels Complexity 291 / 1000 (size 186, features 105) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 127, 367, 23 Triangles, simulation 1,448,826 in 60 parts Note panel Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 50 MB 578 MB STEP 162 MB 648 MB STL 72 MB 587 MB OBJ 153 MB 993 MB Visual GLB 29 MB 701 MB OBJ 88 MB 668 MB

25.46 Groundstation_2400_Hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.6	2.4	0.4 ms	1.9	92 ms	0.3	0.2	5.7
Simulation, STEP	0.2	0.6	2.3	0.3 ms	1.8	1.6	0.3	0.3	7.1
Simulation, STL	0.2	0.6	2.3	0.3 ms	1.8	0.1	0.3	0.2	5.6
Simulation, OBJ	0.2	0.6	2.3	0.4 ms	1.8	3.2	0.4	0.2	8.6
Visual, GLB	0.2	0.6	2.4	0.3 ms	3.9	52 ms	0.5	0.2	7.8
Visual, OBJ	0.3	0.6	2.3	0.3 ms	4.2	1.9	0.5	0.2	9.9

Board Repo: stanford-ssi/samwise-avionics Board: Groundstation_2400_Hat.kicad_pcb Folder Groundstation_2400_Hat Complexity 237 / 1000 (size 147, features 90) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 10, 91, 38 Triangles, simulation 563,868 in 50 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 19 MB 297 MB STEP 64 MB 342 MB STL 28 MB 304 MB OBJ 57 MB 414 MB Visual GLB 11 MB 330 MB OBJ 34 MB 337 MB

25.47 Groundstation_433_Hat

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.7	3.5	0.3 ms	2.7	0.1	0.5	0.2	8.1
Simulation, STEP	0.2	0.7	3.6	0.3 ms	2.7	2.5	0.6	0.3	10.5
Simulation, STL	0.2	0.8	3.5	0.4 ms	2.6	0.2	0.5	0.3	8.1
Simulation, OBJ	0.2	0.7	3.4	0.3 ms	2.7	4.8	0.6	0.2	12.7
Visual, GLB	0.2	0.7	3.6	0.3 ms	5.2	71 ms	0.6	0.3	10.7
Visual, OBJ	0.2	0.8	3.5	0.3 ms	5.5	2.2	0.6	0.2	13.1

Board Repo: stanford-ssi/samwise-avionics Board: Groundstation_433_Hat.kicad_pcb Folder Groundstation_433_Hat Complexity 237 / 1000 (size 147, features 90) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 14, 149, 8 Triangles, simulation 759,192 in 48 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 26 MB 341 MB STEP 112 MB 387 MB STL 38 MB 347 MB OBJ 78 MB 540 MB Visual GLB 13 MB 378 MB OBJ 39 MB 381 MB

25.48 LT8491-mezzanine

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.6	4.4	0.5 ms	4.8	0.2	0.7	0.2	12.4
Simulation, STEP	0.4	1.5	4.4	0.4 ms	5.0	3.6	0.7	0.2	15.9
Simulation, STL	0.4	1.5	4.5	0.4 ms	4.9	0.5	0.7	0.2	12.8
Simulation, OBJ	0.5	1.5	4.6	0.5 ms	4.9	7.6	0.7	0.2	20.0
Visual, GLB	0.5	1.4	4.6	0.8 ms	9.8	0.1	1.0	0.2	17.5
Visual, OBJ	0.5	1.5	4.7	0.5 ms	9.8	4.2	1.0	0.2	21.9

Board Repo: stanford-ssi/samwise-avionics Board: LT8491-mezzanine.kicad_pcb Folder LT8491-mezzanine Complexity 356 / 1000 (size 211, features 145) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours, castellated pads Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 122, 673, 165 Triangles, simulation 1,503,708 in 105 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 51 MB 525 MB STEP 196 MB 662 MB STL 75 MB 553 MB OBJ 157 MB 1.0 GB Visual GLB 28 MB 713 MB OBJ 85 MB 707 MB

25.49 magnetometer_extern

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	89 ms	56 ms	0.3	0.1 ms	0.5	15 ms	46 ms	0.2	1.2
Simulation, STEP	93 ms	74 ms	0.3	0.2 ms	0.5	0.8	56 ms	0.2	2.1
Simulation, STL	94 ms	64 ms	0.3	0.1 ms	0.5	21 ms	47 ms	0.2	1.3
Simulation, OBJ	82 ms	57 ms	0.3	0.1 ms	0.5	0.4	54 ms	0.2	1.6
Visual, GLB	85 ms	58 ms	0.3	0.2 ms	1.0	16 ms	0.1	0.3	1.8
Visual, OBJ	88 ms	59 ms	0.3	0.1 ms	1.0	0.2	76 ms	0.3	2.0

Board Repo: stanford-ssi/samwise-avionics Board: magnetometer_extern.kicad_pcb Folder magnetometer_extern / magnetometer_extern Complexity 106 / 1000 (size 76, features 30) KESE features rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 4, 12, 0 Triangles, simulation 78,032 in 18 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 2.6 MB 173 MB STEP 11 MB 180 MB STL 3.9 MB 173 MB OBJ 7.3 MB 175 MB Visual GLB 1.7 MB 150 MB OBJ 4.6 MB 150 MB

25.50 MPPT_addon_board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.4	6.4	0.5 ms	4.6	0.2	0.5	0.3	13.7
Simulation, STEP	0.4	1.2	6.6	0.4 ms	4.3	3.0	0.4	0.3	16.3
Simulation, STL	0.4	1.2	6.2	0.3 ms	3.6	0.2	0.4	0.3	12.3
Simulation, OBJ	0.4	1.3	7.2	0.6 ms	3.8	4.7	0.4	0.2	18.1
Visual, GLB	0.3	1.1	6.2	0.4 ms	7.6	0.1	0.8	0.2	16.4
Visual, OBJ	0.4	1.4	6.4	0.4 ms	7.4	3.9	0.9	0.3	20.8

Board Repo: stanford-ssi/samwise-avionics Board: MPPT_addon_board.kicad_pcb Folder PiCubed / MPPT_addon_board Complexity 257 / 1000 (size 167, features 90) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 48, 433, 105 Triangles, simulation 739,358 in 61 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 27 MB 417 MB STEP 145 MB 494 MB STL 37 MB 420 MB OBJ 78 MB 560 MB Visual GLB 22 MB 509 MB OBJ 64 MB 510 MB

25.51 picubed_samwise

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	3.7	16.0	2 ms	11.6	0.5	1.9	0.3	34.9
Simulation, STEP	0.9	3.4	16.3	1 ms	11.8	8.6	1.9	0.3	43.1
Simulation, STL	1.0	3.9	16.4	2 ms	12.3	1.1	2.1	0.3	37.2
Simulation, OBJ	1.2	4.0	16.8	1 ms	12.4	16.9	1.9	0.3	53.6
Visual, GLB	1.0	4.0	16.6	1 ms	28.9	0.3	4.0	0.3	55.1
Visual, OBJ	1.0	4.2	17.7	1 ms	30.5	11.2	3.8	0.3	68.7

Board Repo: stanford-ssi/samwise-avionics Board: picubed_samwise.kicad_pcb Folder PiCubed / picubed_samwise Complexity 380 / 1000 (size 255, features 125) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 179, 1,266, 289 Triangles, simulation 3,389,692 in 178 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 119 MB 1.0 GB STEP 579 MB 1.3 GB STL 169 MB 1.0 GB OBJ 371 MB 2.3 GB Visual GLB 73 MB 1.3 GB OBJ 231 MB 1.5 GB

25.52 RPi_interface

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	1.7	4.6	0.4 ms	4.2	0.2	0.6	0.2	12.1
Simulation, STEP	0.7	1.7	4.7	0.3 ms	4.4	3.1	0.6	0.2	15.4
Simulation, STL	0.7	1.6	4.6	0.3 ms	4.2	0.3	0.6	0.2	12.3
Simulation, OBJ	0.7	1.6	4.6	0.5 ms	4.1	7.0	0.6	0.2	18.8
Visual, GLB	0.7	1.6	4.7	1 ms	9.0	0.1	1.0	0.2	17.3
Visual, OBJ	0.7	1.7	4.7	0.3 ms	8.4	4.4	0.9	0.2	21.0

Board Repo: stanford-ssi/samwise-avionics Board: RPi_interface.kicad_pcb Folder RPi_Interface Complexity 272 / 1000 (size 182, features 90) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 38, 340, 145 Triangles, simulation 1,287,604 in 63 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 45 MB 548 MB STEP 175 MB 633 MB STL 64 MB 578 MB OBJ 135 MB 908 MB Visual GLB 30 MB 631 MB OBJ 91 MB 698 MB

25.53 Stationary_X_Panel

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.7	2.2	0.3 ms	1.3	78 ms	0.2	0.2	4.9
Simulation, STEP	0.2	0.7	1.9	0.2 ms	1.3	1.6	0.3	0.2	6.2
Simulation, STL	0.2	0.6	2.0	0.3 ms	1.4	0.1	0.2	0.2	4.7
Simulation, OBJ	0.2	0.6	1.9	0.2 ms	1.3	2.6	0.3	0.2	7.0
Visual, GLB	0.3	0.7	1.9	0.2 ms	4.4	68 ms	0.5	0.3	8.1
Visual, OBJ	0.3	0.6	2.0	0.3 ms	4.1	2.3	0.5	0.2	9.9

Board Repo: stanford-ssi/samwise-avionics Board: Stationary_X_Panel.kicad_pcb Folder Stationary_X_Panel Complexity 245 / 1000 (size 150, features 95) KESE features through vias, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 41, 239, 16 Triangles, simulation 439,218 in 38 parts Note panel Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 15 MB 287 MB STEP 66 MB 328 MB STL 22 MB 291 MB OBJ 45 MB 333 MB Visual GLB 13 MB 358 MB OBJ 39 MB 360 MB

25.54 Piramide_Del_Sol

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.7	0.1 ms	1.0	29 ms	81 ms	0.2	2.4
Simulation, STEP	0.1	0.2	0.8	0.1 ms	1.0	0.9	82 ms	0.2	3.3
Simulation, STL	0.1	0.2	0.7	0.1 ms	0.9	41 ms	76 ms	0.2	2.3
Simulation, OBJ	0.1	0.2	0.8	0.1 ms	1.0	0.9	79 ms	0.2	3.2
Visual, GLB	0.1	0.2	0.8	0.1 ms	1.7	28 ms	0.2	0.2	3.2
Visual, OBJ	0.1	0.2	0.8	0.2 ms	1.8	0.7	0.2	0.2	4.0

Board Repo: stanford-ssi/samwise-avionics Board: Piramide_Del_Sol.kicad_pcb Folder sun_sensor_pyramid Complexity 230 / 1000 (size 140, features 90) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 19, 125, 45 Triangles, simulation 181,334 in 19 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 6.4 MB 214 MB STEP 32 MB 239 MB STL 9.1 MB 215 MB OBJ 18 MB 214 MB Visual GLB 5.7 MB 216 MB OBJ 16 MB 225 MB

25.55 Coil_Panel_XY

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.3	0.6	0.1 ms	0.8	38 ms	0.1	0.2	2.1
Simulation, STEP	0.1	0.3	0.6	0.1 ms	0.8	0.9	0.1	0.2	3.0
Simulation, STL	0.1	0.3	0.5	0.2 ms	0.8	58 ms	0.1	0.2	2.2
Simulation, OBJ	0.1	0.3	0.6	0.2 ms	0.8	1.2	0.1	0.2	3.3
Visual, GLB	0.1	0.3	0.6	0.2 ms	1.9	27 ms	0.2	0.2	3.4
Visual, OBJ	0.1	0.3	0.5	0.2 ms	2.0	0.8	0.3	0.2	4.2

Board Repo: stanford-ssi/samwise-avionics Board: Coil_Panel_XY.kicad_pcb Folder Universal_XY_MagTorq Complexity 245 / 1000 (size 185, features 60) KESE features through vias, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 9, 1,242, 9 Triangles, simulation 287,304 in 38 parts Note panel Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 9.7 MB 227 MB STEP 40 MB 249 MB STL 14 MB 230 MB OBJ 30 MB 237 MB Visual GLB 6.5 MB 198 MB OBJ 19 MB 224 MB

25.56 Coil_Panel_Z

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	0.4	0.2 ms	1.0	40 ms	0.1	0.2	2.2
Simulation, STEP	0.2	0.3	0.4	0.2 ms	0.9	1.2	0.1	0.2	3.4
Simulation, STL	0.2	0.3	0.4	0.2 ms	0.9	54 ms	0.1	0.2	2.2
Simulation, OBJ	0.2	0.3	0.4	0.2 ms	0.9	1.0	0.1	0.2	3.1
Visual, GLB	0.2	0.2	0.4	0.2 ms	1.9	29 ms	0.2	0.3	3.3
Visual, OBJ	0.2	0.3	0.4	0.2 ms	1.9	0.6	0.2	0.2	3.8

Board Repo: stanford-ssi/samwise-avionics Board: Coil_Panel_Z.kicad_pcb Folder Universal_Z_MagTorq / Coil_Panel_Z_v1 Complexity 229 / 1000 (size 179, features 50) KESE features through vias, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 7, 987, 9 Triangles, simulation 201,596 in 32 parts Note panel Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 7.0 MB 226 MB STEP 36 MB 222 MB STL 10 MB 223 MB OBJ 21 MB 210 MB Visual GLB 5.0 MB 198 MB OBJ 14 MB 198 MB

25.57 FeatherRadioAdapter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.4	1.3	0.2 ms	1.1	52 ms	0.2	0.2	3.3
Simulation, STEP	0.1	0.4	1.2	0.2 ms	1.0	1.2	0.2	0.2	4.3
Simulation, STL	0.1	0.4	1.2	0.2 ms	1.1	69 ms	0.2	0.2	3.2
Simulation, OBJ	0.1	0.4	1.2	0.3 ms	1.1	1.8	0.2	0.2	5.0
Visual, GLB	0.1	0.4	1.3	0.2 ms	2.2	24 ms	0.1	0.2	4.4
Visual, OBJ	0.1	0.4	1.2	0.2 ms	2.2	0.8	0.2	0.2	5.1

Board Repo: stanford-ssi/samwise-avionics Board: FeatherRadioAdapter.kicad_pcb Folder unused_boards / FeatherRadioAdapter Complexity 224 / 1000 (size 139, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 8, 90, 18 Triangles, simulation 349,674 in 46 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 12 MB 225 MB STEP 44 MB 248 MB STL 17 MB 226 MB OBJ 36 MB 254 MB Visual GLB 5.6 MB 211 MB OBJ 17 MB 208 MB

25.58 Pete_2400_Mini

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.5	2.1	0.2 ms	1.8	88 ms	0.3	0.2	5.1
Simulation, STEP	0.2	0.5	2.1	0.3 ms	1.8	1.6	0.4	0.2	6.8
Simulation, STL	0.2	0.6	2.2	0.2 ms	1.8	0.1	0.3	0.2	5.3
Simulation, OBJ	0.2	0.6	2.1	0.2 ms	1.8	3.1	0.4	0.2	8.3
Visual, GLB	0.2	0.5	2.2	0.4 ms	4.1	52 ms	0.4	0.2	7.8
Visual, OBJ	0.2	0.5	2.1	0.2 ms	4.0	1.9	0.6	0.2	9.5

Board Repo: stanford-ssi/samwise-avionics Board: Pete_2400_Mini.kicad_pcb Folder unused_boards / Pete_2400_Mini Complexity 261 / 1000 (size 151, features 110) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 12, 130, 35 Triangles, simulation 612,166 in 52 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 21 MB 324 MB STEP 79 MB 341 MB STL 31 MB 313 MB OBJ 63 MB 447 MB Visual GLB 13 MB 355 MB OBJ 37 MB 358 MB

25.59 reaction_wheel

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	1.4	0.2 ms	1.2	63 ms	0.2	0.2	3.5
Simulation, STEP	0.1	0.3	1.3	1.0 ms	1.2	1.5	0.2	0.2	4.8
Simulation, STL	0.1	0.3	1.2	0.2 ms	1.2	70 ms	0.2	0.2	3.3
Simulation, OBJ	0.2	0.3	1.0	0.3 ms	1.2	1.7	0.2	0.2	4.7
Visual, GLB	0.1	0.3	1.1	0.2 ms	2.4	35 ms	0.3	0.2	4.4
Visual, OBJ	0.1	0.3	1.2	0.3 ms	2.4	1.0	0.3	0.2	5.4

Board Repo: stanford-ssi/samwise-avionics Board: reaction_wheel.kicad_pcb Folder unused_boards / reaction_wheel_board Complexity 269 / 1000 (size 184, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 26, 189, 24 Triangles, simulation 293,658 in 40 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 10 MB 242 MB STEP 46 MB 269 MB STL 15 MB 239 MB OBJ 29 MB 256 MB Visual GLB 7.4 MB 242 MB OBJ 21 MB 247 MB

25.60 solar_charger

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.7	2.3	0.3 ms	2.2	0.1	0.5	0.2	6.1
Simulation, STEP	0.2	0.7	2.3	0.4 ms	2.1	2.0	0.5	0.2	7.9
Simulation, STL	0.2	0.7	2.3	0.3 ms	2.2	0.2	0.5	0.2	6.2
Simulation, OBJ	0.2	0.6	2.2	0.3 ms	2.1	3.3	0.5	0.3	9.2
Visual, GLB	0.2	0.6	2.3	0.3 ms	5.3	58 ms	0.6	0.2	9.2
Visual, OBJ	0.2	0.6	2.1	0.4 ms	5.3	1.9	0.6	0.2	10.9

Board Repo: stanford-ssi/samwise-avionics Board: solar_charger.kicad_pcb Folder unused_boards / solar_charger Complexity 232 / 1000 (size 147, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, drill offsets, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 15, 117, 15 Triangles, simulation 675,838 in 80 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 22 MB 336 MB STEP 85 MB 372 MB STL 34 MB 352 MB OBJ 67 MB 485 MB Visual GLB 12 MB 385 MB OBJ 37 MB 387 MB

25.61 ZPlus_Panel

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.9	2.6	0.3 ms	2.3	0.1	0.4	0.2	6.8
Simulation, STEP	0.3	1.0	2.6	0.4 ms	2.2	2.0	0.3	0.3	8.8
Simulation, STL	0.3	1.0	2.6	0.4 ms	2.3	0.2	0.3	0.2	7.0
Simulation, OBJ	0.3	0.9	2.5	0.2 ms	2.2	3.9	0.3	0.2	10.4
Visual, GLB	0.3	0.8	2.5	0.2 ms	4.7	72 ms	0.5	0.2	9.2
Visual, OBJ	0.3	0.9	2.6	0.3 ms	4.4	2.6	0.6	0.2	11.5

Board Repo: stanford-ssi/samwise-avionics Board: ZPlus_Panel.kicad_pcb Folder ZPlus_Panel Complexity 269 / 1000 (size 174, features 95) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 36, 157, 107 Triangles, simulation 680,728 in 31 parts Note panel Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 24 MB 363 MB STEP 84 MB 401 MB STL 34 MB 370 MB OBJ 71 MB 498 MB Visual GLB 16 MB 393 MB OBJ 48 MB 396 MB

25.62 MegaDrive

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.5	6.8	32.7	1 ms	38.3	1.2	4.4	0.3	85.2
Simulation, STEP	1.6	6.8	33.0	1 ms	38.7	21.3	4.5	0.4	106.3
Simulation, STL	1.6	6.9	32.9	1 ms	38.5	2.4	4.7	0.4	87.3
Simulation, OBJ	1.6	7.0	34.0	1 ms	38.9	41.8	4.7	0.3	128.5
Visual, GLB	1.7	6.9	32.8	1 ms	103.0	1.0	9.1	0.3	154.7
Visual, OBJ	1.7	7.6	40.2	2 ms	115.3	30.5	8.5	0.3	204.1

Board Repo: stonedDiscord/MegaDrive Board: MegaDrive.kicad_pcb Complexity 353 / 1000 (size 278, features 75) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 267, 9,611, 785 Triangles, simulation 7,235,902 in 344 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 246 MB 2.4 GB STEP 1.2 GB 2.8 GB STL 362 MB 2.5 GB OBJ 771 MB 4.6 GB Visual GLB 183 MB 2.9 GB OBJ 590 MB 3.6 GB

25.63 SNSP-CPU-01

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.7	6.9	27.8	1 ms	26.9	1.0	3.4	0.4	68.1
Simulation, STEP	1.8	6.8	27.8	1 ms	26.6	17.0	3.3	0.4	83.6
Simulation, STL	1.8	6.7	26.3	2 ms	27.6	2.0	3.4	0.4	68.2
Simulation, OBJ	1.8	6.7	26.3	2 ms	26.8	33.9	3.5	0.4	99.3
Visual, GLB	1.7	6.9	26.4	1 ms	73.3	0.9	7.7	0.4	117.3
Visual, OBJ	1.7	8.0	28.6	2 ms	74.5	29.1	7.1	0.3	149.3

Board Repo: stonedDiscord/nonSNES Board: SNSP-CPU-01.kicad_pcb Folder SNSP-CPU-01 Complexity 423 / 1000 (size 288, features 135) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 10 (20260206) Parts, tracks, vias 291, 8,639, 1,197 Triangles, simulation 5,578,300 in 446 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 192 MB 2.2 GB STEP 1.0 GB 2.2 GB STL 279 MB 2.0 GB OBJ 597 MB 3.6 GB Visual GLB 162 MB 2.6 GB OBJ 522 MB 3.3 GB

25.64 SNSP-CPU-1CHIP

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.1	4.3	15.6	0.6 ms	17.0	0.5	1.9	0.3	40.7
Simulation, STEP	1.0	4.0	14.9	0.6 ms	17.3	10.6	1.9	0.3	50.0
Simulation, STL	1.0	4.1	15.3	0.8 ms	16.8	1.2	1.8	0.3	40.5
Simulation, OBJ	1.0	4.1	14.7	0.6 ms	16.4	20.8	2.1	0.3	59.3
Visual, GLB	1.0	4.1	15.8	1 ms	41.9	0.5	5.2	0.3	68.8
Visual, OBJ	1.2	4.4	16.3	1 ms	41.2	18.2	6.0	0.3	87.6

Board Repo: stonedDiscord/nonSNES Board: SNSP-CPU-1CHIP.kicad_pcb Folder SNSP-CPU-1CHIP Complexity 408 / 1000 (size 263, features 145) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 10 (20260206) Parts, tracks, vias 178, 4,345, 686 Triangles, simulation 3,805,256 in 257 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 131 MB 1.4 GB STEP 696 MB 1.6 GB STL 190 MB 1.4 GB OBJ 406 MB 2.5 GB Visual GLB 107 MB 2.0 GB OBJ 341 MB 2.3 GB

25.65 ControllerCircuit

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.9	3.6	10.4	0.9 ms	8.1	0.4	1.0	0.3	24.6
Simulation, STEP	0.8	2.9	9.3	0.8 ms	7.0	5.5	0.9	0.3	26.7
Simulation, STL	0.8	3.1	9.7	0.9 ms	6.6	0.6	0.8	0.2	21.9
Simulation, OBJ	0.8	3.0	9.1	1 ms	6.8	9.7	0.9	0.3	30.6
Visual, GLB	0.8	3.1	9.2	1 ms	18.9	0.3	2.2	0.3	34.8
Visual, OBJ	0.8	3.1	9.2	1 ms	18.2	8.7	2.4	0.3	42.6

Board Repo: stuartpittaway/diybmsv4 Board: ControllerCircuit.kicad_pcb Folder ControllerCircuit Complexity 295 / 1000 (size 190, features 105) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, TrueType text Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 87, 925, 379 Triangles, simulation 2,089,958 in 115 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 73 MB 915 MB STEP 344 MB 978 MB STL 105 MB 903 MB OBJ 222 MB 1.4 GB Visual GLB 64 MB 1.1 GB OBJ 197 MB 1.3 GB

25.66 ControllerCurrentShuntAddOn

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	85 ms	0.1	0.5	0.1 ms	0.7	22 ms	72 ms	0.2	1.7
Simulation, STEP	89 ms	0.1	0.5	0.2 ms	0.6	0.8	66 ms	0.2	2.5
Simulation, STL	92 ms	0.1	0.5	0.2 ms	0.7	33 ms	62 ms	0.2	1.7
Simulation, OBJ	91 ms	0.2	0.5	0.1 ms	0.6	0.7	89 ms	0.2	2.4
Visual, GLB	98 ms	0.1	0.6	0.1 ms	1.3	18 ms	0.1	0.2	2.4
Visual, OBJ	90 ms	0.1	0.5	0.1 ms	1.3	0.5	0.1	0.2	2.8

Board Repo: stuartpittaway/diybmsv4 Board: ControllerCurrentShuntAddOn.kicad_pcb Folder ControllerCurrentShuntAddOn Complexity 186 / 1000 (size 121, features 65) KESE features through vias, rounded, trapezoid or chamfered pads, drill offsets, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 9, 72, 17 Triangles, simulation 134,582 in 23 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 4.8 MB 192 MB STEP 22 MB 209 MB STL 6.7 MB 190 MB OBJ 13 MB 195 MB Visual GLB 3.9 MB 170 MB OBJ 11 MB 169 MB

25.67 ESP8266ControllerCircuit

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.5	1.8	1 ms	1.3	59 ms	0.2	0.2	4.1
Simulation, STEP	0.1	0.4	1.8	0.2 ms	1.3	1.3	0.2	0.2	5.4
Simulation, STL	0.1	0.4	1.8	0.2 ms	1.3	90 ms	0.2	0.2	4.2
Simulation, OBJ	0.2	0.4	1.9	0.3 ms	1.3	1.8	0.2	0.2	5.9
Visual, GLB	0.1	0.4	1.8	0.3 ms	3.2	45 ms	0.3	0.2	6.1
Visual, OBJ	0.1	0.4	1.8	0.3 ms	3.0	1.4	0.3	0.2	7.3

Board Repo: stuartpittaway/diybmsv4 Board: ESP8266ControllerCircuit.kicad_pcb Folder ESP8266ControllerCircuit Complexity 183 / 1000 (size 138, features 45) KESE features through vias, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 20, 176, 16 Triangles, simulation 453,950 in 37 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 16 MB 280 MB STEP 78 MB 322 MB STL 23 MB 288 MB OBJ 46 MB 328 MB Visual GLB 12 MB 321 MB OBJ 35 MB 326 MB

25.68 v4

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.4	1.6	0.2 ms	1.4	62 ms	0.2	0.2	3.9
Simulation, STEP	0.1	0.3	1.5	0.2 ms	1.2	1.2	0.2	0.2	4.8
Simulation, STL	0.2	0.4	1.6	0.1 ms	1.2	93 ms	0.2	0.2	3.9
Simulation, OBJ	0.1	0.4	1.5	0.2 ms	1.4	1.8	0.2	0.2	5.6
Visual, GLB	0.1	0.3	1.5	0.1 ms	3.3	54 ms	0.5	0.2	6.0
Visual, OBJ	0.1	0.3	1.5	0.3 ms	3.2	1.6	0.6	0.2	7.6

Board Repo: stuartpittaway/diybmsv4 Board: v4.kicad_pcb Folder ModuleV400 Complexity 205 / 1000 (size 160, features 45) KESE features through vias, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 38, 401, 54 Triangles, simulation 446,686 in 40 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 16 MB 276 MB STEP 80 MB 338 MB STL 22 MB 288 MB OBJ 46 MB 359 MB Visual GLB 14 MB 355 MB OBJ 40 MB 344 MB

25.69 ModuleV421

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.4	1.8	0.3 ms	1.5	71 ms	0.2	0.2	4.3
Simulation, STEP	0.2	0.4	1.8	0.2 ms	1.4	1.5	0.2	0.2	5.7
Simulation, STL	0.2	0.4	1.9	0.2 ms	1.6	0.1	0.3	0.3	4.7
Simulation, OBJ	0.2	0.4	2.0	0.6 ms	1.7	2.0	0.2	0.2	6.7
Visual, GLB	0.2	0.4	2.0	0.4 ms	3.9	56 ms	0.5	0.2	7.3
Visual, OBJ	0.2	0.4	1.8	0.3 ms	3.4	1.7	0.5	0.2	8.3

Board Repo: stuartpittaway/diybmsv4 Board: ModuleV421.kicad_pcb Folder ModuleV421 Complexity 206 / 1000 (size 161, features 45) KESE features through vias, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 49, 333, 55 Triangles, simulation 466,586 in 48 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 17 MB 304 MB STEP 84 MB 346 MB STL 23 MB 289 MB OBJ 48 MB 377 MB Visual GLB 14 MB 355 MB OBJ 41 MB 356 MB

25.70 ModuleV440

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.4	2.4	0.3 ms	1.8	71 ms	0.3	0.2	5.3
Simulation, STEP	0.2	0.4	2.1	0.2 ms	1.8	1.7	0.3	0.3	6.8
Simulation, STL	0.2	0.5	2.3	0.4 ms	1.9	0.1	0.2	0.2	5.4
Simulation, OBJ	0.2	0.5	2.2	0.2 ms	1.7	2.4	0.2	0.2	7.2
Visual, GLB	0.2	0.4	2.4	0.3 ms	4.0	73 ms	0.6	0.2	7.8
Visual, OBJ	0.2	0.5	2.2	0.3 ms	4.0	1.9	0.6	0.2	9.6

Board Repo: stuartpittaway/diybmsv4 Board: ModuleV440.kicad_pcb Folder ModuleV440 Complexity 216 / 1000 (size 161, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 42, 305, 79 Triangles, simulation 513,534 in 40 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 18 MB 303 MB STEP 93 MB 353 MB STL 26 MB 295 MB OBJ 53 MB 405 MB Visual GLB 14 MB 368 MB OBJ 43 MB 366 MB

25.71 ModuleV450

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.5	2.7	0.2 ms	1.7	87 ms	0.3	0.2	5.8
Simulation, STEP	0.2	0.6	2.6	0.3 ms	1.7	1.6	0.3	0.2	7.2
Simulation, STL	0.2	0.6	2.6	0.2 ms	1.7	0.1	0.3	0.3	5.7
Simulation, OBJ	0.2	0.5	2.9	0.3 ms	1.8	2.8	0.3	0.2	8.7
Visual, GLB	0.2	0.5	2.8	0.4 ms	4.0	72 ms	0.5	0.3	8.4
Visual, OBJ	0.2	0.6	2.9	0.2 ms	4.1	2.4	0.4	0.2	10.8

Board Repo: stuartpittaway/diybmsv4 Board: ModuleV450.kicad_pcb Folder ModuleV450 Complexity 213 / 1000 (size 158, features 55) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 39, 209, 96 Triangles, simulation 522,076 in 38 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 18 MB 341 MB STEP 92 MB 355 MB STL 26 MB 321 MB OBJ 54 MB 356 MB Visual GLB 15 MB 351 MB OBJ 43 MB 352 MB

25.72 Module_16S

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.1	2.4	8.1	0.7 ms	8.1	0.4	1.2	0.3	21.6
Simulation, STEP	1.1	2.5	8.5	0.8 ms	8.0	6.2	1.1	0.3	27.6
Simulation, STL	1.0	2.5	8.2	0.7 ms	8.0	0.6	1.1	0.2	21.6
Simulation, OBJ	1.0	2.4	8.1	1 ms	8.3	12.1	1.1	0.2	33.3
Visual, GLB	1.1	2.3	8.2	1 ms	19.6	0.3	2.3	0.2	33.9
Visual, OBJ	1.1	2.4	8.4	0.8 ms	19.4	9.3	2.6	0.3	43.4

Board Repo: stuartpittaway/diybmsv4 Board: Module_16S.kicad_pcb Folder ModuleV490-AllInOne Complexity 371 / 1000 (size 256, features 115) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, TrueType text, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 113, 1,167, 289 Triangles, simulation 2,358,828 in 154 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 82 MB 753 MB STEP 320 MB 984 MB STL 118 MB 770 MB OBJ 249 MB 1.6 GB Visual GLB 59 MB 1.0 GB OBJ 181 MB 1.3 GB

25.73 Module_16S_PassiveBalanceAddOn

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	0.9	4.1	0.4 ms	4.6	0.2	0.6	0.2	11.0
Simulation, STEP	0.4	0.9	4.0	0.3 ms	4.2	3.2	0.6	0.3	13.6
Simulation, STL	0.4	0.9	3.8	0.3 ms	4.2	0.4	0.6	0.2	10.4
Simulation, OBJ	0.3	0.9	3.9	0.4 ms	4.4	5.5	0.6	0.2	15.8
Visual, GLB	0.3	0.9	3.9	0.5 ms	8.6	0.1	1.2	0.3	15.3
Visual, OBJ	0.4	0.9	4.1	0.4 ms	8.7	4.3	1.4	0.3	19.9

Board Repo: stuartpittaway/diybmsv4 Board: Module_16S_PassiveBalanceAddOn.kicad_pcb Folder ModuleV490-PassiveBal Complexity 281 / 1000 (size 181, features 100) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 86, 623, 173 Triangles, simulation 984,182 in 102 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 34 MB 452 MB STEP 167 MB 580 MB STL 49 MB 453 MB OBJ 100 MB 725 MB Visual GLB 28 MB 659 MB OBJ 84 MB 701 MB

25.74 ProgrammingAdapter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	88 ms	0.2	0.6	0.1 ms	0.6	23 ms	92 ms	0.2	1.9
Simulation, STEP	84 ms	0.2	0.6	0.1 ms	0.7	0.9	70 ms	0.2	2.7
Simulation, STL	82 ms	0.2	0.7	0.2 ms	0.6	32 ms	71 ms	0.2	1.9
Simulation, OBJ	0.1	0.2	0.7	0.1 ms	0.6	0.7	70 ms	0.2	2.6
Visual, GLB	90 ms	0.2	0.6	0.1 ms	1.4	16 ms	0.1	0.2	2.6
Visual, OBJ	87 ms	0.2	0.6	0.2 ms	1.5	0.5	0.1	0.2	3.2

Board Repo: stuartpittaway/diybmsv4 Board: ProgrammingAdapter.kicad_pcb Folder ProgrammingAdapter Complexity 145 / 1000 (size 100, features 45) KESE features through vias, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 3, 45, 6 Triangles, simulation 130,918 in 17 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 4.6 MB 187 MB STEP 22 MB 193 MB STL 6.5 MB 191 MB OBJ 13 MB 185 MB Visual GLB 3.2 MB 158 MB OBJ 9.0 MB 157 MB

25.75 TemperaturePCB

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	77 ms	0.3	0.1 ms	0.5	25 ms	56 ms	0.2	1.3
Simulation, STEP	0.2	70 ms	0.3	0.1 ms	0.5	0.8	46 ms	0.2	2.1
Simulation, STL	0.1	97 ms	0.4	0.1 ms	0.5	26 ms	56 ms	0.2	1.4
Simulation, OBJ	0.2	92 ms	0.4	0.1 ms	0.6	0.4	51 ms	0.2	1.8
Visual, GLB	0.1	84 ms	0.4	0.1 ms	1.3	14 ms	96 ms	0.2	2.2
Visual, OBJ	0.1	82 ms	0.3	0.1 ms	1.3	0.4	87 ms	0.2	2.4

Board Repo: stuartpittaway/diybmsv4 Board: TemperaturePCB.kicad_pcb Folder TemperaturePCB Complexity 121 / 1000 (size 66, features 55) KESE features rounded, trapezoid or chamfered pads, filled zones, curved board outline, TrueType text Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 3, 7, 0 Triangles, simulation 96,522 in 14 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 3.4 MB 180 MB STEP 14 MB 187 MB STL 4.8 MB 185 MB OBJ 9.5 MB 190 MB Visual GLB 2.8 MB 157 MB OBJ 7.8 MB 157 MB

25.76 TemperaturePCB_PANEL

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.9	1.2	3.9	0.3 ms	3.7	0.2	0.4	0.2	10.5
Simulation, STEP	0.9	1.1	3.9	0.6 ms	4.0	3.2	0.4	0.2	13.8
Simulation, STL	0.8	1.1	3.9	0.4 ms	3.6	0.6	0.3	0.2	10.7
Simulation, OBJ	0.8	1.1	3.9	0.5 ms	3.7	5.5	0.4	0.2	15.6
Visual, GLB	0.9	1.1	4.0	0.4 ms	9.8	0.2	1.3	0.2	17.5
Visual, OBJ	0.9	1.2	4.0	0.4 ms	9.9	4.8	1.5	0.2	22.6

Board Repo: stuartpittaway/diybmsv4 Board: TemperaturePCB_PANEL.kicad_pcb Folder TemperaturePCB_PANEL Complexity 174 / 1000 (size 129, features 45) KESE features rounded, trapezoid or chamfered pads, filled zones, TrueType text Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 36, 84, 0 Triangles, simulation 1,351,064 in 36 parts Note panel Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 47 MB 721 MB STEP 199 MB 723 MB STL 68 MB 714 MB OBJ 142 MB 952 MB Visual GLB 39 MB 746 MB OBJ 117 MB 874 MB

25.77 sensors

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.1	0.3	0.1 ms	0.7	19 ms	70 ms	0.3	1.6
Simulation, STEP	0.1	0.1	0.4	0.1 ms	0.8	1.1	97 ms	0.2	2.8
Simulation, STL	0.2	0.2	0.5	0.2 ms	0.8	37 ms	82 ms	0.3	2.1
Simulation, OBJ	0.1	0.2	0.4	0.1 ms	0.9	0.6	82 ms	0.3	2.6
Visual, GLB	0.1	0.1	0.4	0.2 ms	1.7	20 ms	0.1	0.3	2.8
Visual, OBJ	0.1	0.1	0.3	0.1 ms	1.4	0.4	97 ms	0.2	2.7

Board Repo: StuckAtPrototype/Racer Board: sensors.kicad_pcb Folder hardware / racer-sensors Complexity 185 / 1000 (size 140, features 45) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 14, 75, 12 Triangles, simulation 106,594 in 21 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 3.7 MB 187 MB STEP 18 MB 199 MB STL 5.3 MB 188 MB OBJ 10 MB 189 MB Visual GLB 2.9 MB 153 MB OBJ 8.2 MB 152 MB

25.78 racer

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.1	5.0	0.5 ms	4.7	0.2	0.6	0.3	12.4
Simulation, STEP	0.4	1.1	4.9	0.5 ms	4.8	3.8	0.6	0.3	15.8
Simulation, STL	0.4	1.0	5.0	0.5 ms	4.6	0.3	0.6	0.3	12.2
Simulation, OBJ	0.4	1.0	4.9	0.5 ms	4.6	6.1	0.6	0.3	17.9
Visual, GLB	0.4	1.0	4.9	0.6 ms	8.7	0.1	0.9	0.2	16.4
Visual, OBJ	0.4	1.1	5.0	0.5 ms	8.9	4.8	1.0	0.2	21.6

Board Repo: StuckAtPrototype/Racer Board: racer.kicad_pcb Folder hardware / racer Complexity 325 / 1000 (size 190, features 135) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 70, 546, 107 Triangles, simulation 1,031,612 in 87 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 36 MB 483 MB STEP 164 MB 571 MB STL 52 MB 475 MB OBJ 106 MB 730 MB Visual GLB 25 MB 581 MB OBJ 77 MB 618 MB

25.79 controller

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	0.7	3.5	0.3 ms	3.4	0.2	0.7	0.3	9.1
Simulation, STEP	0.5	1.0	3.5	0.3 ms	3.2	2.9	0.6	0.3	12.0
Simulation, STL	0.4	0.8	3.6	0.2 ms	3.4	0.2	0.5	0.2	9.2
Simulation, OBJ	0.4	1.0	3.7	0.2 ms	3.2	5.1	0.5	0.2	14.1
Visual, GLB	0.3	0.7	3.3	0.2 ms	6.6	91 ms	0.8	0.3	12.2
Visual, OBJ	0.6	1.2	3.7	0.3 ms	7.0	3.3	0.8	0.3	16.8

Board Repo: StuckAtPrototype/Racer Board: controller.kicad_pcb Folder hardware / thumbtroller Complexity 318 / 1000 (size 183, features 135) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 58, 430, 62 Triangles, simulation 833,932 in 71 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 29 MB 394 MB STEP 136 MB 490 MB STL 42 MB 401 MB OBJ 86 MB 627 MB Visual GLB 21 MB 536 MB OBJ 63 MB 527 MB

25.80 ail-LED

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	99 ms	83 ms	0.3	0.2 ms	0.6	18 ms	43 ms	0.2	1.2
Simulation, STEP	0.1	0.1	0.2	0.1 ms	0.6	0.7	38 ms	0.2	1.9
Simulation, STL	98 ms	78 ms	0.2	0.1 ms	0.5	29 ms	38 ms	0.2	1.2
Simulation, OBJ	92 ms	76 ms	0.2	0.1 ms	0.5	0.4	40 ms	0.2	1.6
Visual, GLB	0.1	93 ms	0.2	0.1 ms	1.0	11 ms	66 ms	0.2	1.7
Visual, OBJ	97 ms	77 ms	0.2	0.1 ms	1.1	0.3	63 ms	0.2	2.0

Board Repo: sufst/pcb Board: ail-LED.kicad_pcb Folder ail-LED Complexity 221 / 1000 (size 96, features 125) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 18, 8, 3 Triangles, simulation 99,858 in 27 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 3.9 MB 180 MB STEP 17 MB 196 MB STL 5.0 MB 183 MB OBJ 11 MB 185 MB Visual GLB 2.4 MB 153 MB OBJ 6.7 MB 157 MB

25.81 ail-LED_handsolder

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	76 ms	0.2	0.1 ms	0.5	20 ms	44 ms	0.2	1.2
Simulation, STEP	0.1	74 ms	0.2	0.1 ms	0.6	0.8	48 ms	0.2	2.1
Simulation, STL	99 ms	84 ms	0.2	0.1 ms	0.6	32 ms	45 ms	0.2	1.3
Simulation, OBJ	97 ms	79 ms	0.2	0.1 ms	0.5	0.5	75 ms	0.2	1.7
Visual, GLB	0.1	89 ms	0.2	0.1 ms	1.2	14 ms	88 ms	0.2	2.0
Visual, OBJ	0.1	0.1	0.2	0.1 ms	1.2	0.3	71 ms	0.2	2.2

Board Repo: sufst/pcb Board: ail-LED_handsolder.kicad_pcb Folder ail-LED Complexity 205 / 1000 (size 95, features 110) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 18, 7, 3 Triangles, simulation 96,088 in 27 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 3.8 MB 182 MB STEP 16 MB 194 MB STL 4.8 MB 182 MB OBJ 10 MB 187 MB Visual GLB 2.3 MB 153 MB OBJ 6.2 MB 154 MB

25.82 ail

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.1	0.5	0.3 ms	0.8	25 ms	68 ms	0.2	1.9
Simulation, STEP	0.2	0.1	0.5	0.1 ms	0.7	1.0	56 ms	0.2	2.8
Simulation, STL	0.2	0.2	0.5	0.2 ms	0.8	37 ms	60 ms	0.2	2.0
Simulation, OBJ	0.1	0.1	0.5	0.2 ms	0.7	0.6	59 ms	0.2	2.3
Visual, GLB	0.2	0.1	0.5	0.2 ms	1.4	18 ms	0.1	0.2	2.6
Visual, OBJ	0.2	0.2	0.6	0.2 ms	1.5	0.5	0.1	0.3	3.3

Board Repo: sufst/pcb Board: ail.kicad_pcb Folder ail Complexity 211 / 1000 (size 126, features 85) KESE features rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 29, 83, 0 Triangles, simulation 114,676 in 34 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 4.1 MB 199 MB STEP 23 MB 212 MB STL 5.7 MB 198 MB OBJ 11 MB 198 MB Visual GLB 3.5 MB 172 MB OBJ 9.5 MB 167 MB

25.83 debug-board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.4	1.6	0.2 ms	1.4	71 ms	0.2	0.2	4.1
Simulation, STEP	0.2	0.4	1.6	0.3 ms	1.4	1.7	0.3	0.2	5.8
Simulation, STL	0.2	0.5	1.5	0.2 ms	1.4	0.1	0.3	0.2	4.1
Simulation, OBJ	0.2	0.5	1.5	0.3 ms	1.4	2.1	0.2	0.2	6.1
Visual, GLB	0.2	0.4	1.4	0.2 ms	3.3	49 ms	0.3	0.2	5.8
Visual, OBJ	0.2	0.4	1.5	0.3 ms	3.5	1.8	0.5	0.2	8.2

Board Repo: sufst/pcb Board: debug-board.kicad_pcb Folder archive / debug-board Complexity 311 / 1000 (size 196, features 115) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 53, 279, 21 Triangles, simulation 435,016 in 66 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 15 MB 318 MB STEP 68 MB 318 MB STL 22 MB 313 MB OBJ 43 MB 340 MB Visual GLB 11 MB 339 MB OBJ 33 MB 339 MB

25.84 latching

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	1.4	0.3 ms	1.7	74 ms	0.2	0.2	4.0
Simulation, STEP	0.2	0.3	1.3	0.4 ms	1.6	1.5	0.2	0.2	5.4
Simulation, STL	0.2	0.3	1.4	0.2 ms	1.6	0.1	0.2	0.2	4.0
Simulation, OBJ	0.2	0.4	1.4	0.3 ms	1.7	1.9	0.2	0.2	5.9
Visual, GLB	0.2	0.4	1.4	0.4 ms	3.3	55 ms	0.5	0.2	6.0
Visual, OBJ	0.2	0.3	1.4	0.3 ms	3.5	1.5	0.6	0.2	7.8

Board Repo: sufst/pcb Board: latching.kicad_pcb Folder archive / latching Complexity 257 / 1000 (size 157, features 100) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 41, 268, 54 Triangles, simulation 470,068 in 51 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 16 MB 297 MB STEP 74 MB 350 MB STL 24 MB 296 MB OBJ 47 MB 373 MB Visual GLB 13 MB 397 MB OBJ 39 MB 391 MB

25.85 segment

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.2	3.3	0.5 ms	3.0	0.2	0.6	0.2	8.7
Simulation, STEP	0.3	1.2	3.3	1 ms	2.9	2.4	0.6	0.3	11.0
Simulation, STL	0.3	1.2	3.4	0.4 ms	3.0	0.4	0.6	0.2	9.1
Simulation, OBJ	0.3	1.3	3.5	0.4 ms	3.0	5.4	0.6	0.2	14.2
Visual, GLB	0.3	1.2	3.3	0.5 ms	7.1	83 ms	0.8	0.2	13.0
Visual, OBJ	0.3	1.3	3.4	0.4 ms	6.6	3.1	0.8	0.2	15.8

Board Repo: sufst/pcb Board: segment.kicad_pcb Folder archive / segment Complexity 242 / 1000 (size 157, features 85) KESE features rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 19, 261, 0 Triangles, simulation 940,566 in 66 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 32 MB 402 MB STEP 120 MB 447 MB STL 47 MB 410 MB OBJ 95 MB 649 MB Visual GLB 18 MB 506 MB OBJ 54 MB 478 MB

25.86 sensor-board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.1	4.5	0.7 ms	4.9	0.2	0.6	0.3	12.1
Simulation, STEP	0.5	1.1	4.2	0.4 ms	5.0	4.1	0.6	0.3	15.8
Simulation, STL	0.5	1.1	4.8	0.6 ms	5.2	0.4	0.6	0.3	13.0
Simulation, OBJ	0.6	1.1	4.5	0.7 ms	5.4	7.0	0.6	0.2	19.5
Visual, GLB	0.6	1.1	4.3	0.5 ms	9.3	0.1	1.0	0.3	16.6
Visual, OBJ	0.5	1.1	4.2	0.5 ms	9.3	4.4	1.3	0.2	21.1

Board Repo: sufst/pcb Board: sensor-board.kicad_pcb Folder archive / sensor-board Complexity 319 / 1000 (size 234, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 95, 679, 65 Triangles, simulation 1,192,408 in 126 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 41 MB 484 MB STEP 175 MB 570 MB STL 60 MB 489 MB OBJ 121 MB 828 MB Visual GLB 26 MB 712 MB OBJ 78 MB 706 MB

25.87 strain-gauge-amp-breakout

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.5	0.1 ms	0.7	24 ms	63 ms	0.3	1.8
Simulation, STEP	0.1	0.2	0.5	0.1 ms	0.7	0.9	61 ms	0.2	2.7
Simulation, STL	0.1	0.1	0.5	0.1 ms	0.7	34 ms	65 ms	0.2	1.8
Simulation, OBJ	0.1	0.1	0.5	0.1 ms	0.6	0.7	69 ms	0.2	2.3
Visual, GLB	0.1	0.2	0.5	0.1 ms	1.4	20 ms	0.2	0.2	2.6
Visual, OBJ	0.1	0.2	0.5	0.1 ms	1.4	0.6	0.1	0.2	3.1

Board Repo: sufst/pcb Board: strain-gauge-amp-breakout.kicad_pcb Folder archive / sensor-board / strain-gauge-amp-breakout Complexity 188 / 1000 (size 103, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 10, 30, 3 Triangles, simulation 127,118 in 21 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 4.5 MB 202 MB STEP 23 MB 206 MB STL 6.4 MB 200 MB OBJ 12 MB 205 MB Visual GLB 3.7 MB 161 MB OBJ 10 MB 160 MB

25.88 telemetry

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.7	3.4	0.6 ms	3.4	0.2	0.5	0.2	8.6
Simulation, STEP	0.3	0.7	3.6	1 ms	3.1	2.8	0.4	0.2	11.1
Simulation, STL	0.3	0.7	3.6	0.7 ms	3.5	0.3	0.5	0.2	9.1
Simulation, OBJ	0.3	0.7	3.7	1 ms	3.3	4.2	0.5	0.2	12.9
Visual, GLB	0.2	0.7	3.5	0.6 ms	7.7	0.1	1.1	0.2	13.6
Visual, OBJ	0.3	0.7	3.8	0.8 ms	8.0	3.1	0.9	0.2	17.0

Board Repo: sufst/pcb Board: telemetry.kicad_pcb Folder archive / telemetry Complexity 246 / 1000 (size 161, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 44, 423, 37 Triangles, simulation 1,117,864 in 147 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 37 MB 475 MB STEP 178 MB 595 MB STL 56 MB 480 MB OBJ 112 MB 797 MB Visual GLB 26 MB 653 MB OBJ 79 MB 638 MB

25.89 test-rig

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	0.9	5.1	0.5 ms	3.7	0.2	0.6	0.2	11.0
Simulation, STEP	0.3	1.0	5.2	0.4 ms	3.4	2.9	0.5	0.2	13.6
Simulation, STL	0.3	0.9	5.0	0.5 ms	3.5	0.3	0.5	0.2	10.7
Simulation, OBJ	0.3	1.0	5.2	0.6 ms	3.8	5.8	0.6	0.2	16.9
Visual, GLB	0.3	1.0	5.3	0.6 ms	8.0	0.1	0.9	0.2	15.8
Visual, OBJ	0.3	0.9	5.1	0.4 ms	8.1	4.1	1.0	0.2	19.7

Board Repo: sufst/pcb Board: test-rig.kicad_pcb Folder archive / test-rig Complexity 264 / 1000 (size 154, features 110) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 60, 259, 6 Triangles, simulation 1,130,338 in 68 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 38 MB 530 MB STEP 174 MB 598 MB STL 57 MB 545 MB OBJ 114 MB 769 MB Visual GLB 27 MB 680 MB OBJ 82 MB 679 MB

25.90 tsal

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.9	3.7	0.5 ms	3.9	0.2	0.6	0.2	9.7
Simulation, STEP	0.3	0.9	3.5	0.5 ms	3.9	3.4	0.5	0.2	12.9
Simulation, STL	0.3	0.9	3.7	0.7 ms	4.6	0.4	0.5	0.2	10.6
Simulation, OBJ	0.3	0.9	3.6	0.5 ms	4.4	4.4	0.5	0.2	14.4
Visual, GLB	0.3	0.9	3.9	0.6 ms	8.3	0.2	1.4	0.2	15.1
Visual, OBJ	0.3	0.9	3.8	0.5 ms	8.2	4.2	1.2	0.3	18.9

Board Repo: sufst/pcb Board: tsal.kicad_pcb Folder archive / tsal Complexity 281 / 1000 (size 181, features 100) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 93, 603, 181 Triangles, simulation 1,101,330 in 93 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 38 MB 522 MB STEP 182 MB 632 MB STL 55 MB 529 MB OBJ 111 MB 753 MB Visual GLB 32 MB 618 MB OBJ 97 MB 707 MB

25.91 batak

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	1.1	7.4	0.4 ms	6.1	0.2	0.6	0.3	16.4
Simulation, STEP	0.6	1.2	6.6	0.7 ms	5.6	4.5	0.6	0.3	19.3
Simulation, STL	0.5	1.1	6.6	0.4 ms	5.7	0.4	0.7	0.3	15.1
Simulation, OBJ	0.5	1.0	7.1	0.5 ms	6.0	6.7	0.7	0.3	22.2
Visual, GLB	0.5	1.3	6.7	0.5 ms	12.6	0.1	1.4	0.3	23.0
Visual, OBJ	0.5	1.2	6.8	0.7 ms	12.5	4.7	1.6	0.2	27.6

Board Repo: sufst/pcb Board: batak.kicad_pcb Folder batak Complexity 309 / 1000 (size 189, features 120) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 169, 1,040, 71 Triangles, simulation 1,324,298 in 178 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 45 MB 568 MB STEP 225 MB 670 MB STL 66 MB 567 MB OBJ 136 MB 915 MB Visual GLB 32 MB 754 MB OBJ 96 MB 731 MB

25.92 bms-interface

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	1.5	0.2 ms	1.4	66 ms	0.2	0.3	4.0
Simulation, STEP	0.2	0.4	1.5	0.2 ms	1.3	1.5	0.2	0.3	5.5
Simulation, STL	0.2	0.4	1.5	0.2 ms	1.4	0.1	0.2	0.3	4.1
Simulation, OBJ	0.2	0.3	1.5	0.3 ms	1.4	2.1	0.2	0.3	6.0
Visual, GLB	0.2	0.4	1.5	0.2 ms	3.1	51 ms	0.4	0.3	5.9
Visual, OBJ	0.2	0.4	1.5	0.3 ms	3.1	1.4	0.3	0.3	7.2

Board Repo: sufst/pcb Board: bms-interface.kicad_pcb Folder bms-interface Complexity 219 / 1000 (size 129, features 90) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 11, 88, 32 Triangles, simulation 350,714 in 15 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 12 MB 270 MB STEP 44 MB 291 MB STL 18 MB 253 MB OBJ 35 MB 280 MB Visual GLB 8.4 MB 272 MB OBJ 24 MB 274 MB

25.93 brake-light

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	1.1	0.2 ms	1.6	60 ms	0.2	0.2	3.6
Simulation, STEP	0.2	0.3	1.1	0.2 ms	1.6	1.6	0.2	0.2	5.2
Simulation, STL	0.2	0.3	1.0	0.2 ms	1.6	83 ms	0.2	0.2	3.5
Simulation, OBJ	0.2	0.3	1.1	0.2 ms	1.6	1.9	0.2	0.2	5.5
Visual, GLB	0.2	0.3	1.1	0.2 ms	3.2	50 ms	0.3	0.2	5.5
Visual, OBJ	0.2	0.3	1.1	0.2 ms	3.1	1.5	0.3	0.2	6.7

Board Repo: sufst/pcb Board: brake-light.kicad_pcb Folder brake-light Complexity 247 / 1000 (size 152, features 95) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 62, 203, 13 Triangles, simulation 372,316 in 49 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 14 MB 283 MB STEP 68 MB 318 MB STL 19 MB 285 MB OBJ 39 MB 327 MB Visual GLB 10 MB 298 MB OBJ 30 MB 305 MB

25.94 BSPD

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	0.8	2.8	0.3 ms	3.2	0.1	0.6	0.2	8.1
Simulation, STEP	0.4	0.7	2.7	0.2 ms	3.0	2.7	0.5	0.2	10.3
Simulation, STL	0.5	0.7	2.7	0.2 ms	3.1	0.2	0.5	0.2	8.0
Simulation, OBJ	0.4	0.8	2.8	0.3 ms	3.0	4.8	0.5	0.2	12.5
Visual, GLB	0.4	0.7	2.8	0.2 ms	6.8	93 ms	0.8	0.2	11.8
Visual, OBJ	0.4	0.7	2.8	0.2 ms	6.6	3.2	0.7	0.2	14.7

Board Repo: sufst/pcb Board: BSPD.kicad_pcb Folder bspd Complexity 321 / 1000 (size 181, features 140) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 68, 363, 41 Triangles, simulation 986,096 in 70 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 34 MB 415 MB STEP 160 MB 511 MB STL 49 MB 452 MB OBJ 100 MB 672 MB Visual GLB 23 MB 562 MB OBJ 68 MB 552 MB

25.95 can-repeater

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	0.7	2.6	0.3 ms	2.8	0.1	0.4	0.2	7.4
Simulation, STEP	0.4	0.7	2.6	0.3 ms	3.0	2.6	0.4	0.2	10.0
Simulation, STL	0.4	0.7	2.7	0.2 ms	3.2	0.2	0.4	0.2	8.0
Simulation, OBJ	0.4	0.8	2.6	0.2 ms	2.9	4.1	0.4	0.2	11.4
Visual, GLB	0.4	0.7	2.6	0.4 ms	6.0	82 ms	0.4	0.2	10.5
Visual, OBJ	0.4	0.8	2.5	0.3 ms	5.8	2.6	0.6	0.2	12.9

Board Repo: sufst/pcb Board: can-repeater.kicad_pcb Folder can-repeater Complexity 362 / 1000 (size 222, features 140) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 61, 338, 74 Triangles, simulation 787,626 in 94 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 27 MB 370 MB STEP 130 MB 444 MB STL 39 MB 379 MB OBJ 80 MB 554 MB Visual GLB 18 MB 499 MB OBJ 55 MB 497 MB

25.96 curr-amp

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	0.9	0.4 ms	1.0	39 ms	0.1	0.2	2.8
Simulation, STEP	0.1	0.2	0.9	0.2 ms	1.0	1.2	0.1	0.2	3.7
Simulation, STL	0.1	0.2	0.9	0.2 ms	1.0	54 ms	0.1	0.3	2.7
Simulation, OBJ	0.2	0.3	0.9	0.2 ms	1.0	1.1	0.1	0.2	3.7
Visual, GLB	0.1	0.2	0.9	0.1 ms	2.0	33 ms	0.2	0.2	3.8
Visual, OBJ	0.2	0.2	1.0	0.2 ms	2.0	0.9	0.2	0.2	4.6

Board Repo: sufst/pcb Board: curr-amp.kicad_pcb Folder curr-amp Complexity 238 / 1000 (size 143, features 95) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 33, 181, 11 Triangles, simulation 219,220 in 37 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 7.6 MB 224 MB STEP 39 MB 248 MB STL 11 MB 224 MB OBJ 22 MB 224 MB Visual GLB 6.5 MB 225 MB OBJ 19 MB 226 MB

25.97 Dash-PCB

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.3	5.1	0.5 ms	3.9	0.2	0.6	0.2	11.7
Simulation, STEP	0.4	1.2	5.0	0.5 ms	3.9	3.2	0.5	0.3	14.5
Simulation, STL	0.4	1.1	4.9	0.5 ms	3.9	0.3	0.7	0.2	11.7
Simulation, OBJ	0.4	1.2	4.9	0.6 ms	3.8	6.0	0.5	0.2	17.0
Visual, GLB	0.6	1.2	5.1	0.5 ms	9.8	0.1	0.8	0.3	18.0
Visual, OBJ	0.4	1.2	5.2	0.7 ms	10.0	4.6	0.9	0.3	22.7

Board Repo: sufst/pcb Board: Dash-PCB.kicad_pcb Folder dash Complexity 336 / 1000 (size 211, features 125) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 60, 383, 151 Triangles, simulation 1,099,544 in 125 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 38 MB 530 MB STEP 182 MB 584 MB STL 55 MB 502 MB OBJ 114 MB 798 MB Visual GLB 29 MB 696 MB OBJ 86 MB 660 MB

25.98 can-node

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.7	2.0	0.2 ms	1.8	94 ms	0.3	0.2	5.4
Simulation, STEP	0.3	0.7	2.0	0.3 ms	1.8	1.8	0.3	0.2	7.0
Simulation, STL	0.3	0.6	2.0	0.2 ms	1.8	0.2	0.3	0.2	5.4
Simulation, OBJ	0.3	0.7	1.9	0.2 ms	1.8	2.8	0.3	0.2	7.9
Visual, GLB	0.3	0.7	1.9	0.2 ms	4.7	69 ms	0.6	0.2	8.4
Visual, OBJ	0.3	0.6	2.0	0.4 ms	4.7	2.4	0.6	0.2	10.8

Board Repo: sufst/pcb Board: can-node.kicad_pcb Folder debug-board / can-node Complexity 320 / 1000 (size 205, features 115) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 86, 337, 35 Triangles, simulation 565,364 in 78 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 20 MB 337 MB STEP 91 MB 392 MB STL 28 MB 315 MB OBJ 57 MB 437 MB Visual GLB 16 MB 444 MB OBJ 46 MB 403 MB

25.99 Discharge

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.7	0.1 ms	0.7	27 ms	80 ms	0.2	2.1
Simulation, STEP	0.1	0.2	0.8	0.1 ms	0.7	0.9	82 ms	0.2	3.0
Simulation, STL	0.2	0.2	0.7	0.1 ms	0.7	39 ms	0.1	0.2	2.2
Simulation, OBJ	0.1	0.2	0.8	0.1 ms	0.7	0.9	97 ms	0.2	3.1
Visual, GLB	0.1	0.3	0.9	0.2 ms	1.6	23 ms	0.1	0.2	3.4
Visual, OBJ	0.1	0.2	0.8	0.2 ms	1.5	0.6	0.1	0.2	3.6

Board Repo: sufst/pcb Board: Discharge.kicad_pcb Folder discharge Complexity 201 / 1000 (size 121, features 80) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 16, 72, 5 Triangles, simulation 155,512 in 24 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 5.4 MB 199 MB STEP 23 MB 208 MB STL 7.8 MB 195 MB OBJ 15 MB 200 MB Visual GLB 4.0 MB 171 MB OBJ 11 MB 167 MB

25.100 hv_sense

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.4	1.1	0.2 ms	0.9	44 ms	0.1	0.2	3.0
Simulation, STEP	0.1	0.5	1.1	0.3 ms	0.9	1.1	0.1	0.2	4.0
Simulation, STL	0.1	0.4	1.1	0.2 ms	0.9	60 ms	0.1	0.2	2.8
Simulation, OBJ	0.1	0.4	1.1	0.3 ms	1.0	1.5	0.1	0.2	4.5
Visual, GLB	0.1	0.4	1.1	0.2 ms	2.2	34 ms	0.2	0.2	4.3
Visual, OBJ	0.2	0.4	1.1	0.2 ms	2.2	1.1	0.2	0.2	5.5

Board Repo: sufst/pcb Board: hv_sense.kicad_pcb Folder hv-sense Complexity 250 / 1000 (size 150, features 100) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 24, 94, 104 Triangles, simulation 272,196 in 32 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 9.4 MB 227 MB STEP 32 MB 263 MB STL 14 MB 242 MB OBJ 27 MB 228 MB Visual GLB 7.7 MB 239 MB OBJ 22 MB 241 MB

25.101 CAN_Bridge

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.4	1.8	0.3 ms	2.0	69 ms	0.2	0.2	4.9
Simulation, STEP	0.2	0.4	1.7	0.3 ms	2.1	1.8	0.2	0.2	6.7
Simulation, STL	0.2	0.4	1.7	0.3 ms	2.1	0.1	0.3	0.2	5.1
Simulation, OBJ	0.2	0.4	1.5	0.2 ms	2.3	2.1	0.3	0.2	7.0
Visual, GLB	0.2	0.4	1.6	0.6 ms	4.1	56 ms	0.5	0.2	7.1
Visual, OBJ	0.2	0.4	1.6	0.3 ms	4.1	1.6	0.5	0.2	8.8

Board Repo: sufst/pcb Board: CAN_Bridge.kicad_pcb Folder isolator Complexity 294 / 1000 (size 194, features 100) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 41, 283, 32 Triangles, simulation 459,396 in 84 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 16 MB 305 MB STEP 76 MB 350 MB STL 23 MB 303 MB OBJ 46 MB 368 MB Visual GLB 13 MB 350 MB OBJ 37 MB 352 MB

25.102 lvbms-connector

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	70 ms	48 ms	0.2	0.1 ms	0.3	8 ms	28 ms	0.2	0.9
Simulation, STEP	85 ms	57 ms	0.2	0.1 ms	0.4	0.3	35 ms	0.2	1.3
Simulation, STL	73 ms	50 ms	0.2	0.1 ms	0.4	12 ms	27 ms	0.2	1.0
Simulation, OBJ	88 ms	56 ms	0.2	0.1 ms	0.3	0.2	28 ms	0.2	1.1
Visual, GLB	90 ms	51 ms	0.2	0.1 ms	0.4	5 ms	48 ms	0.2	1.0
Visual, OBJ	82 ms	52 ms	0.2	0.1 ms	0.4	0.1	39 ms	0.2	1.1

Board Repo: sufst/pcb Board: lvbms-connector.kicad_pcb Folder lvbms-conn Complexity 62 / 1000 (size 32, features 30) KESE features rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 3, 0, 0 Triangles, simulation 45,170 in 17 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 1.5 MB 66 MB STEP 5.4 MB 70 MB STL 2.3 MB 68 MB OBJ 4.3 MB 85 MB Visual GLB 931 kB 99 MB OBJ 2.5 MB 100 MB

25.103 PCB - VOLTAGE TAPS

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.6	2.9	0.2 ms	1.7	73 ms	0.2	0.2	5.9
Simulation, STEP	0.2	0.5	3.0	0.2 ms	1.7	1.5	0.3	0.2	7.4
Simulation, STL	0.2	0.6	3.0	0.2 ms	1.7	0.1	0.2	0.2	6.0
Simulation, OBJ	0.2	0.5	3.0	0.3 ms	1.7	2.5	0.2	0.2	8.3
Visual, GLB	0.2	0.6	2.9	0.2 ms	3.4	46 ms	0.3	0.2	7.6
Visual, OBJ	0.2	0.6	3.0	0.2 ms	3.4	1.7	0.3	0.3	9.4

Board Repo: sufst/pcb Board: PCB - VOLTAGE TAPS.kicad_pcb Folder PCB - VOLTAGE TAPS Complexity 267 / 1000 (size 122, features 145) KESE features slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, copper drawings, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 26, 68, 0 Triangles, simulation 459,532 in 25 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 17 MB 273 MB STEP 94 MB 325 MB STL 23 MB 266 MB OBJ 49 MB 374 MB Visual GLB 10 MB 286 MB OBJ 30 MB 304 MB

25.104 precharge

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	0.8	0.2 ms	0.8	41 ms	0.1	0.2	2.5
Simulation, STEP	0.2	0.3	0.9	0.2 ms	0.9	1.1	0.1	0.2	3.6
Simulation, STL	0.2	0.3	0.8	0.2 ms	0.9	65 ms	0.1	0.2	2.6
Simulation, OBJ	0.2	0.3	0.9	0.2 ms	0.9	1.5	0.1	0.3	4.2
Visual, GLB	0.2	0.3	0.8	0.2 ms	2.4	36 ms	0.3	0.2	4.2
Visual, OBJ	0.2	0.3	0.8	0.2 ms	2.5	1.1	0.2	0.2	5.4

Board Repo: sufst/pcb Board: precharge.kicad_pcb Folder precharge Complexity 221 / 1000 (size 141, features 80) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 40, 153, 4 Triangles, simulation 243,334 in 48 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 8.3 MB 232 MB STEP 39 MB 246 MB STL 12 MB 236 MB OBJ 24 MB 224 MB Visual GLB 6.8 MB 223 MB OBJ 19 MB 222 MB

25.105 right-sidepanel

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.7	4.3	0.2 ms	3.9	0.2	0.5	0.3	10.2
Simulation, STEP	0.3	0.7	4.1	0.3 ms	3.7	2.5	0.4	0.3	12.0
Simulation, STL	0.2	0.7	4.1	0.2 ms	3.8	0.2	0.4	0.3	9.7
Simulation, OBJ	0.2	0.8	4.2	0.2 ms	4.2	4.6	0.4	0.3	14.7
Visual, GLB	0.2	0.8	4.4	0.2 ms	6.8	76 ms	0.6	0.2	13.1
Visual, OBJ	0.2	0.7	4.3	0.2 ms	6.6	2.7	0.6	0.2	15.3

Board Repo: sufst/pcb Board: right-sidepanel.kicad_pcb Folder right-sidepanel Complexity 230 / 1000 (size 160, features 70) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 34, 122, 155 Triangles, simulation 775,100 in 39 parts Note panel Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 26 MB 346 MB STEP 96 MB 441 MB STL 39 MB 348 MB OBJ 78 MB 581 MB Visual GLB 15 MB 476 MB OBJ 44 MB 440 MB

25.106 rotary-switch

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.8	0.1 ms	0.8	38 ms	0.1	0.3	2.3
Simulation, STEP	0.1	0.2	0.8	0.2 ms	0.8	1.1	0.1	0.2	3.3
Simulation, STL	0.1	0.2	0.8	0.2 ms	0.9	57 ms	0.1	0.2	2.3
Simulation, OBJ	0.1	0.2	0.8	0.2 ms	0.8	1.1	0.1	0.2	3.3
Visual, GLB	0.1	0.2	0.7	0.2 ms	1.9	31 ms	0.2	0.2	3.5
Visual, OBJ	0.1	0.2	0.8	0.2 ms	2.2	0.8	0.2	0.2	4.4

Board Repo: sufst/pcb Board: rotary-switch.kicad_pcb Folder rotary-switch Complexity 173 / 1000 (size 108, features 65) KESE features rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 18, 37, 0 Triangles, simulation 222,110 in 28 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 7.6 MB 223 MB STEP 35 MB 239 MB STL 11 MB 224 MB OBJ 22 MB 224 MB Visual GLB 5.6 MB 224 MB OBJ 16 MB 226 MB

25.107 segment-switch

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	63 ms	31 ms	40 ms	0.1 ms	0.1	4 ms	9 ms	0.2	0.5
Simulation, STEP	64 ms	31 ms	40 ms	0.1 ms	0.1	0.1	10 ms	0.2	0.6
Simulation, STL	73 ms	37 ms	47 ms	0.1 ms	0.1	6 ms	10 ms	0.2	0.5
Simulation, OBJ	71 ms	32 ms	41 ms	0.1 ms	0.1	68 ms	11 ms	0.2	0.5
Visual, GLB	62 ms	31 ms	44 ms	0.1 ms	0.2	3 ms	27 ms	0.2	0.6
Visual, OBJ	61 ms	30 ms	41 ms	0.1 ms	0.2	65 ms	28 ms	0.2	0.6

Board Repo: sufst/pcb Board: segment-switch.kicad_pcb Folder segment-switch Complexity 120 / 1000 (size 65, features 55) KESE features rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 2, 8, 0 Triangles, simulation 16,958 in 10 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 617 kB 61 MB STEP 2.8 MB 64 MB STL 849 kB 61 MB OBJ 1.7 MB 63 MB Visual GLB 599 kB 87 MB OBJ 1.6 MB 89 MB

25.108 16Ch-Sensor-Hub

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	2.1	8.4	0.6 ms	10.7	0.4	1.0	0.2	23.7
Simulation, STEP	0.9	2.2	9.0	0.5 ms	10.6	6.8	1.1	0.3	30.9
Simulation, STL	1.0	2.3	9.0	0.6 ms	10.9	0.6	1.1	0.2	25.1
Simulation, OBJ	0.9	2.2	9.2	0.7 ms	10.9	14.3	1.1	0.3	38.8
Visual, GLB	1.0	2.5	9.7	0.7 ms	27.0	0.3	3.3	0.3	44.2
Visual, OBJ	1.1	2.6	10.2	0.6 ms	26.8	10.6	3.6	0.3	55.2

Board Repo: sufst/pcb Board: 16Ch-Sensor-Hub.kicad_pcb Folder sensor-hub Complexity 375 / 1000 (size 250, features 125) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 170, 906, 236 Triangles, simulation 2,375,892 in 122 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 82 MB 845 MB STEP 389 MB 1.0 GB STL 119 MB 824 MB OBJ 252 MB 1.6 GB Visual GLB 52 MB 979 MB OBJ 159 MB 1.2 GB

25.109 8Ch-Sensor-Hub

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	2.1	6.0	0.5 ms	7.5	0.3	0.8	0.4	17.8
Simulation, STEP	0.8	2.0	6.3	1 ms	8.6	5.7	0.9	0.4	24.7
Simulation, STL	0.8	2.1	5.8	0.7 ms	7.8	0.6	0.8	0.3	18.1
Simulation, OBJ	0.7	1.9	6.0	0.5 ms	7.5	9.5	0.7	0.3	26.7
Visual, GLB	0.7	1.9	5.9	0.9 ms	13.6	0.2	1.6	0.3	24.1
Visual, OBJ	0.7	1.8	5.6	0.6 ms	12.8	6.4	1.5	0.2	29.0

Board Repo: sufst/pcb Board: 8Ch-Sensor-Hub.kicad_pcb Folder sensor-hub Complexity 364 / 1000 (size 239, features 125) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 111, 527, 186 Triangles, simulation 1,586,974 in 105 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 54 MB 620 MB STEP 219 MB 734 MB STL 79 MB 606 MB OBJ 163 MB 1.1 GB Visual GLB 35 MB 681 MB OBJ 106 MB 810 MB

25.110 ss-relay

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	67 ms	43 ms	0.2	0.1 ms	0.3	7 ms	27 ms	0.2	0.8
Simulation, STEP	69 ms	44 ms	0.2	0.1 ms	0.3	0.3	35 ms	0.2	1.2
Simulation, STL	87 ms	63 ms	0.2	0.1 ms	0.3	11 ms	29 ms	0.2	0.9
Simulation, OBJ	78 ms	49 ms	0.2	0.1 ms	0.4	0.2	27 ms	0.2	1.1
Visual, GLB	74 ms	46 ms	0.2	0.1 ms	0.4	6 ms	44 ms	0.2	1.0
Visual, OBJ	76 ms	47 ms	0.2	0.1 ms	0.4	0.1	48 ms	0.2	1.1

Board Repo: sufst/pcb Board: ss-relay.kicad_pcb Folder ss-relay Complexity 160 / 1000 (size 90, features 70) KESE features custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, knockout text Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 7, 21, 0 Triangles, simulation 46,626 in 18 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 1.6 MB 69 MB STEP 7.8 MB 75 MB STL 2.3 MB 69 MB OBJ 4.5 MB 79 MB Visual GLB 1.2 MB 104 MB OBJ 3.2 MB 107 MB

25.111 tem

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.7	2.6	0.5 ms	4.0	0.1	0.3	0.2	8.4
Simulation, STEP	0.3	0.7	2.4	0.4 ms	3.5	3.0	0.3	0.2	10.4
Simulation, STL	0.3	0.7	2.5	0.4 ms	3.7	0.3	0.4	0.2	8.0
Simulation, OBJ	0.3	0.6	2.4	0.5 ms	3.8	3.6	0.4	0.2	11.3
Visual, GLB	0.3	0.6	2.5	0.4 ms	7.0	0.1	0.9	0.2	11.6
Visual, OBJ	0.3	0.7	2.5	0.6 ms	6.9	3.0	0.9	0.2	14.5

Board Repo: sufst/pcb Board: tem.kicad_pcb Folder tem Complexity 269 / 1000 (size 224, features 45) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 103, 756, 169 Triangles, simulation 865,058 in 60 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 30 MB 485 MB STEP 154 MB 519 MB STL 43 MB 488 MB OBJ 87 MB 620 MB Visual GLB 25 MB 696 MB OBJ 75 MB 651 MB

25.112 trc

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.7	2.7	0.5 ms	3.4	0.1	0.4	0.3	7.9
Simulation, STEP	0.3	0.7	2.7	0.4 ms	3.3	2.7	0.4	0.3	10.3
Simulation, STL	0.3	0.6	2.8	0.4 ms	3.3	0.2	0.4	0.2	7.9
Simulation, OBJ	0.2	0.6	2.6	0.8 ms	3.1	3.4	0.4	0.2	10.7
Visual, GLB	0.3	0.6	2.8	0.4 ms	6.0	94 ms	0.8	0.2	10.8
Visual, OBJ	0.3	0.6	2.8	0.4 ms	6.2	2.9	0.9	0.2	13.9

Board Repo: sufst/pcb Board: trc.kicad_pcb Folder trc Complexity 266 / 1000 (size 166, features 100) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 56, 364, 89 Triangles, simulation 721,698 in 71 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 25 MB 370 MB STEP 121 MB 435 MB STL 36 MB 372 MB OBJ 73 MB 525 MB Visual GLB 20 MB 529 MB OBJ 59 MB 540 MB

25.113 tsal-latching-integrated

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.0	3.5	0.4 ms	3.5	0.2	0.6	0.2	9.4
Simulation, STEP	0.4	1.0	3.7	0.3 ms	3.4	3.1	0.5	0.3	12.3
Simulation, STL	0.4	0.9	3.6	0.4 ms	3.5	0.4	0.5	0.2	9.5
Simulation, OBJ	0.4	1.0	3.6	0.4 ms	3.7	5.1	0.5	0.2	14.5
Visual, GLB	0.3	1.0	3.7	0.4 ms	7.6	0.1	1.0	0.2	13.9
Visual, OBJ	0.3	1.0	3.5	0.4 ms	7.4	3.2	0.9	0.2	16.6

Board Repo: sufst/pcb Board: tsal-latching-integrated.kicad_pcb Folder tsal-latching-integrated Complexity 311 / 1000 (size 186, features 125) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 80, 429, 62 Triangles, simulation 1,076,692 in 77 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 37 MB 461 MB STEP 156 MB 536 MB STL 54 MB 456 MB OBJ 109 MB 767 MB Visual GLB 24 MB 661 MB OBJ 73 MB 602 MB

25.114 tsal-led

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.0	3.9	0.4 ms	3.8	0.1	0.5	0.2	9.8
Simulation, STEP	0.2	0.9	3.7	0.4 ms	3.7	2.0	0.5	0.2	11.3
Simulation, STL	0.2	1.0	3.7	0.4 ms	3.6	0.4	0.6	0.2	9.7
Simulation, OBJ	0.3	0.9	3.7	0.4 ms	3.8	4.8	0.6	0.3	14.3
Visual, GLB	0.2	1.0	3.6	0.4 ms	10.4	98 ms	0.7	0.2	16.3
Visual, OBJ	0.3	1.0	4.0	0.3 ms	9.5	3.0	0.7	0.2	18.8

Board Repo: sufst/pcb Board: tsal-led.kicad_pcb Folder tsal-led Complexity 321 / 1000 (size 191, features 130) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 57, 85, 316 Triangles, simulation 973,862 in 36 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 33 MB 470 MB STEP 84 MB 544 MB STL 49 MB 492 MB OBJ 96 MB 637 MB Visual GLB 18 MB 503 MB OBJ 54 MB 515 MB

25.115 vcu

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	3.1	11.9	1 ms	13.1	0.6	1.4	0.3	31.0
Simulation, STEP	0.7	3.0	12.3	0.8 ms	13.5	9.3	1.4	0.3	40.5
Simulation, STL	0.7	3.1	11.9	1 ms	12.9	1.0	1.4	0.3	31.2
Simulation, OBJ	0.7	3.1	11.5	1 ms	13.0	17.9	1.4	0.3	47.8
Visual, GLB	0.7	3.1	12.1	1 ms	28.9	0.4	2.9	0.3	48.4
Visual, OBJ	0.6	3.0	11.5	1 ms	27.6	11.2	3.3	0.3	57.4

Board Repo: sufst/pcb Board: vcu.kicad_pcb Folder vcu Complexity 346 / 1000 (size 266, features 80) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 205, 1,711, 293 Triangles, simulation 3,172,496 in 345 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 109 MB 1.0 GB STEP 459 MB 1.3 GB STL 159 MB 1.0 GB OBJ 338 MB 2.1 GB Visual GLB 70 MB 1.3 GB OBJ 220 MB 1.5 GB

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