Corpus Testing 07

Corpus Page 7

Part 7 of 29 of Corpus Testing: boards 649 to 756, six runs each, one file format a run, as Corpus Testing describes.

649. TC01AtariJoystick

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.3	2.2	0.3 ms	1.7	85 ms	0.3	0.2	5.0
Simulation, STEP	0.1	0.3	2.2	0.3 ms	1.6	1.6	0.3	0.2	6.3
Simulation, STL	0.1	0.3	2.0	0.2 ms	1.7	0.1	0.3	0.2	4.9
Simulation, OBJ	0.1	0.3	2.2	0.4 ms	1.7	2.7	0.3	0.2	7.6
Visual, GLB	0.2	0.4	2.9	0.4 ms	3.2	39 ms	0.3	0.2	7.2
Visual, OBJ	0.1	0.3	2.2	0.3 ms	3.2	1.4	0.3	0.2	7.8

Board Repo: Board-Folk/Einstein-TC-01 Board: TC01AtariJoystick.kicad_pcb Folder Expansions / TC01AtariJoystick / Kicad Complexity 191 / 1000 (size 131, features 60) KESE features filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 10, 219, 0 Triangles, simulation 503,944 in 29 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 17 MB 287 MB STEP 68 MB 334 MB STL 25 MB 284 MB OBJ 50 MB 377 MB Visual GLB 9.4 MB 333 MB OBJ 28 MB 327 MB

650. TC02Mini

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	2.4	15.2	1 ms	11.2	0.5	2.0	0.3	32.2
Simulation, STEP	0.5	2.4	13.3	0.8 ms	10.3	8.3	1.8	0.3	36.9
Simulation, STL	0.6	2.4	13.4	0.8 ms	10.5	1.0	1.8	0.3	29.9
Simulation, OBJ	0.6	2.3	13.4	0.8 ms	10.3	16.3	1.8	0.3	45.0
Visual, GLB	0.6	2.3	14.3	0.8 ms	22.1	0.3	2.3	0.3	42.2
Visual, OBJ	0.6	2.4	14.2	1 ms	21.9	9.9	2.6	0.3	51.9

Board Repo: Board-Folk/Einstein-TC-01 Board: TC02Mini.kicad_pcb Folder Expansions / TC02Mini / Kicad Complexity 264 / 1000 (size 189, features 75) KESE features through vias, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 51, 2,290, 128 Triangles, simulation 2,815,452 in 155 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 96 MB 1.0 GB STEP 419 MB 1.1 GB STL 141 MB 972 MB OBJ 295 MB 1.8 GB Visual GLB 57 MB 1.2 GB OBJ 176 MB 1.3 GB

651. TMSAdapterTC01

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.7	4.9	0.4 ms	3.8	0.2	0.6	0.2	10.6
Simulation, STEP	0.2	0.7	4.9	0.5 ms	4.1	2.8	0.5	0.2	13.4
Simulation, STL	0.2	0.8	4.8	0.5 ms	3.8	0.3	0.6	0.3	10.8
Simulation, OBJ	0.2	0.7	4.6	0.4 ms	4.0	5.4	0.5	0.2	15.6
Visual, GLB	0.2	0.7	4.7	0.4 ms	7.7	92 ms	0.9	0.2	14.4
Visual, OBJ	0.2	0.7	4.8	0.3 ms	7.4	3.4	1.1	0.3	17.7

Board Repo: Board-Folk/Einstein-TC-01 Board: TMSAdapterTC01.kicad_pcb Folder Expansions / TMSAdapterTC01 / Kicad Complexity 238 / 1000 (size 163, features 75) KESE features through vias, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 22, 850, 24 Triangles, simulation 1,335,060 in 72 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 45 MB 542 MB STEP 191 MB 630 MB STL 67 MB 537 MB OBJ 135 MB 903 MB Visual GLB 27 MB 646 MB OBJ 83 MB 728 MB

652. V9958AdapterTC01

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.3	8.3	0.8 ms	6.5	0.3	1.1	0.3	18.2
Simulation, STEP	0.4	1.4	8.2	0.8 ms	6.6	5.1	1.0	0.3	22.9
Simulation, STL	0.4	1.3	8.1	0.5 ms	6.8	0.6	0.9	0.3	18.3
Simulation, OBJ	0.4	1.2	7.9	1 ms	6.4	10.0	1.0	0.3	27.2
Visual, GLB	0.4	1.3	7.9	0.9 ms	15.5	0.2	1.8	0.3	27.3
Visual, OBJ	0.4	1.3	8.3	0.8 ms	14.9	5.9	1.7	0.3	32.8

Board Repo: Board-Folk/Einstein-TC-01 Board: V9958AdapterTC01.kicad_pcb Folder Expansions / V9958AdapterTC01 / Kicad Complexity 276 / 1000 (size 176, features 100) KESE features through vias, custom pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 46, 1,132, 49 Triangles, simulation 1,913,332 in 118 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 64 MB 732 MB STEP 272 MB 858 MB STL 96 MB 730 MB OBJ 196 MB 1.3 GB Visual GLB 41 MB 942 MB OBJ 125 MB 978 MB

653. EinsteinTC01

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	5.5	12.5	72.6	4 ms	56.2	3.0	9.2	0.6	159.6
Simulation, STEP	6.6	12.3	72.4	3 ms	62.7	41.9	9.1	0.6	205.7
Simulation, STL	6.2	12.9	73.8	3 ms	66.7	7.0	8.6	0.6	175.7
Simulation, OBJ	6.0	12.7	70.4	3 ms	57.5	93.5	8.5	0.6	249.3
Visual, GLB	5.9	12.3	75.4	4 ms	141.9	1.7	17.1	0.5	254.7
Visual, OBJ	6.3	13.1	73.8	4 ms	131.1	52.0	15.7	0.7	292.7

Board Repo: Board-Folk/Einstein-TC-01 Board: EinsteinTC01.kicad_pcb Folder Kicad Complexity 309 / 1000 (size 234, features 75) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, drill offsets, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 346, 9,719, 769 Triangles, simulation 11,902,236 in 528 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 398 MB 3.2 GB STEP 1.7 GB 4.2 GB STL 595 MB 3.3 GB OBJ 1.3 GB 7.4 GB Visual GLB 238 MB 3.8 GB OBJ 765 MB 4.9 GB

654. EinsteinCE

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.9	6.7	37.3	2 ms	30.4	1.7	5.1	0.4	82.6
Simulation, STEP	0.8	6.2	36.1	2 ms	30.8	22.2	5.0	0.5	101.5
Simulation, STL	1.0	5.9	38.1	2 ms	30.7	3.7	5.5	0.5	85.3
Simulation, OBJ	0.9	6.0	35.8	2 ms	30.0	41.1	5.1	0.4	119.6
Visual, GLB	1.1	6.1	36.4	2 ms	78.8	0.8	8.8	0.3	132.2
Visual, OBJ	1.0	6.1	35.7	3 ms	78.9	25.2	9.3	0.3	156.5

Board Repo: Board-Folk/Einstein-TC-01 Board: EinsteinCE.kicad_pcb Folder Remix / EinsteinCE / Kicad Complexity 253 / 1000 (size 218, features 35) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 154, 6,261, 418 Triangles, simulation 7,959,458 in 329 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 265 MB 2.1 GB STEP 1.3 GB 2.8 GB STL 398 MB 2.1 GB OBJ 836 MB 4.9 GB Visual GLB 170 MB 2.6 GB OBJ 542 MB 3.4 GB

655. MegaCD

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.2	6.4	23.6	2 ms	26.0	1.3	5.1	0.4	64.9
Simulation, STEP	2.3	6.3	24.0	2 ms	26.3	16.7	4.6	0.4	80.6
Simulation, STL	2.1	6.1	22.8	2 ms	26.5	2.5	4.9	0.4	65.3
Simulation, OBJ	2.3	6.3	23.4	2 ms	25.5	38.1	4.9	0.4	100.9
Visual, GLB	2.2	6.4	23.0	2 ms	67.6	0.8	8.1	0.4	108.6
Visual, OBJ	2.2	6.4	23.6	2 ms	70.5	23.2	8.4	0.3	134.6

Board Repo: Board-Folk/MegaCD-Main-BD Board: MegaCD.kicad_pcb Folder MegaCD-837-8015-01-Rev1-MCE2 Complexity 428 / 1000 (size 293, features 135) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 103, 10,727, 883 Triangles, simulation 6,854,478 in 355 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 234 MB 2.0 GB STEP 994 MB 2.3 GB STL 343 MB 2.0 GB OBJ 733 MB 4.3 GB Visual GLB 149 MB 2.5 GB OBJ 486 MB 3.1 GB

656. MegaCD

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	3.3	7.3	25.1	1 ms	25.6	1.1	5.0	0.4	67.9
Simulation, STEP	2.2	6.2	24.1	1 ms	26.7	18.5	4.5	0.5	82.6
Simulation, STL	2.8	6.8	26.1	1 ms	30.2	3.2	4.6	0.4	74.3
Simulation, OBJ	2.9	6.0	26.0	1 ms	28.3	40.3	4.5	0.4	108.6
Visual, GLB	2.4	6.1	25.7	1 ms	71.8	0.7	9.4	0.4	116.6
Visual, OBJ	2.3	5.8	24.3	1 ms	70.0	27.4	10.9	0.4	141.0

Board Repo: Board-Folk/MegaCD-Main-BD Board: MegaCD.kicad_pcb Folder MegaCD-837-8015-Rev0-MCE1 Complexity 425 / 1000 (size 290, features 135) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 93, 9,360, 822 Triangles, simulation 6,425,034 in 355 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 220 MB 2.0 GB STEP 897 MB 2.2 GB STL 321 MB 1.9 GB OBJ 686 MB 4.1 GB Visual GLB 138 MB 2.3 GB OBJ 450 MB 2.9 GB

657. MegaCD

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	4.3	5.7	22.2	2 ms	22.5	1.0	3.7	0.4	59.9
Simulation, STEP	4.3	5.7	21.4	2 ms	22.7	15.3	3.9	0.4	73.6
Simulation, STL	4.2	5.6	21.5	1 ms	22.8	2.0	4.2	0.4	60.7
Simulation, OBJ	4.4	5.7	22.4	1 ms	24.0	39.2	4.1	0.4	100.1
Visual, GLB	4.8	5.7	22.4	2 ms	61.2	0.6	7.6	0.4	102.5
Visual, OBJ	4.3	6.1	21.9	2 ms	60.2	24.5	8.1	0.3	125.3

Board Repo: Board-Folk/MegaCD-Main-BD Board: MegaCD.kicad_pcb Folder MegaCD-837-8952-Export Complexity 424 / 1000 (size 289, features 135) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 117, 7,524, 826 Triangles, simulation 6,123,290 in 361 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 210 MB 1.9 GB STEP 862 MB 2.2 GB STL 306 MB 1.9 GB OBJ 655 MB 4.0 GB Visual GLB 137 MB 2.3 GB OBJ 445 MB 3.1 GB

658. MegaCD

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.8	2.5	0.4 ms	2.5	99 ms	0.5	0.2	6.9
Simulation, STEP	0.3	0.7	2.5	0.3 ms	2.3	2.2	0.4	0.3	8.7
Simulation, STL	0.4	0.7	2.3	0.4 ms	2.3	0.2	0.5	0.3	6.7
Simulation, OBJ	0.2	0.7	2.6	0.5 ms	2.3	4.2	0.5	0.2	10.7
Visual, GLB	0.2	0.6	2.7	0.4 ms	5.5	88 ms	0.6	0.2	10.0
Visual, OBJ	0.3	0.7	2.6	0.5 ms	5.6	2.2	0.8	0.3	12.5

Board Repo: Board-Folk/MegaCD-Main-BD Board: MegaCD.kicad_pcb Folder RAM-Adapter-837-8015-01 Complexity 251 / 1000 (size 156, features 95) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 7, 359, 27 Triangles, simulation 814,600 in 54 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 28 MB 396 MB STEP 115 MB 407 MB STL 41 MB 415 MB OBJ 82 MB 557 MB Visual GLB 16 MB 460 MB OBJ 48 MB 442 MB

659. MegaCD

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.7	2.4	0.3 ms	2.3	0.1	0.4	0.2	6.5
Simulation, STEP	0.2	0.6	2.6	0.4 ms	2.3	2.0	0.5	0.2	8.5
Simulation, STL	0.3	0.6	2.6	0.4 ms	2.3	0.3	0.4	0.2	6.7
Simulation, OBJ	0.3	0.6	2.3	0.3 ms	2.3	4.0	0.4	0.2	10.2
Visual, GLB	0.3	0.7	2.5	0.5 ms	5.7	79 ms	0.6	0.2	10.1
Visual, OBJ	0.4	0.7	2.6	0.3 ms	5.5	2.4	0.6	0.3	12.4

Board Repo: Board-Folk/MegaCD-Main-BD Board: MegaCD.kicad_pcb Folder RAM-Adapter-837-8015 Complexity 252 / 1000 (size 157, features 95) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 7, 398, 27 Triangles, simulation 817,738 in 54 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 28 MB 400 MB STEP 119 MB 413 MB STL 41 MB 391 MB OBJ 82 MB 568 MB Visual GLB 17 MB 460 MB OBJ 50 MB 461 MB

660. NeoGeoAES3_5

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	7.0	15.4	76.5	3 ms	65.1	2.4	11.5	0.6	178.5
Simulation, STEP	7.1	14.2	80.6	3 ms	73.0	40.3	11.2	0.7	227.1
Simulation, STL	6.8	14.2	76.9	3 ms	65.3	5.6	11.2	0.5	180.6
Simulation, OBJ	5.9	14.2	77.2	3 ms	63.5	104.7	10.0	0.6	276.2
Visual, GLB	6.7	15.2	77.7	3 ms	186.0	1.4	19.6	0.4	307.1
Visual, OBJ	6.3	13.2	77.2	3 ms	185.2	72.4	19.3	0.5	374.0

Board Repo: Board-Folk/NeoGeoAES-3.5 Board: NeoGeoAES3_5.kicad_pcb Complexity 368 / 1000 (size 243, features 125) KESE features through vias, slotted holes, custom pads, filled zones, copper drawings, curved board outline, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 10 (20260206) Parts, tracks, vias 298, 18,210, 1,498 Triangles, simulation 12,427,738 in 777 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 421 MB 3.6 GB STEP 2.0 GB 4.7 GB STL 621 MB 3.7 GB OBJ 1.3 GB 7.9 GB Visual GLB 290 MB 4.5 GB OBJ 940 MB 5.8 GB

661. Neptune-32x-315-5805-bypass

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.3	1.2	0.2 ms	1.1	47 ms	0.2	0.2	3.1
Simulation, STEP	0.1	0.3	1.2	0.2 ms	1.1	1.2	0.2	0.2	4.3
Simulation, STL	0.1	0.3	1.2	0.3 ms	1.1	72 ms	0.2	0.2	3.2
Simulation, OBJ	0.1	0.3	1.6	0.4 ms	1.2	1.7	0.2	0.2	5.3
Visual, GLB	0.1	0.3	1.2	0.3 ms	2.8	44 ms	0.3	0.2	5.0
Visual, OBJ	0.1	0.3	1.3	0.2 ms	3.1	1.2	0.3	0.2	6.5

Board Repo: Board-Folk/Neptune Board: Neptune-32x-315-5805-bypass.kicad_pcb Folder helpers / Neptune-32x-315-5805-bypass Complexity 234 / 1000 (size 124, features 110) KESE features through vias, padstacks, drill offsets, stack-up, dielectric εr and tanδ, castellated pads Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 1, 306, 44 Triangles, simulation 282,880 in 67 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 10 MB 224 MB STEP 49 MB 263 MB STL 14 MB 232 MB OBJ 30 MB 257 MB Visual GLB 7.5 MB 266 MB OBJ 22 MB 268 MB

662. Neptune-32x-315-5818-bypass

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.3	0.8	0.2 ms	1.1	42 ms	0.2	0.2	2.8
Simulation, STEP	0.1	0.3	0.9	0.3 ms	1.1	1.1	0.2	0.2	3.8
Simulation, STL	0.1	0.2	0.8	0.3 ms	1.1	77 ms	0.2	0.2	2.8
Simulation, OBJ	0.1	0.3	0.7	0.3 ms	1.1	1.3	0.2	0.2	4.0
Visual, GLB	0.1	0.3	0.8	0.3 ms	2.6	40 ms	0.5	0.2	4.5
Visual, OBJ	0.1	0.3	0.8	0.3 ms	2.6	1.0	0.4	0.3	5.4

Board Repo: Board-Folk/Neptune Board: Neptune-32x-315-5818-bypass.kicad_pcb Folder helpers / Neptune-32x-315-5818-bypass Complexity 173 / 1000 (size 128, features 45) KESE features through vias, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 1, 367, 65 Triangles, simulation 244,460 in 70 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 9.2 MB 253 MB STEP 47 MB 258 MB STL 12 MB 259 MB OBJ 26 MB 262 MB Visual GLB 7.5 MB 293 MB OBJ 23 MB 281 MB

663. Neptune-Region-Fix

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	67 ms	25 ms	41 ms	0.1 ms	85 ms	3 ms	11 ms	0.2	0.4
Simulation, STEP	68 ms	26 ms	34 ms	0.1 ms	79 ms	68 ms	10 ms	0.2	0.5
Simulation, STL	63 ms	23 ms	39 ms	0.1 ms	83 ms	3 ms	10 ms	0.2	0.4
Simulation, OBJ	58 ms	22 ms	43 ms	0.1 ms	77 ms	35 ms	10 ms	0.2	0.4
Visual, GLB	58 ms	23 ms	36 ms	0.1 ms	0.2	3 ms	25 ms	0.2	0.5
Visual, OBJ	53 ms	20 ms	41 ms	0.1 ms	0.2	31 ms	23 ms	0.2	0.5

Board Repo: Board-Folk/Neptune Board: Neptune-Region-Fix.kicad_pcb Folder helpers / Neptune-Region-Fix Complexity 87 / 1000 (size 62, features 25) KESE features through vias, rounded, trapezoid or chamfered pads Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 0, 12, 1 Triangles, simulation 8,908 in 9 parts Note no components Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 336 kB 59 MB STEP 1.7 MB 61 MB STL 446 kB 60 MB OBJ 853 kB 63 MB Visual GLB 299 kB 83 MB OBJ 754 kB 83 MB

664. Neptune

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.5	10.8	37.4	2 ms	41.5	2.1	8.3	0.6	103.3
Simulation, STEP	2.5	10.4	36.6	2 ms	41.6	24.4	8.0	0.5	124.0
Simulation, STL	2.6	10.5	37.1	2 ms	42.2	4.5	8.6	0.6	106.1
Simulation, OBJ	2.6	11.1	37.5	2 ms	43.3	56.7	8.1	0.5	159.8
Visual, GLB	2.5	11.0	36.8	2 ms	128.6	1.3	14.9	0.4	195.4
Visual, OBJ	2.7	11.0	37.8	2 ms	126.1	36.0	14.8	0.5	229.0

Board Repo: Board-Folk/Neptune Board: Neptune.kicad_pcb Complexity 468 / 1000 (size 318, features 150) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 374, 11,140, 1,391 Triangles, simulation 9,804,248 in 748 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 339 MB 2.5 GB STEP 1.5 GB 3.4 GB STL 490 MB 2.5 GB OBJ 1.1 GB 6.2 GB Visual GLB 223 MB 3.5 GB OBJ 725 MB 4.6 GB

665. Oric

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	3.5	18.8	0.8 ms	15.7	0.6	2.5	0.2	42.1
Simulation, STEP	0.6	3.7	18.9	2 ms	14.3	10.5	2.2	0.3	50.4
Simulation, STL	0.6	3.3	18.2	0.8 ms	14.6	1.4	2.2	0.3	40.7
Simulation, OBJ	0.6	3.3	18.0	2 ms	14.9	22.0	2.1	0.2	61.2
Visual, GLB	0.6	3.5	17.6	0.8 ms	33.1	0.4	4.4	0.2	59.8
Visual, OBJ	0.7	3.7	18.4	0.9 ms	32.3	15.7	5.2	0.3	76.2

Board Repo: Board-Folk/Oric-Remix Board: Oric.kicad_pcb Folder Archive / IssueAv1.1 Complexity 268 / 1000 (size 203, features 65) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 129, 2,835, 234 Triangles, simulation 4,060,494 in 203 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 136 MB 1.2 GB STEP 566 MB 1.6 GB STL 203 MB 1.2 GB OBJ 426 MB 2.5 GB Visual GLB 87 MB 1.5 GB OBJ 275 MB 1.9 GB

666. Oric-PS2USB

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.5	3.6	0.5 ms	2.7	0.1	0.4	0.2	7.8
Simulation, STEP	0.2	0.6	3.5	0.4 ms	2.6	2.1	0.4	0.2	9.6
Simulation, STL	0.2	0.6	3.5	0.5 ms	2.7	0.2	0.4	0.2	7.8
Simulation, OBJ	0.2	0.5	3.4	0.5 ms	2.9	4.6	0.4	0.2	12.3
Visual, GLB	0.2	0.6	3.5	0.5 ms	6.4	70 ms	0.6	0.2	11.4
Visual, OBJ	0.2	0.6	3.6	0.7 ms	6.4	2.7	0.7	0.2	14.3

Board Repo: Board-Folk/Oric-Remix Board: Oric-PS2USB.kicad_pcb Folder Expansions / Oric-PS2USB / Kicad Complexity 234 / 1000 (size 149, features 85) KESE features through vias, slotted holes, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 11, 554, 26 Triangles, simulation 859,924 in 74 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 29 MB 461 MB STEP 143 MB 456 MB STL 43 MB 466 MB OBJ 88 MB 611 MB Visual GLB 17 MB 514 MB OBJ 52 MB 492 MB

667. Oric

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	3.8	19.7	0.9 ms	15.1	0.6	2.4	0.3	42.4
Simulation, STEP	0.7	3.6	20.2	1 ms	15.6	11.6	2.7	0.3	54.8
Simulation, STL	0.7	3.8	20.8	2 ms	16.1	1.6	2.6	0.3	45.7
Simulation, OBJ	0.6	3.7	19.2	0.9 ms	15.4	23.7	2.6	0.3	65.5
Visual, GLB	0.7	3.8	20.5	2 ms	34.5	0.4	4.4	0.3	64.6
Visual, OBJ	0.7	3.9	20.8	1 ms	34.6	15.2	4.8	0.3	80.1

Board Repo: Board-Folk/Oric-Remix Board: Oric.kicad_pcb Folder Kicad Complexity 268 / 1000 (size 203, features 65) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 129, 2,832, 234 Triangles, simulation 4,065,754 in 203 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 137 MB 1.2 GB STEP 568 MB 1.5 GB STL 203 MB 1.3 GB OBJ 426 MB 2.6 GB Visual GLB 87 MB 1.8 GB OBJ 275 MB 1.8 GB

668. PCE

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.3	2.9	13.4	0.9 ms	12.4	0.6	1.9	0.3	32.7
Simulation, STEP	1.4	3.1	13.2	1.0 ms	12.8	8.7	1.8	0.3	41.3
Simulation, STL	1.2	2.8	13.6	1 ms	12.6	1.0	2.1	0.3	33.5
Simulation, OBJ	1.3	2.8	13.6	0.9 ms	12.8	17.7	2.0	0.3	50.5
Visual, GLB	1.3	2.8	13.8	0.9 ms	31.5	0.4	3.8	0.2	53.7
Visual, OBJ	1.3	2.8	13.3	1 ms	31.3	13.7	4.0	0.3	66.6

Board Repo: Board-Folk/PC-Engine Board: PCE.kicad_pcb Complexity 325 / 1000 (size 210, features 115) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 123, 4,523, 290 Triangles, simulation 3,209,090 in 199 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 112 MB 1.1 GB STEP 614 MB 1.3 GB STL 160 MB 1.2 GB OBJ 345 MB 2.1 GB Visual GLB 87 MB 1.5 GB OBJ 273 MB 1.8 GB

669. PCE

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	5.0	9.3	37.0	2 ms	40.5	1.5	5.1	0.4	98.8
Simulation, STEP	5.6	9.5	36.2	2 ms	40.3	27.0	5.1	0.4	124.1
Simulation, STL	5.0	9.6	36.5	3 ms	40.2	3.2	5.1	0.5	100.1
Simulation, OBJ	5.4	9.2	36.1	3 ms	39.2	55.7	5.4	0.5	151.5
Visual, GLB	5.3	10.0	38.4	4 ms	108.7	1.3	12.6	0.3	176.7
Visual, OBJ	5.0	9.3	35.9	2 ms	109.2	43.4	13.1	0.5	216.4

Board Repo: Board-Folk/PC-Engine-Duo Board: PCE.kicad_pcb Complexity 414 / 1000 (size 309, features 105) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 618, 15,551, 1,491 Triangles, simulation 8,529,616 in 690 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 295 MB 2.7 GB STEP 1.6 GB 3.5 GB STL 427 MB 2.6 GB OBJ 921 MB 5.5 GB Visual GLB 256 MB 3.9 GB OBJ 826 MB 5.2 GB

670. PCE

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.1	3.7	10.5	0.9 ms	13.1	0.6	1.7	0.3	32.1
Simulation, STEP	2.2	3.7	10.3	1 ms	13.1	8.5	1.7	0.3	39.8
Simulation, STL	2.0	3.5	10.2	1 ms	13.0	1.2	1.8	0.3	32.0
Simulation, OBJ	2.1	3.4	9.6	0.9 ms	13.5	16.5	1.9	0.3	47.3
Visual, GLB	2.2	3.5	10.1	1 ms	29.6	0.4	4.4	0.3	50.4
Visual, OBJ	2.2	3.6	9.9	1 ms	29.3	13.2	4.3	0.3	62.7

Board Repo: Board-Folk/PC-Engine-GT Board: PCE.kicad_pcb Complexity 348 / 1000 (size 233, features 115) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 195, 4,794, 322 Triangles, simulation 3,256,982 in 307 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 113 MB 1.2 GB STEP 511 MB 1.3 GB STL 163 MB 1.2 GB OBJ 349 MB 2.1 GB Visual GLB 81 MB 1.3 GB OBJ 255 MB 1.7 GB

671. TRS80I-Charmap

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.3	1.4	0.3 ms	1.1	81 ms	0.3	0.2	3.5
Simulation, STEP	0.1	0.3	1.4	0.3 ms	1.1	1.2	0.2	0.2	4.6
Simulation, STL	0.1	0.3	1.4	0.3 ms	1.1	80 ms	0.2	0.2	3.4
Simulation, OBJ	0.1	0.3	1.3	0.3 ms	1.1	1.8	0.2	0.3	5.1
Visual, GLB	0.1	0.3	1.4	0.2 ms	2.5	35 ms	0.2	0.2	4.9
Visual, OBJ	0.1	0.3	1.4	0.3 ms	2.3	1.2	0.2	0.2	5.7

Board Repo: Board-Folk/TRS80IJP Board: TRS80I-Charmap.kicad_pcb Folder Extras / Charmap / Kicad Complexity 163 / 1000 (size 123, features 40) KESE features rounded, trapezoid or chamfered pads, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 6 (20211014) Parts, tracks, vias 5, 197, 0 Triangles, simulation 323,104 in 38 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 11 MB 238 MB STEP 42 MB 261 MB STL 16 MB 231 MB OBJ 32 MB 266 MB Visual GLB 6.5 MB 238 MB OBJ 19 MB 242 MB

672. TRSG3JPMod

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	1.4	0.2 ms	1.2	56 ms	0.2	0.3	3.5
Simulation, STEP	0.1	0.3	1.3	0.4 ms	1.2	1.2	0.2	0.3	4.5
Simulation, STL	0.1	0.3	1.2	0.2 ms	1.1	0.1	0.2	0.2	3.3
Simulation, OBJ	0.2	0.3	1.3	0.4 ms	1.2	1.8	0.2	0.3	5.3
Visual, GLB	0.1	0.3	1.4	0.2 ms	2.5	36 ms	0.3	0.3	4.8
Visual, OBJ	0.1	0.3	1.4	0.2 ms	2.6	1.3	0.2	0.2	6.1

Board Repo: Board-Folk/TRS80IJP Board: TRSG3JPMod.kicad_pcb Folder Extras / TRSG3Mod / TRSG3JPModv1 Complexity 179 / 1000 (size 114, features 65) KESE features through vias, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 3, 129, 8 Triangles, simulation 282,270 in 33 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 9.8 MB 232 MB STEP 47 MB 249 MB STL 14 MB 227 MB OBJ 28 MB 242 MB Visual GLB 5.8 MB 237 MB OBJ 17 MB 236 MB

673. TRSG3Mod

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	1.2	0.3 ms	1.0	45 ms	0.2	0.2	3.0
Simulation, STEP	0.1	0.2	1.1	0.2 ms	1.0	1.1	0.2	0.2	3.9
Simulation, STL	0.1	0.2	1.2	0.2 ms	1.0	87 ms	0.2	0.2	3.0
Simulation, OBJ	0.1	0.2	1.1	0.2 ms	1.0	1.5	0.2	0.2	4.3
Visual, GLB	0.1	0.2	1.2	0.2 ms	2.4	28 ms	0.2	0.2	4.3
Visual, OBJ	0.1	0.2	1.1	0.2 ms	2.3	0.9	0.2	0.2	5.1

Board Repo: Board-Folk/TRS80IJP Board: TRSG3Mod.kicad_pcb Folder Extras / TRSG3Mod / TRSG3Modv1 Complexity 198 / 1000 (size 123, features 75) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 6, 153, 10 Triangles, simulation 308,292 in 34 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 11 MB 238 MB STEP 52 MB 261 MB STL 15 MB 243 MB OBJ 31 MB 245 MB Visual GLB 6.6 MB 260 MB OBJ 19 MB 262 MB

674. TRS80IJP_1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	4.9	11.4	52.1	2 ms	42.3	2.1	5.8	0.5	119.0
Simulation, STEP	4.5	10.8	56.2	2 ms	42.3	26.1	5.9	0.5	146.3
Simulation, STL	5.2	11.0	54.8	6 ms	42.2	5.4	6.5	0.5	125.6
Simulation, OBJ	5.0	11.2	51.0	3 ms	39.9	65.1	6.4	0.6	179.2
Visual, GLB	5.0	10.2	53.8	4 ms	101.5	1.4	12.4	0.4	184.6
Visual, OBJ	4.7	10.9	50.5	3 ms	106.4	38.3	11.6	0.5	222.9

Board Repo: Board-Folk/TRS80IJP Board: TRS80IJP_1.kicad_pcb Folder v1.1 / Kicad Complexity 297 / 1000 (size 232, features 65) KESE features through vias, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 254, 10,574, 737 Triangles, simulation 9,938,980 in 419 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 335 MB 3.1 GB STEP 1.5 GB 3.7 GB STL 497 MB 3.1 GB OBJ 1.1 GB 6.2 GB Visual GLB 223 MB 3.5 GB OBJ 715 MB 4.6 GB

675. TRS80ILCMod

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	79 ms	0.2	0.9	0.2 ms	1.0	37 ms	0.1	0.2	2.5
Simulation, STEP	87 ms	0.2	1.0	0.2 ms	1.1	1.0	0.1	0.2	3.6
Simulation, STL	86 ms	0.2	0.9	0.1 ms	1.0	58 ms	0.1	0.2	2.6
Simulation, OBJ	83 ms	0.2	0.9	0.2 ms	0.9	1.3	0.1	0.2	3.7
Visual, GLB	86 ms	0.2	0.9	0.2 ms	1.7	19 ms	0.1	0.2	3.2
Visual, OBJ	83 ms	0.2	0.9	0.2 ms	1.7	0.7	0.1	0.2	3.9

Board Repo: Board-Folk/TRS80IUS Board: TRS80ILCMod.kicad_pcb Folder Extras / TRS80ILCMod / Kicad Complexity 139 / 1000 (size 109, features 30) KESE features stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 5, 83, 0 Triangles, simulation 246,726 in 28 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 8.2 MB 218 MB STEP 31 MB 236 MB STL 12 MB 213 MB OBJ 24 MB 217 MB Visual GLB 4.5 MB 206 MB OBJ 13 MB 212 MB

676. TRS80IUS

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	4.6	8.6	50.1	2 ms	43.5	2.1	6.7	0.5	116.2
Simulation, STEP	4.9	8.7	48.0	3 ms	45.4	28.4	6.7	0.5	142.5
Simulation, STL	4.4	9.5	52.8	3 ms	46.6	4.6	7.3	0.5	125.7
Simulation, OBJ	4.8	9.7	49.9	2 ms	39.7	61.4	6.5	0.5	172.5
Visual, GLB	5.3	8.6	46.3	2 ms	100.2	1.0	10.0	0.4	171.7
Visual, OBJ	4.7	8.0	50.0	17 ms	112.8	40.2	10.4	0.4	226.5

Board Repo: Board-Folk/TRS80IUS Board: TRS80IUS.kicad_pcb Folder v1.1 / Kicad Complexity 308 / 1000 (size 228, features 80) KESE features through vias, custom pads, filled zones, copper drawings, copper text, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 231, 9,962, 380 Triangles, simulation 8,820,422 in 392 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 296 MB 2.4 GB STEP 1.3 GB 3.3 GB STL 441 MB 2.5 GB OBJ 933 MB 5.5 GB Visual GLB 183 MB 3.0 GB OBJ 587 MB 3.7 GB

677. Debug_Adapter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.5	1.4	0.3 ms	1.7	67 ms	0.2	0.2	4.3
Simulation, STEP	0.2	0.5	1.3	0.5 ms	1.7	1.6	0.2	0.2	5.8
Simulation, STL	0.2	0.5	1.3	0.3 ms	1.8	0.1	0.2	0.3	4.4
Simulation, OBJ	0.2	0.5	1.3	0.3 ms	1.7	1.9	0.2	0.3	6.1
Visual, GLB	0.2	0.5	1.4	0.3 ms	3.2	52 ms	0.4	0.2	6.0
Visual, OBJ	0.2	0.5	1.3	0.3 ms	3.4	1.6	0.4	0.3	7.7

Board Repo: bogdan8266/h616-board Board: Debug_Adapter.kicad_pcb Folder Hardware / Debug_Adapter Complexity 261 / 1000 (size 161, features 100) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text, curved board outline, knockout text Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 25, 251, 179 Triangles, simulation 370,438 in 57 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 13 MB 306 MB STEP 50 MB 338 MB STL 19 MB 299 MB OBJ 37 MB 298 MB Visual GLB 11 MB 334 MB OBJ 32 MB 337 MB

678. H616_devboard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	3.1	10.4	2 ms	13.1	0.6	1.7	0.3	29.8
Simulation, STEP	0.6	3.0	10.4	1 ms	13.3	8.6	2.0	0.4	38.3
Simulation, STL	0.6	2.9	10.1	1 ms	13.5	1.5	1.9	0.3	30.7
Simulation, OBJ	0.6	3.0	10.4	1 ms	13.7	20.0	1.8	0.3	49.8
Visual, GLB	0.6	2.7	10.3	2 ms	37.5	0.4	3.3	0.2	55.1
Visual, OBJ	0.6	2.8	11.0	1 ms	38.1	10.5	3.8	0.2	67.0

Board Repo: bogdan8266/h616-board Board: H616_devboard.kicad_pcb Folder Hardware / H616_DDR3 Complexity 412 / 1000 (size 297, features 115) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, drill offsets, arc tracks, copper text, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 8 File format KiCad 10 (20260206) Parts, tracks, vias 167, 1,531, 263 Triangles, simulation 4,056,192 in 464 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 131 MB 1.1 GB STEP 460 MB 1.3 GB STL 203 MB 1.1 GB OBJ 426 MB 2.5 GB Visual GLB 73 MB 1.3 GB OBJ 230 MB 1.5 GB

679. H616_devboard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	3.7	10.8	2 ms	16.3	0.6	1.5	0.3	33.9
Simulation, STEP	0.8	3.7	10.3	1 ms	15.3	9.0	1.5	0.3	40.9
Simulation, STL	0.8	3.6	10.2	2 ms	15.0	1.3	1.6	0.3	32.8
Simulation, OBJ	0.8	3.6	10.4	0.7 ms	15.7	16.6	1.5	0.3	48.9
Visual, GLB	0.8	3.5	10.2	0.6 ms	31.0	0.4	3.3	0.2	49.4
Visual, OBJ	0.8	3.5	10.2	1 ms	31.1	12.8	4.2	0.2	62.9

Board Repo: bogdan8266/h616-board Board: H616_devboard.kicad_pcb Folder Hardware / H616_LPDDR4 Complexity 447 / 1000 (size 297, features 150) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, copper text, curved board outline, knockout text, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 152, 6,210, 715 Triangles, simulation 4,013,826 in 333 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 135 MB 1.3 GB STEP 567 MB 1.7 GB STL 201 MB 1.3 GB OBJ 422 MB 2.5 GB Visual GLB 99 MB 1.7 GB OBJ 316 MB 2.2 GB

680. SmartPrintCoreH7x

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.4	10.3	42.8	1 ms	46.4	1.7	5.0	0.4	109.0
Simulation, STEP	2.4	9.9	43.2	2 ms	46.0	25.5	5.1	0.4	132.5
Simulation, STL	2.4	10.1	41.5	1 ms	45.8	3.5	5.3	0.4	108.9
Simulation, OBJ	2.4	9.7	41.7	1 ms	44.3	48.0	5.1	0.4	151.6
Visual, GLB	2.3	9.6	41.8	2 ms	123.1	1.2	14.7	0.4	193.2
Visual, OBJ	2.4	9.6	41.3	1 ms	125.7	39.2	14.1	0.4	232.7

Board Repo: BoltzRnD/SmartPrintCoreH7x Board: SmartPrintCoreH7x.kicad_pcb Folder SmartPrintCoreH7x Complexity 410 / 1000 (size 280, features 130) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 541, 8,490, 1,506 Triangles, simulation 7,949,190 in 428 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 273 MB 2.7 GB STEP 1.5 GB 3.1 GB STL 397 MB 2.8 GB OBJ 851 MB 5.0 GB Visual GLB 238 MB 3.5 GB OBJ 764 MB 4.9 GB

681. other-m68k

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.1	6.0	18.7	2 ms	21.2	1.1	3.1	0.3	51.5
Simulation, STEP	1.1	6.2	19.5	1.0 ms	20.1	13.3	3.2	0.3	63.9
Simulation, STL	1.1	6.0	19.3	2 ms	20.7	2.6	3.1	0.4	53.2
Simulation, OBJ	1.1	6.2	19.3	1 ms	20.8	33.4	3.1	0.4	84.3
Visual, GLB	1.1	6.3	19.8	0.9 ms	43.1	0.5	7.1	0.3	78.1
Visual, OBJ	1.1	6.3	19.6	2 ms	43.2	15.9	7.0	0.3	93.4

Board Repo: bradgrantham/other-m68k Board: other-m68k.kicad_pcb Folder kicad / release Complexity 349 / 1000 (size 284, features 65) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 163, 6,720, 665 Triangles, simulation 6,929,688 in 267 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 234 MB 2.0 GB STEP 837 MB 2.3 GB STL 347 MB 1.9 GB OBJ 734 MB 4.3 GB Visual GLB 126 MB 2.1 GB OBJ 403 MB 2.6 GB

682. ClassicIIReloaded

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	6.6	11.4	37.7	2 ms	47.1	2.1	6.4	0.5	111.8
Simulation, STEP	6.8	11.9	39.4	2 ms	48.4	28.7	6.6	0.5	142.3
Simulation, STL	7.1	11.7	38.8	2 ms	47.0	4.2	6.1	0.5	115.4
Simulation, OBJ	7.0	12.5	40.7	2 ms	48.2	82.5	6.9	0.5	198.3
Visual, GLB	6.9	11.6	40.3	3 ms	116.8	1.1	12.5	0.4	189.7
Visual, OBJ	7.1	12.0	40.5	2 ms	120.9	43.4	11.4	0.4	235.7

Board Repo: btb/ClassicII Board: ClassicIIReloaded.kicad_pcb Folder ClassicIIReloaded Complexity 450 / 1000 (size 305, features 145) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, drill offsets, arc tracks, filled zones, copper drawings, copper text, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 290, 10,450, 1,255 Triangles, simulation 11,075,382 in 454 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 378 MB 2.7 GB STEP 1.5 GB 3.6 GB STL 554 MB 2.5 GB OBJ 1.2 GB 7.1 GB Visual GLB 223 MB 3.7 GB OBJ 726 MB 4.9 GB

683. ClassicIIRevB

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	8.9	9.8	35.0	1 ms	42.5	1.9	6.0	0.7	104.9
Simulation, STEP	9.6	11.1	36.8	2 ms	44.9	25.1	5.6	0.5	133.5
Simulation, STL	8.9	9.8	35.6	2 ms	42.0	4.2	5.6	0.5	106.6
Simulation, OBJ	8.8	9.6	35.9	2 ms	42.3	62.1	6.2	0.5	165.5
Visual, GLB	8.2	9.6	36.5	4 ms	106.1	1.1	10.9	0.4	172.8
Visual, OBJ	8.8	10.1	36.0	2 ms	107.6	35.2	10.1	0.4	208.2

Board Repo: btb/ClassicII Board: ClassicIIRevB.kicad_pcb Folder ClassicIIRevB Complexity 449 / 1000 (size 304, features 145) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, drill offsets, arc tracks, filled zones, copper drawings, copper text, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 281, 10,002, 1,306 Triangles, simulation 10,662,252 in 454 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 365 MB 2.6 GB STEP 1.4 GB 3.6 GB STL 533 MB 2.6 GB OBJ 1.1 GB 6.9 GB Visual GLB 217 MB 3.6 GB OBJ 706 MB 4.8 GB

684. ButterStick

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.6	6.6	24.3	2 ms	27.9	1.4	3.3	0.4	65.4
Simulation, STEP	1.6	6.4	24.3	0.9 ms	28.8	17.2	3.1	0.4	81.8
Simulation, STL	1.6	6.6	24.2	2 ms	27.0	2.4	3.2	0.4	65.3
Simulation, OBJ	1.6	6.9	25.1	1 ms	27.7	41.4	3.2	0.4	106.2
Visual, GLB	1.6	6.7	24.3	2 ms	52.3	0.6	5.6	0.3	91.4
Visual, OBJ	1.8	7.1	24.3	2 ms	48.8	22.7	6.4	0.4	111.5

Board Repo: butterstick-fpga/butterstick-hardware Board: ButterStick.kicad_pcb Folder hardware / ButterStick_r0.1 Complexity 398 / 1000 (size 318, features 80) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline Tested 9th November 2026 Copper layers 6 File format KiCad 5 (20171130) Parts, tracks, vias 181, 17,618, 671 Triangles, simulation 6,232,652 in 340 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 214 MB 1.6 GB STEP 881 MB 2.3 GB STL 312 MB 1.7 GB OBJ 667 MB 4.0 GB Visual GLB 114 MB 2.0 GB OBJ 374 MB 2.6 GB

685. ButterStick

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.1	5.9	19.9	1 ms	22.5	0.9	2.6	0.3	53.3
Simulation, STEP	1.1	5.9	20.8	1 ms	22.7	13.0	2.7	0.3	66.7
Simulation, STL	1.2	5.7	21.5	0.8 ms	22.7	2.1	3.3	0.4	56.9
Simulation, OBJ	1.2	5.9	21.2	1 ms	22.4	31.5	2.8	0.3	85.3
Visual, GLB	1.2	6.2	20.1	1.0 ms	42.1	0.5	5.8	0.3	76.2
Visual, OBJ	1.2	5.9	20.5	1 ms	43.5	15.1	4.8	0.3	91.4

Board Repo: butterstick-fpga/butterstick-hardware Board: ButterStick.kicad_pcb Folder hardware / ButterStick_r0.2 Complexity 410 / 1000 (size 320, features 90) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text, curved board outline Tested 9th November 2026 Copper layers 6 File format KiCad 5 (20171130) Parts, tracks, vias 223, 16,942, 792 Triangles, simulation 6,727,172 in 339 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 231 MB 1.7 GB STEP 896 MB 2.3 GB STL 336 MB 1.6 GB OBJ 722 MB 4.2 GB Visual GLB 117 MB 2.1 GB OBJ 383 MB 2.6 GB

686. ButterStick

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.4	8.4	23.0	2 ms	34.1	1.6	5.1	0.5	75.0
Simulation, STEP	2.4	8.7	22.4	2 ms	33.3	18.1	5.2	0.4	90.4
Simulation, STL	2.2	8.5	22.7	2 ms	33.9	3.7	5.2	0.5	76.7
Simulation, OBJ	2.3	8.8	22.7	1 ms	33.8	62.1	5.1	0.4	135.3
Visual, GLB	2.3	9.1	23.0	2 ms	86.7	0.8	7.4	0.4	129.6
Visual, OBJ	2.4	9.4	24.2	1 ms	92.7	26.0	8.7	0.4	163.9

Board Repo: butterstick-fpga/butterstick-hardware Board: ButterStick.kicad_pcb Folder hardware / ButterStick_r1.0 Complexity 491 / 1000 (size 341, features 150) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, copper text, curved board outline, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 8 File format KiCad 6 (20211014) Parts, tracks, vias 327, 19,487, 1,061 Triangles, simulation 10,425,092 in 367 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 345 MB 2.1 GB STEP 1.1 GB 3.1 GB STL 521 MB 2.1 GB OBJ 1.1 GB 6.5 GB Visual GLB 154 MB 2.8 GB OBJ 520 MB 3.5 GB

687. 250407_

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.0	6.7	54.4	2 ms	42.1	1.5	7.6	0.5	113.9
Simulation, STEP	1.1	7.2	50.4	3 ms	42.2	25.0	6.7	0.5	133.1
Simulation, STL	1.0	7.1	51.7	3 ms	44.6	4.6	8.5	0.4	117.9
Simulation, OBJ	1.1	7.2	53.3	3 ms	48.3	60.9	7.3	0.5	178.6
Visual, GLB	1.4	7.2	51.6	2 ms	93.9	0.8	11.6	0.4	166.9
Visual, OBJ	1.1	7.0	49.6	3 ms	88.2	24.3	11.3	0.4	181.9

Board Repo: bwack/C64-250407-Replica-KiCad Board: 250407_.kicad_pcb Complexity 283 / 1000 (size 223, features 60) KESE features through vias, custom pads, filled zones, copper drawings Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 215, 6,552, 574 Triangles, simulation 8,877,004 in 261 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 301 MB 2.3 GB STEP 1.4 GB 3.1 GB STL 444 MB 2.3 GB OBJ 949 MB 5.6 GB Visual GLB 152 MB 2.5 GB OBJ 484 MB 3.2 GB

688. C64-250469-KiCad

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	3.3	6.4	41.2	1 ms	46.5	1.4	5.7	0.5	104.9
Simulation, STEP	3.3	6.3	41.1	1 ms	46.1	22.9	5.2	0.5	125.3
Simulation, STL	3.4	6.7	40.7	1 ms	45.4	3.9	6.1	0.5	106.8
Simulation, OBJ	3.3	6.2	41.9	1 ms	46.1	48.2	6.0	0.4	152.2
Visual, GLB	3.3	6.0	37.9	1 ms	95.1	0.9	9.2	0.3	152.7
Visual, OBJ	3.4	6.5	39.9	0.9 ms	98.6	32.6	10.5	0.4	191.9

Board Repo: bwack/C64C-250469-KiCAD-Replica Board: C64-250469-KiCad.kicad_pcb Complexity 322 / 1000 (size 222, features 100) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 to 10th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 138, 8,544, 642 Triangles, simulation 8,242,170 in 213 parts Verifier PASS in all six runs Run again Simulation, GLB; Simulation, STEP; Simulation, STL; Simulation, OBJ: failed in the corpus run, run again with fixes to KESE made after the corpus run, and passed

File type File size Peak memory used Simulation GLB 280 MB 2.3 GB STEP 1.4 GB 3.1 GB STL 412 MB 2.3 GB OBJ 880 MB 5.2 GB Visual GLB 191 MB 3.0 GB OBJ 615 MB 3.8 GB

689. audio

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	0.5	2.0	0.4 ms	2.3	75 ms	0.3	0.2	5.7
Simulation, STEP	0.3	0.5	2.0	0.3 ms	2.8	1.9	0.3	0.3	7.9
Simulation, STL	0.3	0.4	1.9	0.3 ms	2.6	0.1	0.3	0.2	5.9
Simulation, OBJ	0.4	0.5	1.9	0.3 ms	2.5	2.5	0.3	0.3	8.3
Visual, GLB	0.2	0.5	1.9	0.3 ms	4.7	58 ms	0.4	0.2	8.0
Visual, OBJ	0.3	0.6	2.2	0.3 ms	4.8	2.3	0.7	0.3	11.3

Board Repo: byrantech/laptop Board: audio.kicad_pcb Folder audio Complexity 291 / 1000 (size 196, features 95) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, TrueType text Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241007) Parts, tracks, vias 41, 244, 58 Triangles, simulation 416,276 in 71 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 14 MB 272 MB STEP 74 MB 305 MB STL 21 MB 272 MB OBJ 42 MB 313 MB Visual GLB 12 MB 318 MB OBJ 35 MB 310 MB

690. encoder

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	97 ms	45 ms	0.2	0.2 ms	0.4	8 ms	35 ms	0.3	1.1
Simulation, STEP	94 ms	53 ms	0.3	0.1 ms	0.4	0.3	36 ms	0.3	1.4
Simulation, STL	76 ms	49 ms	0.2	0.1 ms	0.5	12 ms	39 ms	0.3	1.1
Simulation, OBJ	80 ms	50 ms	0.3	0.3 ms	0.5	0.3	43 ms	0.2	1.4
Visual, GLB	78 ms	49 ms	0.2	0.1 ms	0.5	7 ms	58 ms	0.2	1.2
Visual, OBJ	99 ms	61 ms	0.2	0.1 ms	0.5	0.1	48 ms	0.2	1.3

Board Repo: byrantech/laptop Board: encoder.kicad_pcb Folder haptic / encoder Complexity 101 / 1000 (size 81, features 20) KESE features rounded, trapezoid or chamfered pads, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20240225) Parts, tracks, vias 2, 24, 0 Triangles, simulation 43,206 in 17 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 1.5 MB 67 MB STEP 7.1 MB 72 MB STL 2.2 MB 68 MB OBJ 4.1 MB 77 MB Visual GLB 990 kB 102 MB OBJ 2.7 MB 103 MB

691. keyboard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.2	3.5	14.0	0.8 ms	14.2	0.4	1.3	0.3	34.9
Simulation, STEP	1.2	3.6	13.7	0.5 ms	14.5	8.9	1.3	0.3	43.5
Simulation, STL	1.2	3.5	13.8	0.4 ms	14.6	0.8	1.3	0.3	35.5
Simulation, OBJ	1.2	3.5	13.8	1 ms	14.5	16.0	1.5	0.3	50.7
Visual, GLB	1.3	3.6	14.2	1 ms	29.4	0.4	4.0	0.3	53.2
Visual, OBJ	1.4	3.7	14.5	0.5 ms	28.1	13.6	4.0	0.3	65.5

Board Repo: byrantech/laptop Board: keyboard.kicad_pcb Folder keyboard Complexity 327 / 1000 (size 247, features 80) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, TrueType text Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20240225) Parts, tracks, vias 208, 1,484, 571 Triangles, simulation 2,715,872 in 171 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 94 MB 1.1 GB STEP 491 MB 1.5 GB STL 136 MB 1.1 GB OBJ 290 MB 1.9 GB Visual GLB 84 MB 1.4 GB OBJ 261 MB 1.8 GB

692. protector

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	61 ms	0.2	1.2	0.2 ms	0.7	34 ms	97 ms	0.2	2.5
Simulation, STEP	57 ms	0.2	0.9	0.2 ms	0.7	0.9	0.1	0.2	3.2
Simulation, STL	54 ms	0.2	1.0	0.2 ms	0.8	51 ms	97 ms	0.2	2.4
Simulation, OBJ	54 ms	0.2	1.0	0.2 ms	0.7	0.8	96 ms	0.2	3.0
Visual, GLB	53 ms	0.2	1.0	0.2 ms	1.7	20 ms	0.2	0.3	3.4
Visual, OBJ	55 ms	0.2	1.0	0.2 ms	1.6	0.6	0.1	0.2	3.8

Board Repo: byrantech/laptop Board: protector.kicad_pcb Folder keyboard / protector Complexity 218 / 1000 (size 133, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, copper text, knockout text, TrueType text Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20240225) Parts, tracks, vias 6, 37, 97 Triangles, simulation 203,696 in 21 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 6.9 MB 193 MB STEP 23 MB 202 MB STL 10 MB 196 MB OBJ 20 MB 194 MB Visual GLB 4.5 MB 162 MB OBJ 13 MB 159 MB

693. display_eval

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.4	1.5	0.4 ms	1.9	0.1	0.2	0.2	4.5
Simulation, STEP	0.1	0.5	1.4	0.3 ms	1.7	1.4	0.2	0.2	5.6
Simulation, STL	0.1	0.4	1.3	0.2 ms	1.8	0.1	0.2	0.2	4.1
Simulation, OBJ	0.1	0.4	1.3	0.2 ms	1.8	2.3	0.3	0.2	6.4
Visual, GLB	0.1	0.4	1.4	0.4 ms	3.8	59 ms	0.4	0.2	6.3
Visual, OBJ	0.1	0.5	1.5	0.3 ms	3.3	1.6	0.5	0.2	7.6

Board Repo: byrantech/laptop Board: display_eval.kicad_pcb Folder motherboard / display_eval Complexity 296 / 1000 (size 171, features 125) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20240225) Parts, tracks, vias 10, 577, 108 Triangles, simulation 523,320 in 47 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 18 MB 311 MB STEP 66 MB 353 MB STL 26 MB 286 MB OBJ 52 MB 383 MB Visual GLB 12 MB 322 MB OBJ 36 MB 348 MB

694. display_eval_short

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	87 ms	0.2	0.7	0.2 ms	0.8	31 ms	0.1	0.3	2.2
Simulation, STEP	89 ms	0.2	0.6	0.2 ms	0.8	1.0	0.1	0.2	3.0
Simulation, STL	0.1	0.2	0.6	0.2 ms	0.8	48 ms	0.1	0.3	2.1
Simulation, OBJ	82 ms	0.2	0.6	0.2 ms	0.8	1.0	0.1	0.2	3.0
Visual, GLB	82 ms	0.2	0.6	0.2 ms	1.9	21 ms	0.1	0.2	3.2
Visual, OBJ	90 ms	0.2	0.6	0.2 ms	2.0	0.7	0.1	0.2	3.9

Board Repo: byrantech/laptop Board: display_eval_short.kicad_pcb Folder motherboard / display_eval_short Complexity 224 / 1000 (size 134, features 90) KESE features through vias, filled zones, curved board outline, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20240225) Parts, tracks, vias 4, 121, 13 Triangles, simulation 165,308 in 43 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 5.9 MB 174 MB STEP 25 MB 188 MB STL 8.3 MB 184 MB OBJ 17 MB 183 MB Visual GLB 4.1 MB 145 MB OBJ 12 MB 141 MB

695. motherboard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.1	6.3	24.5	3 ms	32.0	1.2	3.6	0.4	70.2
Simulation, STEP	2.1	5.8	23.8	1 ms	32.4	16.2	3.6	0.4	84.5
Simulation, STL	2.2	5.9	24.0	2 ms	31.9	2.9	3.6	0.5	71.1
Simulation, OBJ	2.1	6.0	24.6	2 ms	32.7	36.2	4.0	0.5	106.0
Visual, GLB	2.1	6.2	24.4	2 ms	59.9	0.7	7.5	0.4	101.1
Visual, OBJ	2.3	6.2	24.7	2 ms	60.6	21.2	7.5	0.5	122.9

Board Repo: byrantech/laptop Board: motherboard.kicad_pcb Folder motherboard Complexity 417 / 1000 (size 247, features 170) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, curved board outline, TrueType text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241007) Parts, tracks, vias 258, 4,080, 734 Triangles, simulation 6,514,532 in 491 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 222 MB 1.6 GB STEP 900 MB 2.2 GB STL 326 MB 1.7 GB OBJ 698 MB 4.2 GB Visual GLB 132 MB 2.2 GB OBJ 425 MB 2.7 GB

696. power

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.2	2.0	8.4	0.7 ms	11.1	0.3	1.1	0.3	24.3
Simulation, STEP	1.5	2.1	9.0	1.0 ms	10.8	6.0	1.1	0.3	30.7
Simulation, STL	1.1	2.1	9.2	0.6 ms	10.7	0.5	1.0	0.3	24.8
Simulation, OBJ	1.2	1.9	7.5	0.6 ms	10.4	11.2	0.9	0.3	33.5
Visual, GLB	1.4	2.3	7.7	0.8 ms	18.7	0.2	1.7	0.3	32.3
Visual, OBJ	1.1	2.0	8.1	0.6 ms	17.8	7.4	2.0	0.3	38.6

Board Repo: byrantech/laptop Board: power.kicad_pcb Folder power Complexity 394 / 1000 (size 239, features 155) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, TrueType text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 13 File format KiCad 9 (20241007) Parts, tracks, vias 176, 1,129, 167 Triangles, simulation 1,717,024 in 153 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 59 MB 647 MB STEP 289 MB 811 MB STL 86 MB 658 MB OBJ 179 MB 1.2 GB Visual GLB 42 MB 857 MB OBJ 126 MB 959 MB

697. switch

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	15 ms	52 ms	0.1	0.1 ms	0.3	8 ms	29 ms	0.3	0.8
Simulation, STEP	15 ms	46 ms	0.1	0.1 ms	0.4	0.3	35 ms	0.3	1.2
Simulation, STL	19 ms	54 ms	0.2	0.1 ms	0.3	12 ms	27 ms	0.2	0.8
Simulation, OBJ	18 ms	54 ms	0.2	0.1 ms	0.3	0.2	41 ms	0.2	1.1
Visual, GLB	17 ms	48 ms	0.1	0.2 ms	0.5	9 ms	58 ms	0.2	1.0
Visual, OBJ	19 ms	49 ms	0.1	0.1 ms	0.5	0.2	60 ms	0.2	1.2

Board Repo: byrantech/laptop Board: switch.kicad_pcb Folder switch Complexity 151 / 1000 (size 101, features 50) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline, TrueType text Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241007) Parts, tracks, vias 6, 32, 5 Triangles, simulation 39,470 in 15 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 1.4 MB 46 MB STEP 5.5 MB 52 MB STL 2.0 MB 48 MB OBJ 3.7 MB 60 MB Visual GLB 1.0 MB 71 MB OBJ 2.9 MB 78 MB

698. motherboard-stable

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	3.7	27.2	131.4	5 ms	110.6	8.4	20.1	1.0	302.5
Simulation, STEP	3.7	30.1	136.6	4 ms	126.0	71.8	25.0	1.1	394.3
Simulation, STL	4.6	29.6	146.5	5 ms	121.8	17.4	22.6	1.3	343.7
Simulation, OBJ	4.0	28.6	133.5	6 ms	111.6	170.3	24.0	2.2	474.3
Visual, GLB	3.7	30.4	139.3	4 ms	282.3	2.4	30.8	0.7	489.6
Visual, OBJ	4.4	28.4	134.8	0.2	277.4	81.2	32.7	1.0	560.1

Board Repo: c4puter/motherboard Board: motherboard-stable.kicad_pcb Complexity 402 / 1000 (size 327, features 75) KESE features through vias, slotted holes, drill offsets, filled zones, copper text, curved board outline Tested 9th November 2026 to 11th November 2026 Copper layers 6 File format KiCad 4 (4) Parts, tracks, vias 591, 22,267, 2,074 Triangles, simulation 22,500,734 in 1157 parts Verifier PASS in all six runs Run again Simulation, OBJ: failed in the corpus run, run again with no memory cap and no time limit (swap added to a 16 GB machine), and passed

File type File size Peak memory used Simulation GLB 775 MB 4.3 GB STEP 3.1 GB 6.1 GB STL 1.1 GB 4.6 GB OBJ 2.5 GB 14 GB Visual GLB 389 MB 6.3 GB OBJ 1.3 GB 8.1 GB

699. motherboard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	3.5	27.8	135.1	5 ms	111.7	7.1	20.4	0.8	306.4
Simulation, STEP	3.7	27.8	132.8	4 ms	106.6	61.4	19.2	1.0	352.4
Simulation, STL	3.7	27.5	132.6	4 ms	102.8	11.9	17.2	0.9	296.6
Simulation, OBJ	4.3	28.6	135.9	4 ms	104.3	162.5	18.3	1.1	455.0
Visual, GLB	3.7	26.6	131.1	4 ms	266.9	2.9	23.8	0.6	455.7
Visual, OBJ	3.8	27.6	132.1	4 ms	263.7	72.5	23.1	0.6	523.4

Board Repo: c4puter/motherboard Board: motherboard.kicad_pcb Complexity 402 / 1000 (size 327, features 75) KESE features through vias, slotted holes, drill offsets, filled zones, copper text, curved board outline Tested 9th November 2026 to 10th November 2026 Copper layers 6 File format KiCad 5 (20160815) Parts, tracks, vias 591, 22,267, 2,074 Triangles, simulation 22,500,734 in 1157 parts Verifier PASS in all six runs Run again Simulation, OBJ: failed in the corpus run, run again with the memory cap raised from 11 GB to 14.5 GB, and passed

File type File size Peak memory used Simulation GLB 775 MB 4.5 GB STEP 3.1 GB 6.1 GB STL 1.1 GB 4.6 GB OBJ 2.5 GB 14 GB Visual GLB 389 MB 6.3 GB OBJ 1.3 GB 7.9 GB

700. OBC Development Board

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.0	6.4	21.5	4 ms	19.8	1.0	2.6	0.4	52.7
Simulation, STEP	1.0	6.2	20.1	2 ms	19.3	10.1	2.4	0.4	59.4
Simulation, STL	1.4	6.1	21.6	2 ms	19.2	2.3	2.3	0.4	53.4
Simulation, OBJ	1.2	5.7	20.2	3 ms	19.7	28.2	2.8	0.3	78.1
Visual, GLB	1.1	6.6	21.6	1 ms	39.7	0.4	5.8	0.4	75.5
Visual, OBJ	1.1	6.0	20.7	0.9 ms	37.8	13.7	6.1	0.3	85.7

Board Repo: calgarytospace/cts-sat-2-obc-pcb Board: OBC Development Board.kicad_pcb Folder CTS-SAT-1 Hardware Complexity 337 / 1000 (size 237, features 100) KESE features through vias, padstacks, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 221, 1,889, 667 Triangles, simulation 5,120,894 in 206 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 176 MB 1.4 GB STEP 525 MB 1.8 GB STL 256 MB 1.4 GB OBJ 565 MB 3.3 GB Visual GLB 87 MB 1.6 GB OBJ 280 MB 1.9 GB

701. CTS-SAT-2-OBC-PCB

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.4	4.4	16.4	2 ms	16.0	0.8	2.4	0.4	41.7
Simulation, STEP	1.2	4.4	16.6	3 ms	16.3	11.5	2.3	0.4	52.7
Simulation, STL	1.3	4.4	16.8	3 ms	16.6	1.7	2.2	0.3	43.3
Simulation, OBJ	1.3	4.2	16.9	2 ms	16.6	23.4	2.2	0.4	64.9
Visual, GLB	1.3	4.3	16.7	2 ms	38.0	0.5	4.8	0.4	65.9
Visual, OBJ	1.2	4.4	16.6	1 ms	37.9	13.6	4.9	0.4	79.0

Board Repo: calgarytospace/cts-sat-2-obc-pcb Board: CTS-SAT-2-OBC-PCB.kicad_pcb Folder Hardware Complexity 395 / 1000 (size 280, features 115) KESE features through vias, padstacks, slotted holes, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 6 File format KiCad 9 (20241229) Parts, tracks, vias 219, 1,783, 433 Triangles, simulation 4,523,508 in 424 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 149 MB 1.3 GB STEP 573 MB 1.6 GB STL 226 MB 1.3 GB OBJ 475 MB 2.9 GB Visual GLB 93 MB 1.6 GB OBJ 293 MB 2.1 GB

702. MiniLatteLedArray

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.3	5.2	0.7 ms	6.1	0.2	0.8	0.2	14.3
Simulation, STEP	0.5	1.2	5.1	0.6 ms	6.4	4.8	0.8	0.2	18.9
Simulation, STL	0.5	1.2	5.4	0.7 ms	6.7	0.4	0.8	0.2	15.2
Simulation, OBJ	0.5	1.3	5.4	1 ms	6.8	4.7	0.8	0.2	19.7
Visual, GLB	0.5	1.3	5.2	0.8 ms	11.3	0.1	1.2	0.2	20.0
Visual, OBJ	0.5	1.3	5.2	0.8 ms	11.5	4.6	1.7	0.2	24.9

Board Repo: cath272/minilatte Board: MiniLatteLedArray.kicad_pcb Folder MiniLatteLedArray Complexity 294 / 1000 (size 204, features 90) KESE features through vias, arc tracks, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 225, 1,844, 229 Triangles, simulation 1,114,792 in 235 parts Note panel Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 39 MB 626 MB STEP 201 MB 665 MB STL 56 MB 631 MB OBJ 117 MB 760 MB Visual GLB 37 MB 933 MB OBJ 110 MB 806 MB

703. MiniLatte

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	5.5	10.3	40.3	2 ms	71.5	2.5	7.7	0.5	138.3
Simulation, STEP	5.5	10.6	42.1	2 ms	74.8	38.8	7.4	0.6	179.8
Simulation, STL	5.9	10.5	42.3	2 ms	76.6	5.2	8.0	0.5	149.0
Simulation, OBJ	5.6	11.0	42.0	2 ms	80.8	85.1	8.3	0.6	233.4
Visual, GLB	6.2	11.5	46.0	2 ms	132.9	2.6	13.5	0.5	213.3
Visual, OBJ	5.7	10.2	40.8	2 ms	135.9	49.2	14.7	0.5	257.0

Board Repo: cath272/minilatte Board: MiniLatte.kicad_pcb Folder PCB Complexity 450 / 1000 (size 315, features 135) KESE features through vias, slotted holes, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 10 (20260206) Parts, tracks, vias 495, 11,156, 736 Triangles, simulation 8,966,200 in 848 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 306 MB 2.9 GB STEP 1.5 GB 3.5 GB STL 448 MB 2.8 GB OBJ 971 MB 5.8 GB Visual GLB 232 MB 3.6 GB OBJ 752 MB 4.7 GB

704. hdmi-edp2

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	1.1	3.6	0.5 ms	4.1	0.2	0.6	0.2	10.1
Simulation, STEP	0.4	1.1	3.5	0.3 ms	4.1	3.3	0.6	0.2	13.2
Simulation, STL	0.4	1.1	3.5	0.5 ms	4.2	0.3	0.6	0.2	10.2
Simulation, OBJ	0.4	1.2	3.7	0.4 ms	4.5	5.9	0.6	0.2	16.5
Visual, GLB	0.4	1.0	3.5	0.4 ms	9.0	0.1	1.0	0.2	15.4
Visual, OBJ	0.4	1.2	3.8	0.6 ms	8.3	4.4	1.4	0.2	19.7

Board Repo: cetola/reform-next-mirror Board: hdmi-edp2.kicad_pcb Folder hdmi-edp2 Complexity 329 / 1000 (size 254, features 75) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 93, 910, 170 Triangles, simulation 1,071,490 in 92 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 37 MB 460 MB STEP 156 MB 547 MB STL 54 MB 452 MB OBJ 108 MB 740 MB Visual GLB 27 MB 635 MB OBJ 81 MB 626 MB

705. nref-batterypack-backside

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.1	0.4	0.1 ms	0.5	16 ms	48 ms	0.3	1.5
Simulation, STEP	0.2	0.1	0.4	0.1 ms	0.5	0.8	48 ms	0.3	2.4
Simulation, STL	0.2	0.1	0.4	0.1 ms	0.5	31 ms	49 ms	0.2	1.5
Simulation, OBJ	0.1	0.1	0.4	0.1 ms	0.5	0.5	48 ms	0.2	1.9
Visual, GLB	0.1	0.1	0.4	0.1 ms	1.2	13 ms	79 ms	0.3	2.1
Visual, OBJ	0.1	0.1	0.4	0.2 ms	1.1	0.4	0.1	0.2	2.4

Board Repo: cetola/reform-next-mirror Board: nref-batterypack-backside.kicad_pcb Folder nref-batterypack-v3 Complexity 229 / 1000 (size 114, features 115) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 10 (20260206) Parts, tracks, vias 3, 16, 13 Triangles, simulation 82,176 in 16 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 2.9 MB 183 MB STEP 13 MB 185 MB STL 4.1 MB 178 MB OBJ 8.0 MB 176 MB Visual GLB 2.3 MB 151 MB OBJ 6.3 MB 153 MB

706. nref-batterypack

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.0	3.0	0.4 ms	3.6	0.2	0.6	0.2	9.0
Simulation, STEP	0.5	1.0	3.1	0.3 ms	3.3	2.8	0.5	0.3	11.6
Simulation, STL	0.4	1.0	3.2	0.2 ms	3.8	0.3	0.6	0.3	9.5
Simulation, OBJ	0.4	1.0	3.1	0.5 ms	3.5	4.8	0.5	0.3	13.6
Visual, GLB	0.4	1.0	3.1	0.3 ms	7.7	0.1	0.9	0.2	13.4
Visual, OBJ	0.4	1.0	3.2	0.4 ms	8.0	3.6	1.1	0.2	17.6

Board Repo: cetola/reform-next-mirror Board: nref-batterypack.kicad_pcb Folder nref-batterypack-v3 Complexity 355 / 1000 (size 240, features 115) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 10 (20260206) Parts, tracks, vias 85, 776, 191 Triangles, simulation 978,200 in 77 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 33 MB 421 MB STEP 142 MB 545 MB STL 49 MB 418 MB OBJ 98 MB 700 MB Visual GLB 24 MB 617 MB OBJ 72 MB 599 MB

707. nref-batterypack-backside

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	99 ms	0.2	0.1 ms	0.3	7 ms	23 ms	0.2	1.0
Simulation, STEP	0.1	90 ms	0.2	0.1 ms	0.3	0.3	20 ms	0.3	1.2
Simulation, STL	0.1	0.1	0.2	0.1 ms	0.3	11 ms	25 ms	0.2	1.0
Simulation, OBJ	0.1	0.1	0.2	0.1 ms	0.3	0.2	21 ms	0.2	1.2
Visual, GLB	0.1	90 ms	0.2	0.1 ms	0.6	8 ms	49 ms	0.2	1.2
Visual, OBJ	0.2	0.1	0.2	0.1 ms	0.6	0.3	48 ms	0.2	1.6

Board Repo: cetola/reform-next-mirror Board: nref-batterypack-backside.kicad_pcb Folder nref-batterypack Complexity 122 / 1000 (size 72, features 50) KESE features through vias, rounded, trapezoid or chamfered pads, curved board outline, knockout text Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 1, 12, 2 Triangles, simulation 31,336 in 12 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 1.2 MB 72 MB STEP 7.0 MB 77 MB STL 1.6 MB 72 MB OBJ 3.2 MB 79 MB Visual GLB 1.1 MB 88 MB OBJ 3.1 MB 101 MB

708. nref-batterypack

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.7	2.3	0.4 ms	2.7	98 ms	0.3	0.3	6.7
Simulation, STEP	0.3	0.7	2.2	0.4 ms	2.6	2.3	0.4	0.2	8.7
Simulation, STL	0.3	0.7	2.2	0.3 ms	2.7	0.2	0.4	0.3	6.7
Simulation, OBJ	0.3	0.6	2.1	0.3 ms	2.6	3.3	0.4	0.2	9.6
Visual, GLB	0.4	0.7	2.2	0.3 ms	5.6	71 ms	0.5	0.3	9.6
Visual, OBJ	0.3	0.7	2.3	0.4 ms	5.1	2.6	0.6	0.2	11.7

Board Repo: cetola/reform-next-mirror Board: nref-batterypack.kicad_pcb Folder nref-batterypack Complexity 334 / 1000 (size 224, features 110) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 59, 456, 67 Triangles, simulation 555,620 in 64 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 19 MB 321 MB STEP 88 MB 389 MB STL 28 MB 320 MB OBJ 56 MB 422 MB Visual GLB 14 MB 425 MB OBJ 43 MB 368 MB

709. nref-camera-adapter

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.4	1.0	0.2 ms	1.1	51 ms	0.2	0.2	3.2
Simulation, STEP	0.2	0.4	0.9	0.2 ms	1.2	1.2	0.2	0.2	4.3
Simulation, STL	0.2	0.4	1.0	0.2 ms	1.2	0.1	0.2	0.2	3.4
Simulation, OBJ	0.2	0.4	1.0	0.2 ms	1.2	1.9	0.2	0.3	5.0
Visual, GLB	0.2	0.4	1.0	0.3 ms	2.3	44 ms	0.3	0.2	4.4
Visual, OBJ	0.2	0.4	1.0	0.2 ms	2.4	1.1	0.2	0.3	5.5

Board Repo: cetola/reform-next-mirror Board: nref-camera-adapter.kicad_pcb Folder nref-camera-adapter Complexity 236 / 1000 (size 146, features 90) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 2, 157, 101 Triangles, simulation 308,202 in 36 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 11 MB 273 MB STEP 31 MB 278 MB STL 15 MB 269 MB OBJ 30 MB 260 MB Visual GLB 7.0 MB 233 MB OBJ 21 MB 237 MB

710. reform-camera

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	2.0	7.9	0.5 ms	8.1	0.3	0.8	0.4	20.1
Simulation, STEP	0.6	1.6	7.4	0.4 ms	8.0	5.6	0.8	0.3	24.3
Simulation, STL	0.6	1.7	7.5	0.4 ms	8.3	0.4	0.8	0.3	19.6
Simulation, OBJ	0.6	1.6	7.4	0.6 ms	8.0	9.8	0.9	0.3	28.6
Visual, GLB	0.6	1.7	7.4	0.4 ms	14.7	0.2	1.6	0.3	26.4
Visual, OBJ	0.6	1.7	7.8	0.4 ms	15.2	7.3	1.6	0.3	34.4

Board Repo: cetola/reform-next-mirror Board: reform-camera.kicad_pcb Folder nref-camera Complexity 356 / 1000 (size 261, features 95) KESE features through vias, rounded, trapezoid or chamfered pads, arc tracks, filled zones, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 8 (20240108) Parts, tracks, vias 114, 1,298, 235 Triangles, simulation 1,605,780 in 148 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 54 MB 613 MB STEP 253 MB 747 MB STL 80 MB 622 MB OBJ 165 MB 1.1 GB Visual GLB 39 MB 755 MB OBJ 119 MB 902 MB

711. nref-flex-eth

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.7	0.2 ms	0.7	27 ms	95 ms	0.2	2.0
Simulation, STEP	0.1	0.2	0.7	0.3 ms	0.7	0.9	94 ms	0.2	2.9
Simulation, STL	0.1	0.2	0.6	0.1 ms	0.7	34 ms	84 ms	0.3	2.0
Simulation, OBJ	98 ms	0.2	0.6	0.2 ms	0.7	0.7	80 ms	0.2	2.6
Visual, GLB	94 ms	0.2	0.8	0.2 ms	1.6	24 ms	0.2	0.2	3.0
Visual, OBJ	94 ms	0.2	0.6	0.2 ms	1.7	0.7	0.2	0.2	3.7

Board Repo: cetola/reform-next-mirror Board: nref-flex-eth.kicad_pcb Folder nref-flex / nref-flex-eth Complexity 176 / 1000 (size 126, features 50) KESE features through vias, filled zones, TrueType text Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 2, 88, 98 Triangles, simulation 147,362 in 22 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 5.2 MB 212 MB STEP 18 MB 223 MB STL 7.4 MB 211 MB OBJ 15 MB 217 MB Visual GLB 5.4 MB 205 MB OBJ 15 MB 203 MB

712. nref-flex-dp-140mm

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.6	0.1 ms	0.7	20 ms	69 ms	0.2	1.9
Simulation, STEP	0.1	0.1	0.5	0.1 ms	0.8	0.9	51 ms	0.2	2.7
Simulation, STL	0.1	0.1	0.5	0.1 ms	0.7	25 ms	67 ms	0.2	1.8
Simulation, OBJ	0.1	0.1	0.6	0.1 ms	0.8	0.5	51 ms	0.2	2.4
Visual, GLB	0.1	0.1	0.5	0.1 ms	1.3	19 ms	0.1	0.2	2.4
Visual, OBJ	0.1	0.1	0.5	0.1 ms	1.3	0.6	0.1	0.2	2.9

Board Repo: cetola/reform-next-mirror Board: nref-flex-dp-140mm.kicad_pcb Folder nref-flex / nref-flex-hdmi Complexity 165 / 1000 (size 115, features 50) KESE features through vias, filled zones, TrueType text Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 2, 75, 40 Triangles, simulation 89,198 in 23 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 3.3 MB 185 MB STEP 16 MB 203 MB STL 4.5 MB 190 MB OBJ 9.1 MB 187 MB Visual GLB 4.0 MB 174 MB OBJ 11 MB 171 MB

713. nref-flex-hdmi

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.1	0.5	0.1 ms	0.7	18 ms	59 ms	0.2	1.7
Simulation, STEP	0.1	0.2	0.5	0.1 ms	0.7	0.9	53 ms	0.2	2.6
Simulation, STL	0.1	0.1	0.5	0.1 ms	0.7	24 ms	57 ms	0.2	1.7
Simulation, OBJ	0.1	0.1	0.5	0.1 ms	0.7	0.5	57 ms	0.2	2.2
Visual, GLB	0.1	0.1	0.4	0.1 ms	1.3	19 ms	0.1	0.2	2.3
Visual, OBJ	0.1	0.1	0.4	0.1 ms	1.3	0.6	0.1	0.2	2.8

Board Repo: cetola/reform-next-mirror Board: nref-flex-hdmi.kicad_pcb Folder nref-flex / nref-flex-hdmi Complexity 166 / 1000 (size 116, features 50) KESE features through vias, filled zones, TrueType text Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 2, 76, 44 Triangles, simulation 91,684 in 23 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 3.4 MB 189 MB STEP 16 MB 195 MB STL 4.6 MB 193 MB OBJ 9.3 MB 194 MB Visual GLB 4.1 MB 166 MB OBJ 11 MB 167 MB

714. nref-flex-pcie

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.4	0.2 ms	0.6	26 ms	66 ms	0.3	1.7
Simulation, STEP	0.1	0.1	0.5	0.2 ms	0.7	0.8	68 ms	0.2	2.5
Simulation, STL	0.1	0.2	0.4	0.1 ms	0.7	25 ms	64 ms	0.2	1.7
Simulation, OBJ	0.1	0.1	0.4	0.2 ms	0.6	0.6	88 ms	0.3	2.2
Visual, GLB	0.1	0.1	0.4	0.2 ms	1.4	20 ms	0.1	0.2	2.5
Visual, OBJ	0.1	0.1	0.4	0.2 ms	1.4	0.6	0.1	0.3	3.1

Board Repo: cetola/reform-next-mirror Board: nref-flex-pcie.kicad_pcb Folder nref-flex / nref-flex-pcie Complexity 195 / 1000 (size 115, features 80) KESE features through vias, filled zones, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 2, 95, 32 Triangles, simulation 97,104 in 24 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 3.4 MB 181 MB STEP 16 MB 195 MB STL 4.9 MB 185 MB OBJ 9.6 MB 190 MB Visual GLB 3.5 MB 158 MB OBJ 9.9 MB 166 MB

715. nref-flex-sdcard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	97 ms	0.1	0.3	0.1 ms	0.6	15 ms	65 ms	0.2	1.4
Simulation, STEP	0.1	0.1	0.4	0.1 ms	0.6	0.7	50 ms	0.2	2.1
Simulation, STL	88 ms	0.1	0.3	0.1 ms	0.5	22 ms	52 ms	0.2	1.3
Simulation, OBJ	85 ms	0.1	0.3	0.1 ms	0.5	0.4	51 ms	0.2	1.7
Visual, GLB	95 ms	0.1	0.4	0.1 ms	1.4	20 ms	0.1	0.2	2.3
Visual, OBJ	0.1	0.1	0.3	0.1 ms	1.3	0.4	0.1	0.2	2.6

Board Repo: cetola/reform-next-mirror Board: nref-flex-sdcard.kicad_pcb Folder nref-flex / nref-flex-sdcard Complexity 163 / 1000 (size 113, features 50) KESE features through vias, filled zones, TrueType text Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 2, 32, 48 Triangles, simulation 93,212 in 19 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 3.4 MB 182 MB STEP 15 MB 199 MB STL 4.7 MB 184 MB OBJ 9.2 MB 184 MB Visual GLB 4.0 MB 168 MB OBJ 11 MB 158 MB

716. nref-flex-sound

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.1	0.5	0.1 ms	0.7	23 ms	70 ms	0.2	1.8
Simulation, STEP	0.1	0.1	0.5	0.2 ms	0.7	0.9	60 ms	0.2	2.6
Simulation, STL	0.1	0.1	0.4	0.1 ms	0.6	36 ms	67 ms	0.2	1.6
Simulation, OBJ	0.1	0.1	0.4	0.1 ms	0.8	0.6	97 ms	0.2	2.4
Visual, GLB	0.1	0.2	0.4	0.1 ms	1.3	20 ms	0.1	0.2	2.4
Visual, OBJ	0.1	0.1	0.4	0.1 ms	1.4	0.7	0.1	0.3	3.0

Board Repo: cetola/reform-next-mirror Board: nref-flex-sound.kicad_pcb Folder nref-flex / nref-flex-sound Complexity 162 / 1000 (size 112, features 50) KESE features through vias, filled zones, TrueType text Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 2, 29, 44 Triangles, simulation 89,318 in 19 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 3.2 MB 185 MB STEP 15 MB 197 MB STL 4.5 MB 179 MB OBJ 8.9 MB 184 MB Visual GLB 3.8 MB 163 MB OBJ 11 MB 163 MB

717. nref-flex-usb3-camera

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.5	0.5 ms	0.6	22 ms	63 ms	0.3	1.7
Simulation, STEP	98 ms	0.2	0.4	0.4 ms	0.6	0.8	60 ms	0.2	2.3
Simulation, STL	0.1	0.1	0.4	0.1 ms	0.6	31 ms	60 ms	0.3	1.6
Simulation, OBJ	0.1	0.2	0.4	0.1 ms	0.6	0.6	65 ms	0.2	2.1
Visual, GLB	0.1	0.1	0.4	0.1 ms	1.3	19 ms	0.1	0.2	2.2
Visual, OBJ	0.1	0.1	0.7	0.2 ms	1.4	0.7	98 ms	0.2	3.4

Board Repo: cetola/reform-next-mirror Board: nref-flex-usb3-camera.kicad_pcb Folder nref-flex / nref-flex-usb3-one Complexity 199 / 1000 (size 119, features 80) KESE features through vias, filled zones, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 2, 66, 60 Triangles, simulation 97,574 in 19 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 3.4 MB 186 MB STEP 13 MB 195 MB STL 4.9 MB 190 MB OBJ 9.5 MB 188 MB Visual GLB 3.6 MB 157 MB OBJ 10.0 MB 156 MB

718. nref-flex-usb3-one-130mm

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	88 ms	0.3	0.1 ms	0.6	15 ms	45 ms	0.2	1.3
Simulation, STEP	0.1	0.1	0.4	0.3 ms	0.6	0.7	43 ms	0.2	2.1
Simulation, STL	0.1	98 ms	0.3	0.2 ms	0.6	20 ms	49 ms	0.2	1.4
Simulation, OBJ	0.1	98 ms	0.3	0.1 ms	0.6	0.5	50 ms	0.2	1.8
Visual, GLB	98 ms	88 ms	0.3	0.1 ms	1.2	23 ms	0.1	0.2	2.0
Visual, OBJ	0.1	94 ms	0.3	0.1 ms	1.2	0.4	87 ms	0.2	2.4

Board Repo: cetola/reform-next-mirror Board: nref-flex-usb3-one-130mm.kicad_pcb Folder nref-flex / nref-flex-usb3-one Complexity 189 / 1000 (size 109, features 80) KESE features through vias, filled zones, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 2, 62, 25 Triangles, simulation 74,446 in 17 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 2.7 MB 177 MB STEP 14 MB 189 MB STL 3.7 MB 179 MB OBJ 7.4 MB 179 MB Visual GLB 3.2 MB 155 MB OBJ 8.8 MB 154 MB

719. nref-flex-usb3-one

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.7	0.1 ms	0.7	25 ms	73 ms	0.3	2.1
Simulation, STEP	0.1	0.2	0.6	0.1 ms	0.7	0.9	77 ms	0.2	2.9
Simulation, STL	0.1	0.2	0.6	0.2 ms	0.7	39 ms	85 ms	0.2	2.0
Simulation, OBJ	0.1	0.2	0.6	0.1 ms	0.7	0.7	81 ms	0.2	2.6
Visual, GLB	0.1	0.2	0.6	0.2 ms	1.5	26 ms	0.1	0.2	2.8
Visual, OBJ	0.1	0.2	0.6	0.2 ms	1.5	0.8	0.1	0.3	3.7

Board Repo: cetola/reform-next-mirror Board: nref-flex-usb3-one.kicad_pcb Folder nref-flex / nref-flex-usb3-one Complexity 203 / 1000 (size 123, features 80) KESE features through vias, filled zones, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 2, 66, 81 Triangles, simulation 127,254 in 19 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 4.5 MB 197 MB STEP 17 MB 215 MB STL 6.4 MB 191 MB OBJ 13 MB 198 MB Visual GLB 4.9 MB 190 MB OBJ 14 MB 182 MB

720. nref-motherboard

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.7	7.3	20.6	0.9 ms	22.1	1.0	3.4	0.4	56.3
Simulation, STEP	1.7	6.6	19.9	1.0 ms	21.6	13.9	3.3	0.3	67.3
Simulation, STL	1.8	6.5	20.0	1.0 ms	21.3	2.3	3.3	0.3	55.5
Simulation, OBJ	1.7	7.0	20.3	1.0 ms	22.3	36.7	3.1	0.3	91.4
Visual, GLB	1.6	6.7	19.6	1 ms	53.6	0.6	6.6	0.3	88.9
Visual, OBJ	1.7	6.7	20.2	1 ms	52.6	21.1	7.0	0.3	109.6

Board Repo: cetola/reform-next-mirror Board: nref-motherboard.kicad_pcb Folder nref-motherboard Complexity 452 / 1000 (size 302, features 150) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, knockout text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 6 File format KiCad 10 (20260206) Parts, tracks, vias 267, 4,810, 1,094 Triangles, simulation 6,534,402 in 430 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 219 MB 1.9 GB STEP 770 MB 2.4 GB STL 327 MB 1.8 GB OBJ 691 MB 4.1 GB Visual GLB 129 MB 2.2 GB OBJ 418 MB 2.7 GB

721. nref-ports-one

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	2.4	8.2	1.0 ms	10.3	0.5	1.1	0.3	23.5
Simulation, STEP	0.7	2.5	8.3	0.9 ms	10.3	6.7	1.2	0.3	30.0
Simulation, STL	0.7	2.7	8.8	0.9 ms	10.6	0.8	1.1	0.3	25.2
Simulation, OBJ	0.6	2.5	8.4	0.9 ms	10.0	11.8	1.2	0.3	34.8
Visual, GLB	0.7	2.5	8.3	0.8 ms	20.1	0.3	2.4	0.2	34.6
Visual, OBJ	0.8	2.6	8.7	1 ms	21.0	8.6	3.0	0.3	45.1

Board Repo: cetola/reform-next-mirror Board: nref-ports-one.kicad_pcb Folder nref-ports-one Complexity 376 / 1000 (size 261, features 115) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 146, 2,113, 461 Triangles, simulation 2,380,888 in 187 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 81 MB 821 MB STEP 339 MB 1.0 GB STL 119 MB 815 MB OBJ 248 MB 1.6 GB Visual GLB 56 MB 1.0 GB OBJ 174 MB 1.2 GB

722. nref-ports-two

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	2.4	10.0	1 ms	11.1	0.4	1.1	0.3	26.2
Simulation, STEP	0.7	2.4	10.2	1.0 ms	10.9	7.1	1.1	0.3	32.9
Simulation, STL	0.7	2.3	9.8	1 ms	11.2	0.9	1.2	0.3	26.4
Simulation, OBJ	0.7	2.5	9.9	1 ms	11.2	12.6	1.2	0.3	38.4
Visual, GLB	0.7	2.5	10.4	1 ms	23.4	0.3	2.7	0.3	40.3
Visual, OBJ	0.7	2.4	10.2	1 ms	22.2	8.9	3.0	0.3	47.7

Board Repo: cetola/reform-next-mirror Board: nref-ports-two.kicad_pcb Folder nref-ports-two Complexity 381 / 1000 (size 266, features 115) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 10 (20260206) Parts, tracks, vias 137, 1,989, 422 Triangles, simulation 2,497,724 in 191 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 86 MB 825 MB STEP 366 MB 1.1 GB STL 125 MB 853 MB OBJ 262 MB 1.6 GB Visual GLB 57 MB 1.1 GB OBJ 175 MB 1.3 GB

723. Trackpad_IQS9150

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.9	5.2	0.3 ms	8.6	0.3	1.0	0.3	17.7
Simulation, STEP	0.4	1.8	5.0	0.4 ms	8.9	6.6	0.9	0.3	24.0
Simulation, STL	0.5	1.7	5.1	0.2 ms	8.8	0.5	0.8	0.3	17.7
Simulation, OBJ	0.5	1.7	5.3	0.3 ms	9.5	8.4	0.9	0.3	26.6
Visual, GLB	0.4	1.9	5.2	0.4 ms	14.4	0.2	1.6	0.3	24.0
Visual, OBJ	0.5	1.9	5.0	0.2 ms	13.9	8.1	1.6	0.3	31.3

Board Repo: cetola/reform-next-mirror Board: Trackpad_IQS9150.kicad_pcb Folder nref-trackpad-sensor Complexity 259 / 1000 (size 174, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 10 (20260206) Parts, tracks, vias 10, 1,065, 633 Triangles, simulation 1,517,980 in 63 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 52 MB 712 MB STEP 213 MB 789 MB STL 76 MB 702 MB OBJ 156 MB 1.0 GB Visual GLB 46 MB 1.0 GB OBJ 141 MB 1.0 GB

724. nref-trackpad

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.2	0.7	0.2 ms	1.3	39 ms	0.1	0.3	2.9
Simulation, STEP	0.2	0.2	0.8	0.3 ms	1.4	1.4	0.1	0.3	4.4
Simulation, STL	0.2	0.2	0.8	0.2 ms	1.3	59 ms	0.1	0.3	2.9
Simulation, OBJ	0.2	0.2	0.9	0.2 ms	1.4	1.1	0.1	0.3	4.3
Visual, GLB	0.2	0.2	0.7	0.2 ms	2.1	30 ms	0.2	0.3	3.6
Visual, OBJ	0.2	0.2	0.7	0.2 ms	2.4	1.0	0.2	0.3	4.9

Board Repo: cetola/reform-next-mirror Board: nref-trackpad.kicad_pcb Folder nref-trackpad Complexity 243 / 1000 (size 168, features 75) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 12, 93, 22 Triangles, simulation 162,486 in 36 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 5.6 MB 209 MB STEP 27 MB 230 MB STL 8.1 MB 210 MB OBJ 16 MB 212 MB Visual GLB 4.8 MB 210 MB OBJ 14 MB 209 MB

725. nref-usb3-redriver

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.7	2.0	0.5 ms	2.6	0.1	0.4	0.2	6.2
Simulation, STEP	0.3	0.7	2.0	0.3 ms	2.5	2.2	0.4	0.2	8.3
Simulation, STL	0.2	0.8	2.2	0.3 ms	2.6	0.2	0.4	0.3	6.6
Simulation, OBJ	0.3	0.7	2.0	0.4 ms	2.8	3.6	0.4	0.3	10.1
Visual, GLB	0.2	0.8	2.0	0.4 ms	4.8	0.1	0.7	0.3	8.9
Visual, OBJ	0.3	0.7	1.9	0.3 ms	4.4	2.4	0.5	0.2	10.3

Board Repo: cetola/reform-next-mirror Board: nref-usb3-redriver.kicad_pcb Folder nref-usb3-redriver Complexity 287 / 1000 (size 187, features 100) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 40, 496, 171 Triangles, simulation 669,168 in 65 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 23 MB 378 MB STEP 84 MB 442 MB STL 33 MB 380 MB OBJ 67 MB 489 MB Visual GLB 16 MB 381 MB OBJ 47 MB 431 MB

726. nref-wifi-m2

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	0.7	1.8	0.3 ms	2.5	0.1	0.4	0.3	6.2
Simulation, STEP	0.3	0.6	1.9	0.4 ms	2.4	2.2	0.4	0.3	8.0
Simulation, STL	0.3	0.7	1.9	0.4 ms	2.5	0.2	0.4	0.2	6.1
Simulation, OBJ	0.3	0.7	1.8	0.3 ms	2.5	3.6	0.3	0.3	9.5
Visual, GLB	0.3	0.7	1.8	0.9 ms	5.0	67 ms	0.4	0.3	8.6
Visual, OBJ	0.3	0.7	1.8	0.4 ms	4.9	2.7	0.8	0.3	11.3

Board Repo: cetola/reform-next-mirror Board: nref-wifi-m2.kicad_pcb Folder nref-wifi-m2 Complexity 280 / 1000 (size 180, features 100) KESE features through vias, custom pads, rounded, trapezoid or chamfered pads, filled zones, copper drawings, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 28, 402, 141 Triangles, simulation 588,790 in 76 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 20 MB 332 MB STEP 80 MB 393 MB STL 29 MB 320 MB OBJ 59 MB 448 MB Visual GLB 14 MB 382 MB OBJ 43 MB 410 MB

727. nref-wifi

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.4	1.5	0.2 ms	1.5	59 ms	0.2	0.2	4.0
Simulation, STEP	0.2	0.4	1.6	0.2 ms	1.5	1.5	0.2	0.2	5.5
Simulation, STL	0.2	0.4	1.5	0.3 ms	1.6	79 ms	0.2	0.2	4.1
Simulation, OBJ	0.2	0.4	1.5	0.3 ms	1.5	1.7	0.2	0.2	5.7
Visual, GLB	0.2	0.4	1.5	0.2 ms	2.9	50 ms	0.2	0.2	5.4
Visual, OBJ	0.2	0.4	1.6	0.2 ms	2.8	1.5	0.3	0.2	6.9

Board Repo: cetola/reform-next-mirror Board: nref-wifi.kicad_pcb Folder nref-wifi Complexity 232 / 1000 (size 157, features 75) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 8 (20240108) Parts, tracks, vias 23, 351, 98 Triangles, simulation 336,550 in 54 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 12 MB 272 MB STEP 56 MB 312 MB STL 17 MB 275 MB OBJ 34 MB 274 MB Visual GLB 10 MB 297 MB OBJ 30 MB 300 MB

728. cm0

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	2.0	6.1	26.1	2 ms	32.7	1.0	2.9	0.4	71.0
Simulation, STEP	1.6	4.8	22.9	2 ms	31.7	15.2	2.9	0.4	79.4
Simulation, STL	2.0	5.6	23.1	3 ms	34.7	2.9	3.6	0.4	72.2
Simulation, OBJ	1.9	5.5	24.1	3 ms	33.4	31.9	3.2	0.6	100.6
Visual, GLB	2.0	5.6	25.4	3 ms	72.5	0.8	8.2	0.3	114.9
Visual, OBJ	2.5	6.1	28.2	2 ms	70.8	23.0	8.2	0.4	139.1

Board Repo: cheyao/icepi-sbc Board: cm0.kicad_pcb Folder hardware Complexity 438 / 1000 (size 303, features 135) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, copper drawings, curved board outline, TrueType text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 269, 5,249, 823 Triangles, simulation 4,795,238 in 480 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 161 MB 1.4 GB STEP 691 MB 1.9 GB STL 240 MB 1.4 GB OBJ 511 MB 3.1 GB Visual GLB 109 MB 2.1 GB OBJ 356 MB 2.3 GB

729. icepi-zero

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	2.0	9.1	1 ms	8.7	0.4	1.0	0.3	22.1
Simulation, STEP	0.7	2.0	9.2	1 ms	8.5	6.1	1.1	0.3	27.7
Simulation, STL	0.6	1.9	8.8	1.0 ms	8.5	0.7	1.1	0.3	22.0
Simulation, OBJ	0.6	2.0	8.8	1.0 ms	8.6	11.0	1.1	0.3	32.4
Visual, GLB	0.6	1.9	8.8	0.9 ms	20.0	0.2	2.0	0.3	33.8
Visual, OBJ	0.6	2.1	9.6	2 ms	20.5	6.7	2.1	0.4	42.0

Board Repo: cheyao/icepi-zero Board: icepi-zero.kicad_pcb Folder hardware / v1.0 Complexity 397 / 1000 (size 267, features 130) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, TrueType text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 119, 2,041, 256 Triangles, simulation 2,163,986 in 265 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 75 MB 754 MB STEP 328 MB 932 MB STL 108 MB 745 MB OBJ 227 MB 1.4 GB Visual GLB 47 MB 1.1 GB OBJ 144 MB 1.1 GB

730. icepi-zero

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	1.9	9.0	0.7 ms	8.5	0.4	1.1	0.3	21.9
Simulation, STEP	0.7	2.0	8.5	0.6 ms	8.1	5.9	1.0	0.2	26.5
Simulation, STL	0.5	1.9	8.5	0.6 ms	8.3	0.6	1.0	0.3	21.1
Simulation, OBJ	0.5	1.9	8.5	0.6 ms	8.2	10.6	1.0	0.2	31.0
Visual, GLB	0.6	1.9	8.6	0.8 ms	19.3	0.2	1.7	0.3	32.6
Visual, OBJ	0.6	2.0	8.4	0.6 ms	19.0	6.6	1.8	0.2	38.6

Board Repo: cheyao/icepi-zero Board: icepi-zero.kicad_pcb Folder hardware / v1.1 Complexity 397 / 1000 (size 267, features 130) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, TrueType text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 124, 1,947, 269 Triangles, simulation 2,216,300 in 265 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 76 MB 777 MB STEP 334 MB 955 MB STL 111 MB 787 MB OBJ 236 MB 1.5 GB Visual GLB 48 MB 902 MB OBJ 149 MB 1.1 GB

731. icepi-zero

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.7	7.8	0.8 ms	8.1	0.3	0.9	0.2	19.6
Simulation, STEP	0.5	1.6	7.6	0.8 ms	7.6	5.2	0.9	0.3	23.9
Simulation, STL	0.6	1.8	8.0	1.0 ms	7.8	0.7	1.0	0.3	19.9
Simulation, OBJ	0.6	1.7	8.0	0.8 ms	8.1	10.0	1.0	0.3	29.7
Visual, GLB	0.5	1.7	7.7	1 ms	17.6	0.2	2.0	0.2	30.1
Visual, OBJ	0.5	1.6	7.5	0.8 ms	18.1	6.3	2.3	0.2	36.6

Board Repo: cheyao/icepi-zero Board: icepi-zero.kicad_pcb Folder hardware / v1.2 Complexity 399 / 1000 (size 269, features 130) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, TrueType text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 9 (20241229) Parts, tracks, vias 140, 2,064, 271 Triangles, simulation 2,281,968 in 274 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 79 MB 797 MB STEP 349 MB 991 MB STL 114 MB 794 MB OBJ 244 MB 1.6 GB Visual GLB 49 MB 905 MB OBJ 154 MB 1.1 GB

732. icepi-zero

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	2.1	9.3	2 ms	9.7	0.5	1.2	0.3	23.9
Simulation, STEP	0.8	2.2	9.4	0.8 ms	9.6	6.9	1.1	0.3	30.3
Simulation, STL	0.8	2.2	9.6	0.8 ms	9.5	0.9	1.2	0.3	24.6
Simulation, OBJ	1.0	2.3	10.1	0.9 ms	9.5	13.4	1.3	0.3	37.8
Visual, GLB	1.0	2.2	9.6	0.9 ms	21.0	0.2	2.3	0.3	36.5
Visual, OBJ	0.8	2.1	9.8	0.8 ms	21.0	8.5	2.4	0.2	44.7

Board Repo: cheyao/icepi-zero Board: icepi-zero.kicad_pcb Folder hardware / v1.3 Complexity 401 / 1000 (size 271, features 130) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, TrueType text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 10 (20260206) Parts, tracks, vias 143, 2,234, 272 Triangles, simulation 2,347,416 in 277 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 81 MB 773 MB STEP 369 MB 992 MB STL 117 MB 890 MB OBJ 250 MB 1.6 GB Visual GLB 51 MB 1.1 GB OBJ 160 MB 1.1 GB

733. icepi-zero

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	1.8	9.3	1 ms	9.2	0.4	1.3	0.3	23.0
Simulation, STEP	0.7	1.9	9.3	1 ms	9.3	6.4	1.2	0.3	29.1
Simulation, STL	0.7	2.1	9.2	1.0 ms	9.2	0.7	1.1	0.3	23.3
Simulation, OBJ	0.7	2.2	9.2	1 ms	9.3	11.7	1.2	0.3	34.7
Visual, GLB	0.7	2.1	9.5	1 ms	21.4	0.3	2.1	0.2	36.3
Visual, OBJ	0.7	2.2	9.4	1.0 ms	21.8	7.6	2.3	0.3	44.3

Board Repo: cheyao/icepi-zero Board: icepi-zero.kicad_pcb Folder hardware / v1.4 Complexity 416 / 1000 (size 271, features 145) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, arc tracks, filled zones, curved board outline, TrueType text, stack-up, dielectric εr and tanδ, copper finish, mask and silkscreen colours Tested 9th November 2026 Copper layers 4 File format KiCad 10 (20260206) Parts, tracks, vias 144, 2,286, 277 Triangles, simulation 2,359,720 in 277 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 81 MB 818 MB STEP 373 MB 1.0 GB STL 118 MB 925 MB OBJ 252 MB 1.6 GB Visual GLB 51 MB 1.0 GB OBJ 161 MB 1.1 GB

734. breakout-tt04-qfn-openframe

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	1.2	3.7	0.6 ms	2.8	0.1	0.5	0.2	9.1
Simulation, STEP	0.6	1.1	3.6	0.5 ms	2.7	2.3	0.5	0.3	11.1
Simulation, STL	0.7	1.2	3.5	0.4 ms	2.7	0.2	0.4	0.3	9.0
Simulation, OBJ	0.6	1.1	3.5	0.5 ms	2.8	4.2	0.5	0.2	13.0
Visual, GLB	0.7	1.1	3.4	0.3 ms	6.8	0.1	0.7	0.3	13.1
Visual, OBJ	0.7	1.1	3.4	0.5 ms	7.0	3.9	0.7	0.3	17.1

Board Repo: chipfoundry/breakout-pcb-standalone Board: breakout-tt04-qfn-openframe.kicad_pcb Folder breakout-tt04-qfn-openframe Complexity 280 / 1000 (size 195, features 85) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, curved board outline, knockout text, TrueType text Tested 9th November 2026 Copper layers 2 File format KiCad 9 (20241229) Parts, tracks, vias 13, 529, 93 Triangles, simulation 688,812 in 81 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 24 MB 388 MB STEP 127 MB 468 MB STL 34 MB 388 MB OBJ 71 MB 500 MB Visual GLB 23 MB 553 MB OBJ 69 MB 550 MB

735. caravel-M.2-card-QFN

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.7	1.5	0.4 ms	1.9	0.1	0.4	0.3	5.1
Simulation, STEP	0.2	0.6	1.5	0.3 ms	1.9	1.7	0.4	0.2	6.6
Simulation, STL	0.2	0.6	1.5	0.3 ms	2.0	0.2	0.4	0.3	5.1
Simulation, OBJ	0.2	0.6	1.5	0.5 ms	2.0	2.6	0.3	0.2	7.4
Visual, GLB	0.2	0.6	1.5	0.3 ms	5.5	59 ms	0.5	0.2	8.6
Visual, OBJ	0.2	0.6	1.6	0.4 ms	5.4	1.7	0.6	0.3	10.4

Board Repo: chipfoundry/caravel_board Board: caravel-M.2-card-QFN.kicad_pcb Folder hardware / breakout / caravel-M.2-card-QFN Complexity 301 / 1000 (size 211, features 90) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 11, 592, 95 Triangles, simulation 547,288 in 77 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 19 MB 299 MB STEP 85 MB 352 MB STL 27 MB 300 MB OBJ 56 MB 417 MB Visual GLB 13 MB 371 MB OBJ 40 MB 369 MB

736. Fab-Drawing-caravel-M.2-card-QFN

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.7	1.6	0.3 ms	1.9	92 ms	0.4	0.2	5.2
Simulation, STEP	0.3	0.6	1.5	0.3 ms	1.9	1.6	0.4	0.2	6.4
Simulation, STL	0.3	0.6	1.5	0.2 ms	2.0	0.2	0.4	0.2	5.1
Simulation, OBJ	0.2	0.6	1.6	0.2 ms	2.1	2.5	0.4	0.2	7.6
Visual, GLB	0.3	0.6	1.6	0.2 ms	5.2	67 ms	0.5	0.2	8.4
Visual, OBJ	0.3	0.6	1.5	0.3 ms	5.2	1.8	0.5	0.2	10.1

Board Repo: chipfoundry/caravel_board Board: Fab-Drawing-caravel-M.2-card-QFN.kicad_pcb Folder hardware / breakout / caravel-M.2-card-QFN Complexity 301 / 1000 (size 211, features 90) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 11, 592, 95 Triangles, simulation 547,288 in 77 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 19 MB 305 MB STEP 85 MB 362 MB STL 27 MB 299 MB OBJ 56 MB 429 MB Visual GLB 13 MB 368 MB OBJ 40 MB 369 MB

737. caravel-M.2-card-WCSP

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.2	0.5	1.5	0.3 ms	2.2	91 ms	0.3	0.2	4.9
Simulation, STEP	0.2	0.5	1.4	0.3 ms	2.2	1.7	0.4	0.3	6.6
Simulation, STL	0.2	0.5	1.4	0.3 ms	2.1	0.1	0.4	0.3	4.9
Simulation, OBJ	0.2	0.5	1.5	0.2 ms	2.2	2.7	0.4	0.2	7.7
Visual, GLB	0.2	0.5	1.5	0.3 ms	4.8	56 ms	0.3	0.3	7.7
Visual, OBJ	0.2	0.5	1.4	0.3 ms	4.9	1.9	0.4	0.2	9.6

Board Repo: chipfoundry/caravel_board Board: caravel-M.2-card-WCSP.kicad_pcb Folder hardware / breakout / caravel-M.2-card-WCSP Complexity 309 / 1000 (size 219, features 90) KESE features through vias, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ, copper finish Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 9, 555, 62 Triangles, simulation 439,070 in 76 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 16 MB 278 MB STEP 72 MB 320 MB STL 22 MB 274 MB OBJ 45 MB 356 MB Visual GLB 11 MB 329 MB OBJ 33 MB 327 MB

738. caravel-5V-dev-v6-M.2

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.9	5.9	0.7 ms	5.6	0.3	0.8	0.3	15.3
Simulation, STEP	0.5	1.8	6.4	0.9 ms	5.4	4.3	0.8	0.3	19.5
Simulation, STL	0.5	1.8	5.9	0.6 ms	5.9	0.5	0.7	0.2	15.5
Simulation, OBJ	0.5	1.9	6.3	0.6 ms	5.2	9.8	0.8	0.2	24.7
Visual, GLB	0.5	1.8	6.2	0.5 ms	11.6	0.2	1.2	0.3	21.8
Visual, OBJ	0.5	1.8	5.9	1 ms	11.4	5.9	1.3	0.3	27.1

Board Repo: chipfoundry/caravel_board Board: caravel-5V-dev-v6-M.2.kicad_pcb Folder hardware / development / _archive / caravel-dev-gf180-v6-M.2 Complexity 327 / 1000 (size 242, features 85) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 4 File format KiCad 7 (20221018) Parts, tracks, vias 82, 1,102, 175 Triangles, simulation 1,609,950 in 124 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 55 MB 545 MB STEP 201 MB 697 MB STL 81 MB 556 MB OBJ 167 MB 1.1 GB Visual GLB 34 MB 661 MB OBJ 102 MB 828 MB

739. caravel_pcb_v3_FTDI_flexy

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.3	7.5	0.7 ms	5.1	0.3	0.7	0.3	15.6
Simulation, STEP	0.5	1.2	6.9	0.9 ms	4.9	4.4	0.7	0.3	18.9
Simulation, STL	0.4	1.5	7.1	0.9 ms	4.7	0.5	0.8	0.2	15.2
Simulation, OBJ	0.4	1.2	7.2	1 ms	4.6	7.7	0.6	0.3	22.0
Visual, GLB	0.3	1.3	6.7	1 ms	10.5	0.2	1.0	0.2	20.2
Visual, OBJ	0.3	1.3	6.8	0.6 ms	10.8	5.4	1.0	0.3	26.0

Board Repo: chipfoundry/caravel_board Board: caravel_pcb_v3_FTDI_flexy.kicad_pcb Folder hardware / development / _archive / caravel_pcb_v3_FTDI_prev Complexity 311 / 1000 (size 216, features 95) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, drill offsets, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 6 (20211014) Parts, tracks, vias 58, 822, 104 Triangles, simulation 1,330,166 in 97 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 45 MB 549 MB STEP 229 MB 652 MB STL 67 MB 511 MB OBJ 136 MB 893 MB Visual GLB 32 MB 703 MB OBJ 96 MB 802 MB

740. caravel_pcb_v3_FTDI_flexy_fixed

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.2	6.9	0.6 ms	4.6	0.2	0.6	0.2	14.1
Simulation, STEP	0.4	1.2	6.5	0.5 ms	4.7	4.0	0.6	0.2	17.6
Simulation, STL	0.3	1.2	6.6	0.5 ms	5.1	0.5	0.6	0.2	14.6
Simulation, OBJ	0.4	1.2	6.7	0.6 ms	4.7	7.0	0.6	0.2	20.9
Visual, GLB	0.4	1.2	6.7	1.0 ms	10.8	0.2	1.4	0.2	20.9
Visual, OBJ	0.4	1.2	7.1	0.8 ms	10.7	5.5	1.5	0.2	26.6

Board Repo: chipfoundry/caravel_board Board: caravel_pcb_v3_FTDI_flexy_fixed.kicad_pcb Folder hardware / development / _archive / caravel_pcb_v3_FTDI_prev Complexity 311 / 1000 (size 216, features 95) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, drill offsets, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 6 (20211014) Parts, tracks, vias 58, 836, 104 Triangles, simulation 1,330,918 in 97 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 45 MB 534 MB STEP 229 MB 680 MB STL 67 MB 514 MB OBJ 137 MB 932 MB Visual GLB 32 MB 649 MB OBJ 96 MB 746 MB

741. clear-dev-v1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.4	5.8	1 ms	6.6	0.2	0.8	0.2	15.5
Simulation, STEP	0.4	1.4	6.0	0.8 ms	6.3	4.9	0.8	0.2	20.0
Simulation, STL	0.5	1.5	6.4	0.7 ms	6.0	0.5	0.8	0.3	16.0
Simulation, OBJ	0.5	1.5	6.6	2 ms	6.4	7.3	0.8	0.3	23.2
Visual, GLB	0.4	1.6	6.2	0.9 ms	13.5	0.2	1.6	0.2	23.7
Visual, OBJ	0.5	1.5	6.7	0.8 ms	13.1	6.0	1.6	0.2	29.6

Board Repo: chipfoundry/caravel_board Board: clear-dev-v1.kicad_pcb Folder hardware / development / _archive / clear-dev-v1 Complexity 328 / 1000 (size 228, features 100) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 82, 1,321, 186 Triangles, simulation 1,469,894 in 111 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 51 MB 614 MB STEP 256 MB 780 MB STL 74 MB 646 MB OBJ 152 MB 1.0 GB Visual GLB 42 MB 890 MB OBJ 126 MB 928 MB

742. Fab-Drawing-clear-dev-v1

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	1.3	5.4	0.7 ms	7.4	0.3	0.6	0.3	15.8
Simulation, STEP	0.6	1.2	5.5	0.6 ms	7.9	4.6	0.6	0.2	20.6
Simulation, STL	0.6	1.3	5.3	0.6 ms	7.9	0.4	0.6	0.2	16.3
Simulation, OBJ	0.6	1.2	5.3	0.5 ms	7.5	7.1	0.6	0.2	22.6
Visual, GLB	0.6	1.4	5.5	0.5 ms	12.9	0.2	1.4	0.2	22.3
Visual, OBJ	0.6	1.2	5.2	0.6 ms	13.3	5.8	1.7	0.2	28.0

Board Repo: chipfoundry/caravel_board Board: Fab-Drawing-clear-dev-v1.kicad_pcb Folder hardware / development / _archive / clear-dev-v1 Complexity 333 / 1000 (size 228, features 105) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 82, 1,321, 186 Triangles, simulation 1,657,796 in 11 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 57 MB 732 MB STEP 309 MB 949 MB STL 83 MB 705 MB OBJ 172 MB 1.1 GB Visual GLB 48 MB 1.1 GB OBJ 146 MB 999 MB

743. caravel-dev-v5-M.2

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.3	0.9	4.4	0.7 ms	4.3	0.2	0.6	0.2	10.9
Simulation, STEP	0.3	0.9	4.3	0.6 ms	4.2	3.2	0.6	0.2	13.7
Simulation, STL	0.3	0.9	4.3	0.6 ms	4.1	0.3	0.6	0.2	10.7
Simulation, OBJ	0.3	0.9	4.5	0.6 ms	4.3	4.9	0.6	0.2	15.7
Visual, GLB	0.3	0.9	4.3	0.7 ms	8.7	0.1	1.1	0.2	15.6
Visual, OBJ	0.3	0.9	4.4	0.6 ms	8.5	3.9	1.0	0.2	19.1

Board Repo: chipfoundry/caravel_board Board: caravel-dev-v5-M.2.kicad_pcb Folder hardware / development / caravel-dev-v5-M.2-revA Complexity 304 / 1000 (size 219, features 85) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 61, 946, 125 Triangles, simulation 1,185,610 in 112 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 41 MB 508 MB STEP 199 MB 642 MB STL 59 MB 494 MB OBJ 121 MB 806 MB Visual GLB 32 MB 631 MB OBJ 97 MB 736 MB

744. caravel-dev-v5-M.2

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.5	1.3	6.5	0.6 ms	5.4	0.2	0.7	0.2	14.9
Simulation, STEP	0.5	1.4	6.4	0.6 ms	5.4	4.3	0.7	0.3	18.9
Simulation, STL	0.5	1.3	6.3	0.6 ms	5.4	0.4	0.7	0.3	14.8
Simulation, OBJ	0.5	1.4	6.4	0.6 ms	5.4	7.0	0.7	0.2	21.5
Visual, GLB	0.5	1.3	6.2	0.6 ms	11.5	0.2	1.3	0.3	21.3
Visual, OBJ	0.5	1.3	6.4	0.9 ms	11.3	6.1	1.3	0.2	27.2

Board Repo: chipfoundry/caravel_board Board: caravel-dev-v5-M.2.kicad_pcb Folder hardware / development / caravel-dev-v5-M.2-revB Complexity 320 / 1000 (size 220, features 100) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, knockout text, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 67, 982, 118 Triangles, simulation 1,221,970 in 111 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 42 MB 559 MB STEP 212 MB 651 MB STL 61 MB 525 MB OBJ 125 MB 843 MB Visual GLB 34 MB 734 MB OBJ 101 MB 799 MB

745. Fab-Drawing-caravel-dev-v5-M.2

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	1.3	6.4	0.6 ms	5.4	0.3	0.7	0.3	15.1
Simulation, STEP	0.7	1.3	6.5	0.7 ms	5.3	4.2	0.7	0.3	19.0
Simulation, STL	0.8	1.4	6.4	0.7 ms	5.3	0.4	0.7	0.3	15.3
Simulation, OBJ	0.8	1.3	6.2	0.6 ms	5.3	7.2	0.7	0.3	21.8
Visual, GLB	0.7	1.3	6.2	0.9 ms	10.8	0.2	1.1	0.2	20.5
Visual, OBJ	0.7	1.3	6.3	1 ms	11.5	5.4	1.1	0.3	26.6

Board Repo: chipfoundry/caravel_board Board: Fab-Drawing-caravel-dev-v5-M.2.kicad_pcb Folder hardware / development / caravel-dev-v5-M.2-revB Complexity 325 / 1000 (size 220, features 105) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, knockout text, stack-up, dielectric εr and tanδ, mask and silkscreen colours Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 67, 982, 118 Triangles, simulation 1,222,914 in 111 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 42 MB 584 MB STEP 212 MB 679 MB STL 61 MB 534 MB OBJ 125 MB 843 MB Visual GLB 34 MB 649 MB OBJ 102 MB 776 MB

746. caravel-Nucleo-v2-M.2

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.6	1.9	9.8	1 ms	8.9	0.3	1.0	0.3	22.8
Simulation, STEP	0.6	1.7	9.6	1 ms	9.0	6.7	1.1	0.3	29.0
Simulation, STL	0.6	1.8	9.7	1 ms	8.9	0.6	1.1	0.3	22.9
Simulation, OBJ	0.6	1.8	9.8	1 ms	9.3	11.7	1.1	0.2	34.4
Visual, GLB	0.5	1.9	9.8	1.0 ms	18.9	0.3	1.9	0.3	33.7
Visual, OBJ	0.5	1.9	9.7	1 ms	18.6	8.3	1.9	0.3	41.2

Board Repo: chipfoundry/caravel_board Board: caravel-Nucleo-v2-M.2.kicad_pcb Folder hardware / nucleo / caravel-Nucleo-v2-M.2 Complexity 322 / 1000 (size 227, features 95) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 89, 1,180, 157 Triangles, simulation 1,978,734 in 216 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 68 MB 702 MB STEP 347 MB 912 MB STL 99 MB 692 MB OBJ 208 MB 1.3 GB Visual GLB 49 MB 985 MB OBJ 149 MB 1.0 GB

747. led-bar-pcb

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.1	0.2	0.9	0.2 ms	0.8	35 ms	0.1	0.2	2.4
Simulation, STEP	0.1	0.2	0.9	0.2 ms	0.8	1.2	0.1	0.3	3.6
Simulation, STL	0.1	0.2	0.9	0.3 ms	0.9	54 ms	0.1	0.2	2.4
Simulation, OBJ	0.1	0.2	0.9	0.3 ms	0.9	1.2	0.1	0.2	3.6
Visual, GLB	0.1	0.2	0.9	0.2 ms	1.8	20 ms	0.1	0.3	3.5
Visual, OBJ	0.1	0.2	0.8	0.2 ms	1.7	0.7	0.1	0.3	3.9

Board Repo: chipfoundry/caravel_board Board: led-bar-pcb.kicad_pcb Folder hardware / other / led-bar-pcb Complexity 175 / 1000 (size 105, features 70) KESE features rounded, trapezoid or chamfered pads, filled zones, curved board outline, stack-up, dielectric εr and tanδ Tested 9th November 2026 Copper layers 2 File format KiCad 7 (20221018) Parts, tracks, vias 12, 39, 0 Triangles, simulation 199,000 in 31 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 6.8 MB 207 MB STEP 30 MB 228 MB STL 10.0 MB 209 MB OBJ 20 MB 207 MB Visual GLB 4.1 MB 194 MB OBJ 12 MB 195 MB

748. ciaa_acc

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	6.7	33.1	61.3	3 ms	92.6	6.8	16.7	0.9	218.0
Simulation, STEP	7.2	33.6	63.9	2 ms	94.6	52.5	16.7	1.0	269.5
Simulation, STL	6.7	33.4	63.8	2 ms	94.1	10.7	16.6	1.1	226.4
Simulation, OBJ	6.2	33.5	62.4	3 ms	96.3	191.3	23.3	2.9	415.8
Visual, GLB	6.2	29.9	57.1	4 ms	149.9	1.7	14.5	0.6	259.9
Visual, OBJ	6.2	31.5	58.0	2 ms	149.5	62.7	14.5	0.7	323.1

Board Repo: ciaa/Hardware Board: ciaa_acc.kicad_pcb Folder PCB / ACC / CIAA_ACC Complexity 422 / 1000 (size 377, features 45) KESE features through vias, slotted holes, filled zones Tested 9th November 2026 to 11th November 2026 Copper layers 12 File format KiCad 5 (20171130) Parts, tracks, vias 550, 59,024, 1,875 Triangles, simulation 25,101,984 in 809 parts Verifier PASS in all six runs Run again Simulation, OBJ: failed in the corpus run, run again with no memory cap and no time limit (swap added to a 16 GB machine), and passed

File type File size Peak memory used Simulation GLB 858 MB 4.7 GB STEP 2.3 GB 6.1 GB STL 1.3 GB 4.9 GB OBJ 2.9 GB 16 GB Visual GLB 300 MB 5.3 GB OBJ 1.0 GB 6.7 GB

749. FPGA para todos

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	3.6	12.1	0.8 ms	7.9	0.3	1.1	0.3	26.0
Simulation, STEP	0.6	3.6	12.2	0.5 ms	8.1	6.1	1.0	0.3	31.9
Simulation, STL	0.6	3.6	12.6	1 ms	8.5	0.6	1.0	0.3	27.2
Simulation, OBJ	0.6	3.6	12.6	0.6 ms	8.5	11.6	0.9	0.3	38.1
Visual, GLB	0.5	3.5	12.5	1.0 ms	17.5	0.2	2.0	0.3	36.5
Visual, OBJ	0.6	3.8	12.1	0.8 ms	17.8	8.5	2.5	0.3	45.6

Board Repo: ciaa/Hardware Board: FPGA para todos.kicad_pcb Folder PCB / EDU-FPGA / Schematic Complexity 297 / 1000 (size 242, features 55) KESE features through vias, slotted holes, rounded, trapezoid or chamfered pads, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 5 (20171130) Parts, tracks, vias 125, 1,674, 196 Triangles, simulation 1,757,582 in 196 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 62 MB 760 MB STEP 327 MB 841 MB STL 88 MB 762 MB OBJ 187 MB 1.2 GB Visual GLB 46 MB 825 MB OBJ 141 MB 971 MB

750. EDU_CIAA_K60

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	3.0	20.9	1 ms	22.1	0.5	1.7	0.3	49.3
Simulation, STEP	0.8	2.8	19.7	0.7 ms	22.4	8.3	1.6	0.3	55.9
Simulation, STL	0.7	2.9	19.9	0.8 ms	22.7	0.8	1.6	0.3	49.0
Simulation, OBJ	0.8	3.0	20.0	0.7 ms	22.9	15.6	1.8	0.4	64.4
Visual, GLB	0.9	3.0	20.4	0.7 ms	29.1	0.3	3.3	0.3	57.2
Visual, OBJ	0.7	3.0	20.0	0.8 ms	28.7	11.8	3.5	0.3	68.0

Board Repo: ciaa/Hardware Board: EDU_CIAA_K60.kicad_pcb Folder PCB / EDU-FSL / EDU_CIAA_K60 Complexity 307 / 1000 (size 252, features 55) KESE features through vias, slotted holes, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 4 (4) Parts, tracks, vias 177, 2,647, 173 Triangles, simulation 2,377,654 in 250 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 85 MB 878 MB STEP 460 MB 1.2 GB STL 119 MB 880 MB OBJ 259 MB 1.6 GB Visual GLB 68 MB 1.3 GB OBJ 208 MB 1.4 GB

751. edk

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.4	1.4	6.6	0.6 ms	5.2	0.2	0.7	0.3	14.7
Simulation, STEP	0.3	1.3	6.6	0.6 ms	5.1	4.2	0.7	0.3	18.5
Simulation, STL	0.4	1.3	6.6	1.0 ms	5.1	0.3	0.7	0.2	14.7
Simulation, OBJ	0.3	1.4	6.5	0.9 ms	5.1	6.6	0.7	0.2	20.8
Visual, GLB	0.4	1.4	6.5	0.7 ms	13.9	0.2	1.2	0.2	23.8
Visual, OBJ	0.4	1.3	6.4	0.6 ms	14.4	6.2	1.5	0.3	30.5

Board Repo: ciaa/Hardware Board: edk.kicad_pcb Folder PCB / EDU-INTEL Complexity 271 / 1000 (size 226, features 45) KESE features through vias, slotted holes, filled zones Tested 9th November 2026 Copper layers 2 File format KiCad 4 (4) Parts, tracks, vias 83, 1,298, 110 Triangles, simulation 1,143,178 in 162 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 40 MB 588 MB STEP 221 MB 647 MB STL 57 MB 576 MB OBJ 119 MB 783 MB Visual GLB 37 MB 759 MB OBJ 111 MB 789 MB

752. edu-ciaa-nxp

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.8	3.0	21.5	0.7 ms	49.2	0.5	1.8	0.3	77.2
Simulation, STEP	0.9	3.2	21.9	0.6 ms	48.1	9.1	1.7	0.3	85.2
Simulation, STL	0.8	2.9	20.4	0.6 ms	47.8	0.9	1.7	0.3	74.8
Simulation, OBJ	0.9	3.0	21.0	0.5 ms	47.6	14.7	1.7	0.3	89.2
Visual, GLB	0.9	3.2	21.0	0.9 ms	31.4	0.4	3.5	0.3	60.6
Visual, OBJ	0.9	3.1	20.8	0.7 ms	30.1	12.5	3.8	0.3	71.4

Board Repo: ciaa/Hardware Board: edu-ciaa-nxp.kicad_pcb Folder PCB / EDU-NXP Complexity 310 / 1000 (size 255, features 55) KESE features through vias, slotted holes, filled zones, curved board outline Tested 9th November 2026 Copper layers 2 File format KiCad 4 (4) Parts, tracks, vias 183, 3,006, 261 Triangles, simulation 2,584,942 in 178 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 92 MB 957 MB STEP 500 MB 1.2 GB STL 129 MB 951 MB OBJ 280 MB 1.8 GB Visual GLB 74 MB 1.3 GB OBJ 228 MB 1.5 GB

753. CIAA_FSL_MINI

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	0.7	3.1	9.4	1 ms	8.6	0.5	1.3	0.3	24.0
Simulation, STEP	0.6	2.9	9.2	1 ms	8.1	6.1	1.4	0.3	28.6
Simulation, STL	0.6	3.0	9.4	1 ms	8.4	0.9	1.4	0.3	24.0
Simulation, OBJ	0.5	3.0	9.1	1 ms	8.2	12.2	1.4	0.3	34.8
Visual, GLB	0.5	3.0	9.0	1 ms	18.4	0.2	2.4	0.3	34.0
Visual, OBJ	0.6	2.8	9.2	1 ms	18.6	7.8	2.6	0.2	41.8

Board Repo: ciaa/Hardware Board: CIAA_FSL_MINI.kicad_pcb Folder PCB / FSL-MINI Complexity 294 / 1000 (size 259, features 35) KESE features through vias, filled zones Tested 9th November 2026 Copper layers 4 File format KiCad 4 (4) Parts, tracks, vias 132, 2,318, 294 Triangles, simulation 2,465,310 in 200 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 85 MB 915 MB STEP 316 MB 950 MB STL 123 MB 856 MB OBJ 260 MB 1.6 GB Visual GLB 52 MB 983 MB OBJ 161 MB 1.1 GB

754. CIAA_K60

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.4	6.9	24.8	1 ms	20.6	1.2	3.1	0.3	58.3
Simulation, STEP	1.3	7.1	25.0	2 ms	20.5	12.8	2.8	0.3	69.9
Simulation, STL	1.3	7.2	24.9	1 ms	20.8	1.9	3.1	0.4	59.5
Simulation, OBJ	1.3	7.1	25.0	1 ms	20.7	29.9	2.8	0.4	87.2
Visual, GLB	1.3	7.0	25.1	1 ms	48.5	0.6	7.0	0.3	89.8
Visual, OBJ	1.3	7.3	24.8	2 ms	49.8	21.1	7.7	0.3	112.3

Board Repo: ciaa/Hardware Board: CIAA_K60.kicad_pcb Folder PCB / FSL / CIAA_K60 Complexity 337 / 1000 (size 292, features 45) KESE features through vias, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 3 (3) Parts, tracks, vias 455, 4,461, 456 Triangles, simulation 4,924,524 in 340 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 176 MB 1.4 GB STEP 795 MB 1.8 GB STL 246 MB 1.4 GB OBJ 544 MB 3.3 GB Visual GLB 125 MB 2.0 GB OBJ 394 MB 2.6 GB

755. ciaa-nxp

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.5	6.4	22.6	1 ms	22.4	1.1	3.0	0.4	57.4
Simulation, STEP	1.6	7.2	22.4	2 ms	21.8	12.9	3.3	0.3	69.5
Simulation, STL	1.6	6.7	21.2	1 ms	21.8	2.1	3.2	0.4	56.9
Simulation, OBJ	1.6	6.5	22.6	2 ms	22.2	29.2	3.1	0.4	85.7
Visual, GLB	1.5	6.8	22.5	1 ms	54.3	0.6	6.7	0.4	92.7
Visual, OBJ	1.6	6.5	23.1	1 ms	53.4	19.3	6.6	0.3	110.7

Board Repo: ciaa/Hardware Board: ciaa-nxp.kicad_pcb Folder PCB / NXP Complexity 332 / 1000 (size 297, features 35) KESE features through vias, filled zones Tested 9th November 2026 Copper layers 4 File format KiCad 5 (20171130) Parts, tracks, vias 430, 8,086, 618 Triangles, simulation 5,554,394 in 389 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 197 MB 1.6 GB STEP 840 MB 1.9 GB STL 278 MB 1.6 GB OBJ 610 MB 3.6 GB Visual GLB 130 MB 2.1 GB OBJ 414 MB 2.8 GB

756. ciaa-pic

Mode and format	1–2 read	3 resolve	4 geometry	5 materials	6 assemble	7 write	8 verify	start-up and exit	Total
Simulation, GLB	1.2	6.0	17.0	3 ms	16.4	0.8	2.0	0.3	43.7
Simulation, STEP	1.1	6.4	16.9	1 ms	16.3	9.7	2.0	0.3	52.6
Simulation, STL	1.1	6.4	17.0	1 ms	16.3	1.4	2.1	0.3	44.6
Simulation, OBJ	1.0	6.2	16.9	1 ms	16.3	21.9	2.3	0.4	65.0
Visual, GLB	1.0	6.5	17.0	2 ms	40.2	0.5	5.5	0.3	71.0
Visual, OBJ	1.1	6.4	17.2	1 ms	41.3	15.0	6.3	0.3	87.6

Board Repo: ciaa/Hardware Board: ciaa-pic.kicad_pcb Folder PCB / PIC Complexity 340 / 1000 (size 295, features 45) KESE features through vias, filled zones, curved board outline Tested 9th November 2026 Copper layers 4 File format KiCad 4 (4) Parts, tracks, vias 423, 5,588, 506 Triangles, simulation 4,767,406 in 329 parts Verifier PASS in all six runs

File type File size Peak memory used Simulation GLB 170 MB 1.3 GB STEP 762 MB 1.8 GB STL 238 MB 1.4 GB OBJ 524 MB 3.2 GB Visual GLB 119 MB 1.9 GB OBJ 376 MB 2.5 GB

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