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18. Feature Test Collection

Every board of featureTest/, section by section, with its top and bottom and where the time of a run goes:

  • The folder's README says what each board holds.
  • Each board was exported in every format KESE writes, one format a run: GLB, STEP, STL and OBJ in simulation mode, and GLB and OBJ in visual mode. Each of those six runs was made three times, with the Verifier, the solder mask and the silkscreen on and the board's own settings, as the regression suite (Generator/tests/test_boards.py) sets them.
  • Each bar is the median of the three runs for that stage, from the timing block of report.txt. All 720 runs passed the Verifier.
  • Beside each board's facts, a second table gives, for each of the six runs, the size of the model file it writes and the most memory it used at once: the proportional set size (PSS) of KESE's process and its workers, summed and sampled every 10 ms, the median of three more runs. The STL size is that of the stl/ folder, one file a part, and the OBJ size includes its .mtl. MB is a million bytes.
  • The command for board 11, simulation mode with GLB; the other five runs differ only in --format step, stl or obj, or in --mode visual with --format glb or obj:
python run_KESE.py ../featureTest/11_zones.kicad_pcb --mode simulation --format glb --verify \
    --set SolderMask.SOLDER_MASK_ENABLED=True --set Silkscreen.SILKSCREEN_ENABLED=True

The runs used the default parameters otherwise, on one Linux machine with 4 cores (an Intel Xeon at 2.1 GHz) and 16 GB of RAM, so Parallel.WORKERS = 0 gave four workers (Work Done In Parallel). On another machine the seconds differ.

18.1 Every Board At A Glance

Every board's total time in each of the six runs, one format a run, seconds a run

All the feature boards but 16b and 25 take 0.2 to 3.5 s a run, in any format. The fixed part of a run, reading the file and Python starting and exiting, takes 0.16 to 0.33 s of it; a board without text never reads the stroke font, so boards 05, 08b, 19b and 26 read and collect in under 11 ms. Board 16b, a plated border and 91 vias on four layers, takes 5.6 to 8.6 s; board 25, whose countersinks are built as steps, 2.9 to 5.4 s; and the example boards 6.6 to 23.4 s. Simulation with GLB or STL is the quickest of the six runs on every board but 09 and 27, where visual GLB is.

18.2 Holes And Vias

18.2.1 01 Slotted Holes

01 Slotted holes straight from above in visual mode 01 Slotted holes straight from below in visual mode, mirrored as KiCad flips the board

01 Slotted holes: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 42% to 64% of a run. Simulation with GLB takes 0.9 s: read 70 ms, resolve 56 ms, geometry 0.2, materials 0.2 ms, assemble 0.3, write 8 ms, verify 41 ms, start-up and exit 0.2. Simulation with STEP takes 1.3 s: read 74 ms, resolve 55 ms, geometry 0.2, materials 0.1 ms, assemble 0.4, write 0.4, verify 36 ms, start-up and exit 0.2. Simulation with STL takes 0.9 s: read 69 ms, resolve 51 ms, geometry 0.2, materials 0.1 ms, assemble 0.4, write 11 ms, verify 40 ms, start-up and exit 0.2. Simulation with OBJ takes 1.2 s: read 74 ms, resolve 53 ms, geometry 0.2, materials 0.1 ms, assemble 0.4, write 0.2, verify 41 ms, start-up and exit 0.2. Visual with GLB takes 1.1 s: read 83 ms, resolve 56 ms, geometry 0.2, materials 0.1 ms, assemble 0.5, write 7 ms, verify 40 ms, start-up and exit 0.2. Visual with OBJ takes 1.2 s: read 68 ms, resolve 53 ms, geometry 0.2, materials 0.2 ms, assemble 0.5, write 0.1, verify 40 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 70 ms 56 ms 0.2 0.2 ms 0.3 8 ms 41 ms 0.2 0.9
Simulation, STEP 74 ms 55 ms 0.2 0.1 ms 0.4 0.4 36 ms 0.2 1.3
Simulation, STL 69 ms 51 ms 0.2 0.1 ms 0.4 11 ms 40 ms 0.2 0.9
Simulation, OBJ 74 ms 53 ms 0.2 0.1 ms 0.4 0.2 41 ms 0.2 1.2
Visual, GLB 83 ms 56 ms 0.2 0.1 ms 0.5 7 ms 40 ms 0.2 1.1
Visual, OBJ 68 ms 53 ms 0.2 0.2 ms 0.5 0.1 40 ms 0.2 1.2
Board featureTest/
01_holes_slotted.kicad_pcb
Outline 40 × 26 mm
Thickness 1.6 mm
Copper layers 2
Vias none
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 1.1 MB 69 MB
STEP 5.8 MB 72 MB
STL 1.8 MB 69 MB
OBJ 3.2 MB 76 MB
Visual
GLB 661 kB 95 MB
OBJ 1.8 MB 97 MB

18.2.2 02 Round Holes

02 Round holes straight from above in visual mode 02 Round holes straight from below in visual mode, mirrored as KiCad flips the board

02 Round holes: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 45% to 62% of a run. Simulation with GLB takes 0.9 s: read 76 ms, resolve 45 ms, geometry 0.2, materials 0.1 ms, assemble 0.4, write 8 ms, verify 34 ms, start-up and exit 0.2. Simulation with STEP takes 1.2 s: read 73 ms, resolve 46 ms, geometry 0.2, materials 0.1 ms, assemble 0.4, write 0.3, verify 31 ms, start-up and exit 0.2. Simulation with STL takes 0.9 s: read 67 ms, resolve 42 ms, geometry 0.2, materials 0.1 ms, assemble 0.4, write 12 ms, verify 31 ms, start-up and exit 0.2. Simulation with OBJ takes 1.1 s: read 72 ms, resolve 49 ms, geometry 0.2, materials 0.1 ms, assemble 0.4, write 0.2, verify 31 ms, start-up and exit 0.2. Visual with GLB takes 1.0 s: read 71 ms, resolve 46 ms, geometry 0.2, materials 0.1 ms, assemble 0.4, write 6 ms, verify 42 ms, start-up and exit 0.2. Visual with OBJ takes 1.1 s: read 66 ms, resolve 39 ms, geometry 0.2, materials 0.1 ms, assemble 0.4, write 0.1, verify 43 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 76 ms 45 ms 0.2 0.1 ms 0.4 8 ms 34 ms 0.2 0.9
Simulation, STEP 73 ms 46 ms 0.2 0.1 ms 0.4 0.3 31 ms 0.2 1.2
Simulation, STL 67 ms 42 ms 0.2 0.1 ms 0.4 12 ms 31 ms 0.2 0.9
Simulation, OBJ 72 ms 49 ms 0.2 0.1 ms 0.4 0.2 31 ms 0.2 1.1
Visual, GLB 71 ms 46 ms 0.2 0.1 ms 0.4 6 ms 42 ms 0.2 1.0
Visual, OBJ 66 ms 39 ms 0.2 0.1 ms 0.4 0.1 43 ms 0.2 1.1
Board featureTest/
02_holes_round.kicad_pcb
Outline 34 × 20 mm
Thickness 1.6 mm
Copper layers 2
Vias none
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 1.3 MB 68 MB
STEP 4.1 MB 72 MB
STL 1.9 MB 70 MB
OBJ 3.4 MB 79 MB
Visual
GLB 741 kB 99 MB
OBJ 2.0 MB 99 MB

18.2.3 03 Through Vias

03 Through vias straight from above in visual mode 03 Through vias straight from below in visual mode, mirrored as KiCad flips the board

03 Through vias: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 55% to 68% of a run. Simulation with GLB takes 1.2 s: read 67 ms, resolve 51 ms, geometry 0.2, materials 0.1 ms, assemble 0.5, write 11 ms, verify 44 ms, start-up and exit 0.2. Simulation with STEP takes 1.6 s: read 71 ms, resolve 58 ms, geometry 0.2, materials 0.1 ms, assemble 0.6, write 0.3, verify 49 ms, start-up and exit 0.2. Simulation with STL takes 1.2 s: read 67 ms, resolve 51 ms, geometry 0.2, materials 0.1 ms, assemble 0.6, write 20 ms, verify 48 ms, start-up and exit 0.2. Simulation with OBJ takes 1.5 s: read 66 ms, resolve 55 ms, geometry 0.2, materials 0.1 ms, assemble 0.6, write 0.3, verify 55 ms, start-up and exit 0.2. Visual with GLB takes 1.2 s: read 67 ms, resolve 55 ms, geometry 0.2, materials 0.1 ms, assemble 0.6, write 6 ms, verify 67 ms, start-up and exit 0.2. Visual with OBJ takes 1.3 s: read 82 ms, resolve 60 ms, geometry 0.2, materials 0.1 ms, assemble 0.6, write 0.1, verify 60 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 67 ms 51 ms 0.2 0.1 ms 0.5 11 ms 44 ms 0.2 1.2
Simulation, STEP 71 ms 58 ms 0.2 0.1 ms 0.6 0.3 49 ms 0.2 1.6
Simulation, STL 67 ms 51 ms 0.2 0.1 ms 0.6 20 ms 48 ms 0.2 1.2
Simulation, OBJ 66 ms 55 ms 0.2 0.1 ms 0.6 0.3 55 ms 0.2 1.5
Visual, GLB 67 ms 55 ms 0.2 0.1 ms 0.6 6 ms 67 ms 0.2 1.2
Visual, OBJ 82 ms 60 ms 0.2 0.1 ms 0.6 0.1 60 ms 0.2 1.3
Board featureTest/
03_vias_through.kicad_pcb
Outline 32 × 20 mm
Thickness 1.6 mm
Copper layers 2
Vias 12 through
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 1.7 MB 72 MB
STEP 5.7 MB 77 MB
STL 2.6 MB 74 MB
OBJ 4.7 MB 92 MB
Visual
GLB 834 kB 111 MB
OBJ 2.3 MB 117 MB

18.2.4 03b KiCad 10 Via Options

03b KiCad 10 via options straight from above in visual mode 03b KiCad 10 via options straight from below in visual mode, mirrored as KiCad flips the board

03b KiCad 10 via options: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 42% to 82% of a run. Simulation with GLB takes 1.5 s: read 69 ms, resolve 0.1, geometry 0.3, materials 0.1 ms, assemble 0.7, write 16 ms, verify 0.1, start-up and exit 0.2. Simulation with STEP takes 2.2 s: read 80 ms, resolve 0.2, geometry 0.3, materials 0.1 ms, assemble 0.6, write 0.7, verify 0.1, start-up and exit 0.2. Simulation with STL takes 1.4 s: read 76 ms, resolve 0.1, geometry 0.3, materials 0.2 ms, assemble 0.6, write 25 ms, verify 97 ms, start-up and exit 0.2. Simulation with OBJ takes 1.8 s: read 75 ms, resolve 0.1, geometry 0.3, materials 0.2 ms, assemble 0.6, write 0.4, verify 94 ms, start-up and exit 0.2. Visual with GLB takes 3.2 s: read 92 ms, resolve 0.2, geometry 0.3, materials 0.1 ms, assemble 2.4, write 14 ms, verify 90 ms, start-up and exit 0.2. Visual with OBJ takes 3.5 s: read 74 ms, resolve 0.2, geometry 0.3, materials 0.1 ms, assemble 2.4, write 0.3, verify 78 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 69 ms 0.1 0.3 0.1 ms 0.7 16 ms 0.1 0.2 1.5
Simulation, STEP 80 ms 0.2 0.3 0.1 ms 0.6 0.7 0.1 0.2 2.2
Simulation, STL 76 ms 0.1 0.3 0.2 ms 0.6 25 ms 97 ms 0.2 1.4
Simulation, OBJ 75 ms 0.1 0.3 0.2 ms 0.6 0.4 94 ms 0.2 1.8
Visual, GLB 92 ms 0.2 0.3 0.1 ms 2.4 14 ms 90 ms 0.2 3.2
Visual, OBJ 74 ms 0.2 0.3 0.1 ms 2.4 0.3 78 ms 0.2 3.5
Board featureTest/
03b_vias_k10.kicad_pcb
Outline 40 × 30 mm
Thickness 1.6 mm
Copper layers 4
Vias 18: 1 micro, 2 blind and buried,
15 through
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 2.6 MB 171 MB
STEP 7.1 MB 177 MB
STL 4.0 MB 173 MB
OBJ 7.4 MB 173 MB
Visual
GLB 1.6 MB 153 MB
OBJ 4.6 MB 153 MB

18.2.5 04 Blind And Buried Vias

04 Blind and buried vias straight from above in visual mode 04 Blind and buried vias straight from below in visual mode, mirrored as KiCad flips the board

04 Blind and buried vias: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 37% to 54% of a run. Simulation with GLB takes 0.7 s: read 73 ms, resolve 51 ms, geometry 62 ms, materials 0.1 ms, assemble 0.2, write 5 ms, verify 26 ms, start-up and exit 0.2. Simulation with STEP takes 0.8 s: read 68 ms, resolve 50 ms, geometry 59 ms, materials 0.1 ms, assemble 0.2, write 0.2, verify 22 ms, start-up and exit 0.2. Simulation with STL takes 0.6 s: read 68 ms, resolve 51 ms, geometry 59 ms, materials 0.1 ms, assemble 0.2, write 8 ms, verify 21 ms, start-up and exit 0.2. Simulation with OBJ takes 0.7 s: read 66 ms, resolve 55 ms, geometry 62 ms, materials 0.1 ms, assemble 0.2, write 0.1, verify 22 ms, start-up and exit 0.2. Visual with GLB takes 0.8 s: read 70 ms, resolve 54 ms, geometry 59 ms, materials 0.1 ms, assemble 0.4, write 5 ms, verify 37 ms, start-up and exit 0.2. Visual with OBJ takes 0.8 s: read 69 ms, resolve 53 ms, geometry 63 ms, materials 0.1 ms, assemble 0.4, write 47 ms, verify 32 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 73 ms 51 ms 62 ms 0.1 ms 0.2 5 ms 26 ms 0.2 0.7
Simulation, STEP 68 ms 50 ms 59 ms 0.1 ms 0.2 0.2 22 ms 0.2 0.8
Simulation, STL 68 ms 51 ms 59 ms 0.1 ms 0.2 8 ms 21 ms 0.2 0.6
Simulation, OBJ 66 ms 55 ms 62 ms 0.1 ms 0.2 0.1 22 ms 0.2 0.7
Visual, GLB 70 ms 54 ms 59 ms 0.1 ms 0.4 5 ms 37 ms 0.2 0.8
Visual, OBJ 69 ms 53 ms 63 ms 0.1 ms 0.4 47 ms 32 ms 0.2 0.8
Board featureTest/
04_vias_blind_buried.kicad_pcb
Outline 32 × 20 mm
Thickness 1.6 mm
Copper layers 6
Vias 6: 3 blind and buried, 3 through
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 679 kB 69 MB
STEP 1.5 MB 67 MB
STL 1.0 MB 66 MB
OBJ 1.8 MB 70 MB
Visual
GLB 327 kB 91 MB
OBJ 815 kB 92 MB

18.2.6 05 Microvias

05 Microvias straight from above in visual mode 05 Microvias straight from below in visual mode, mirrored as KiCad flips the board

05 Microvias: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 40% to 54% of a run. Simulation with GLB takes 0.6 s: read 3 ms, resolve 54 ms, geometry 61 ms, materials 0.1 ms, assemble 0.2, write 5 ms, verify 21 ms, start-up and exit 0.2. Simulation with STEP takes 0.6 s: read 3 ms, resolve 55 ms, geometry 49 ms, materials 0.1 ms, assemble 0.2, write 0.1, verify 20 ms, start-up and exit 0.2. Simulation with STL takes 0.6 s: read 3 ms, resolve 50 ms, geometry 57 ms, materials 0.1 ms, assemble 0.2, write 6 ms, verify 25 ms, start-up and exit 0.2. Simulation with OBJ takes 0.6 s: read 3 ms, resolve 58 ms, geometry 49 ms, materials 0.1 ms, assemble 0.2, write 97 ms, verify 22 ms, start-up and exit 0.2. Visual with GLB takes 0.7 s: read 4 ms, resolve 60 ms, geometry 52 ms, materials 0.1 ms, assemble 0.3, write 3 ms, verify 49 ms, start-up and exit 0.2. Visual with OBJ takes 0.7 s: read 3 ms, resolve 59 ms, geometry 55 ms, materials 0.1 ms, assemble 0.3, write 30 ms, verify 49 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 3 ms 54 ms 61 ms 0.1 ms 0.2 5 ms 21 ms 0.2 0.6
Simulation, STEP 3 ms 55 ms 49 ms 0.1 ms 0.2 0.1 20 ms 0.2 0.6
Simulation, STL 3 ms 50 ms 57 ms 0.1 ms 0.2 6 ms 25 ms 0.2 0.6
Simulation, OBJ 3 ms 58 ms 49 ms 0.1 ms 0.2 97 ms 22 ms 0.2 0.6
Visual, GLB 4 ms 60 ms 52 ms 0.1 ms 0.3 3 ms 49 ms 0.2 0.7
Visual, OBJ 3 ms 59 ms 55 ms 0.1 ms 0.3 30 ms 49 ms 0.2 0.7
Board featureTest/
05_vias_micro.kicad_pcb
Outline 30 × 16 mm
Thickness 1.6 mm
Copper layers 8
Vias 12: 10 micro, 2 blind and buried
Board edge Plain
Mask, silkscreen, finish Mask colour not set (drawn green),
no silkscreen, ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 584 kB 45 MB
STEP 1.1 MB 47 MB
STL 859 kB 46 MB
OBJ 1.5 MB 50 MB
Visual
GLB 206 kB 80 MB
OBJ 497 kB 82 MB

18.2.7 24 Backdrills

24 Backdrills straight from above in visual mode 24 Backdrills straight from below in visual mode, mirrored as KiCad flips the board

24 Backdrills: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 40% to 75% of a run. Simulation with GLB takes 1.5 s: read 82 ms, resolve 0.2, geometry 0.3, materials 0.1 ms, assemble 0.6, write 22 ms, verify 90 ms, start-up and exit 0.2. Simulation with STEP takes 2.2 s: read 73 ms, resolve 0.2, geometry 0.3, materials 0.2 ms, assemble 0.6, write 0.8, verify 90 ms, start-up and exit 0.2. Simulation with STL takes 1.3 s: read 72 ms, resolve 0.2, geometry 0.2, materials 0.2 ms, assemble 0.6, write 28 ms, verify 86 ms, start-up and exit 0.2. Simulation with OBJ takes 1.9 s: read 70 ms, resolve 0.2, geometry 0.2, materials 0.2 ms, assemble 0.6, write 0.5, verify 90 ms, start-up and exit 0.2. Visual with GLB takes 2.0 s: read 70 ms, resolve 0.2, geometry 0.3, materials 0.2 ms, assemble 1.3, write 12 ms, verify 75 ms, start-up and exit 0.2. Visual with OBJ takes 2.3 s: read 72 ms, resolve 0.2, geometry 0.3, materials 0.1 ms, assemble 1.3, write 0.3, verify 68 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 82 ms 0.2 0.3 0.1 ms 0.6 22 ms 90 ms 0.2 1.5
Simulation, STEP 73 ms 0.2 0.3 0.2 ms 0.6 0.8 90 ms 0.2 2.2
Simulation, STL 72 ms 0.2 0.2 0.2 ms 0.6 28 ms 86 ms 0.2 1.3
Simulation, OBJ 70 ms 0.2 0.2 0.2 ms 0.6 0.5 90 ms 0.2 1.9
Visual, GLB 70 ms 0.2 0.3 0.2 ms 1.3 12 ms 75 ms 0.2 2.0
Visual, OBJ 72 ms 0.2 0.3 0.1 ms 1.3 0.3 68 ms 0.2 2.3
Board featureTest/
24_backdrills.kicad_pcb
Outline 52 × 32 mm
Thickness 1.6 mm
Copper layers 6
Vias 15: 1 blind and buried, 14 through
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 3.6 MB 173 MB
STEP 10.0 MB 180 MB
STL 5.4 MB 173 MB
OBJ 10.0 MB 172 MB
Visual
GLB 1.8 MB 151 MB
OBJ 5.0 MB 151 MB

18.2.8 25 Counterbores And Countersinks

25 Counterbores and countersinks straight from above in visual mode 25 Counterbores and countersinks straight from below in visual mode, mirrored as KiCad flips the board

25 Counterbores and countersinks: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 63% to 89% of a run. Simulation with GLB takes 2.9 s: read 76 ms, resolve 0.1, geometry 0.8, materials 0.1 ms, assemble 1.5, write 15 ms, verify 0.1, start-up and exit 0.2. Simulation with STEP takes 3.8 s: read 75 ms, resolve 0.1, geometry 0.8, materials 0.1 ms, assemble 1.6, write 0.9, verify 0.1, start-up and exit 0.2. Simulation with STL takes 3.0 s: read 74 ms, resolve 0.2, geometry 0.9, materials 0.1 ms, assemble 1.5, write 21 ms, verify 0.1, start-up and exit 0.2. Simulation with OBJ takes 3.5 s: read 74 ms, resolve 0.1, geometry 0.9, materials 0.1 ms, assemble 1.6, write 0.4, verify 0.2, start-up and exit 0.2. Visual with GLB takes 4.9 s: read 75 ms, resolve 0.1, geometry 0.9, materials 0.1 ms, assemble 3.5, write 14 ms, verify 88 ms, start-up and exit 0.2. Visual with OBJ takes 5.4 s: read 81 ms, resolve 0.1, geometry 0.9, materials 0.1 ms, assemble 3.6, write 0.4, verify 77 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 76 ms 0.1 0.8 0.1 ms 1.5 15 ms 0.1 0.2 2.9
Simulation, STEP 75 ms 0.1 0.8 0.1 ms 1.6 0.9 0.1 0.2 3.8
Simulation, STL 74 ms 0.2 0.9 0.1 ms 1.5 21 ms 0.1 0.2 3.0
Simulation, OBJ 74 ms 0.1 0.9 0.1 ms 1.6 0.4 0.2 0.2 3.5
Visual, GLB 75 ms 0.1 0.9 0.1 ms 3.5 14 ms 88 ms 0.2 4.9
Visual, OBJ 81 ms 0.1 0.9 0.1 ms 3.6 0.4 77 ms 0.2 5.4
Board featureTest/
25_post_machining.kicad_pcb
Outline 60 × 36 mm
Thickness 1.6 mm
Copper layers 4
Vias 3 through
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 2.7 MB 205 MB
STEP 3.6 MB 204 MB
STL 3.7 MB 208 MB
OBJ 7.4 MB 204 MB
Visual
GLB 2.2 MB 173 MB
OBJ 6.3 MB 173 MB

18.2.9 26 Via Protection

26 Via protection straight from above in visual mode 26 Via protection straight from below in visual mode, mirrored as KiCad flips the board

26 Via protection: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 38% to 73% of a run. Simulation with GLB takes 1.1 s: read 6 ms, resolve 0.1, geometry 0.2, materials 0.1 ms, assemble 0.5, write 16 ms, verify 59 ms, start-up and exit 0.2. Simulation with STEP takes 1.7 s: read 5 ms, resolve 0.1, geometry 0.1, materials 0.1 ms, assemble 0.5, write 0.7, verify 62 ms, start-up and exit 0.2. Simulation with STL takes 1.1 s: read 5 ms, resolve 0.1, geometry 0.2, materials 0.1 ms, assemble 0.5, write 20 ms, verify 59 ms, start-up and exit 0.2. Simulation with OBJ takes 1.5 s: read 5 ms, resolve 0.1, geometry 0.2, materials 0.2 ms, assemble 0.5, write 0.4, verify 62 ms, start-up and exit 0.2. Visual with GLB takes 1.6 s: read 5 ms, resolve 0.1, geometry 0.2, materials 0.2 ms, assemble 1.0, write 8 ms, verify 0.1, start-up and exit 0.2. Visual with OBJ takes 1.9 s: read 5 ms, resolve 0.1, geometry 0.2, materials 0.2 ms, assemble 1.1, write 0.2, verify 73 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 6 ms 0.1 0.2 0.1 ms 0.5 16 ms 59 ms 0.2 1.1
Simulation, STEP 5 ms 0.1 0.1 0.1 ms 0.5 0.7 62 ms 0.2 1.7
Simulation, STL 5 ms 0.1 0.2 0.1 ms 0.5 20 ms 59 ms 0.2 1.1
Simulation, OBJ 5 ms 0.1 0.2 0.2 ms 0.5 0.4 62 ms 0.2 1.5
Visual, GLB 5 ms 0.1 0.2 0.2 ms 1.0 8 ms 0.1 0.2 1.6
Visual, OBJ 5 ms 0.1 0.2 0.2 ms 1.1 0.2 73 ms 0.2 1.9
Board featureTest/
26_via_protection.kicad_pcb
Outline 60 × 24 mm
Thickness 1.6 mm
Copper layers 4
Vias 22: 3 blind and buried, 19 through
Board edge Plain
Mask, silkscreen, finish Mask colour not set (drawn green),
no silkscreen, ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 2.2 MB 154 MB
STEP 6.7 MB 155 MB
STL 3.6 MB 152 MB
OBJ 6.7 MB 150 MB
Visual
GLB 1.1 MB 131 MB
OBJ 3.1 MB 130 MB

18.3 Pads

18.3.1 06 Padstacks

06 Padstacks straight from above in visual mode 06 Padstacks straight from below in visual mode, mirrored as KiCad flips the board

06 Padstacks: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 44% to 64% of a run. Simulation with GLB takes 0.7 s: read 68 ms, resolve 48 ms, geometry 92 ms, materials 0.1 ms, assemble 0.3, write 7 ms, verify 29 ms, start-up and exit 0.2. Simulation with STEP takes 1.0 s: read 69 ms, resolve 47 ms, geometry 99 ms, materials 0.1 ms, assemble 0.3, write 0.2, verify 30 ms, start-up and exit 0.2. Simulation with STL takes 0.8 s: read 71 ms, resolve 51 ms, geometry 93 ms, materials 0.1 ms, assemble 0.3, write 9 ms, verify 32 ms, start-up and exit 0.2. Simulation with OBJ takes 0.9 s: read 80 ms, resolve 46 ms, geometry 89 ms, materials 0.1 ms, assemble 0.3, write 0.2, verify 35 ms, start-up and exit 0.2. Visual with GLB takes 0.9 s: read 65 ms, resolve 47 ms, geometry 0.1, materials 0.1 ms, assemble 0.5, write 4 ms, verify 33 ms, start-up and exit 0.2. Visual with OBJ takes 0.9 s: read 68 ms, resolve 48 ms, geometry 93 ms, materials 0.1 ms, assemble 0.4, write 73 ms, verify 32 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 68 ms 48 ms 92 ms 0.1 ms 0.3 7 ms 29 ms 0.2 0.7
Simulation, STEP 69 ms 47 ms 99 ms 0.1 ms 0.3 0.2 30 ms 0.2 1.0
Simulation, STL 71 ms 51 ms 93 ms 0.1 ms 0.3 9 ms 32 ms 0.2 0.8
Simulation, OBJ 80 ms 46 ms 89 ms 0.1 ms 0.3 0.2 35 ms 0.2 0.9
Visual, GLB 65 ms 47 ms 0.1 0.1 ms 0.5 4 ms 33 ms 0.2 0.9
Visual, OBJ 68 ms 48 ms 93 ms 0.1 ms 0.4 73 ms 32 ms 0.2 0.9
Board featureTest/
06_padstacks.kicad_pcb
Outline 34 × 20 mm
Thickness 1.6 mm
Copper layers 4
Vias 3 through
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 948 kB 70 MB
STEP 2.6 MB 69 MB
STL 1.4 MB 68 MB
OBJ 2.6 MB 74 MB
Visual
GLB 481 kB 92 MB
OBJ 1.3 MB 93 MB

18.3.2 07 Pad Shapes

07 Pad shapes straight from above in visual mode 07 Pad shapes straight from below in visual mode, mirrored as KiCad flips the board

07 Pad shapes: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 40% to 66% of a run. Simulation with GLB takes 0.7 s: read 74 ms, resolve 40 ms, geometry 0.1, materials 0.1 ms, assemble 0.3, write 9 ms, verify 25 ms, start-up and exit 0.2. Simulation with STEP takes 1.0 s: read 77 ms, resolve 44 ms, geometry 0.1, materials 0.1 ms, assemble 0.3, write 0.3, verify 25 ms, start-up and exit 0.2. Simulation with STL takes 0.7 s: read 72 ms, resolve 41 ms, geometry 0.1, materials 0.1 ms, assemble 0.3, write 12 ms, verify 23 ms, start-up and exit 0.2. Simulation with OBJ takes 0.9 s: read 90 ms, resolve 37 ms, geometry 0.1, materials 0.1 ms, assemble 0.3, write 0.1, verify 22 ms, start-up and exit 0.2. Visual with GLB takes 1.0 s: read 73 ms, resolve 43 ms, geometry 0.1, materials 0.2 ms, assemble 0.5, write 5 ms, verify 41 ms, start-up and exit 0.2. Visual with OBJ takes 1.1 s: read 76 ms, resolve 37 ms, geometry 0.1, materials 0.1 ms, assemble 0.5, write 0.1, verify 50 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 74 ms 40 ms 0.1 0.1 ms 0.3 9 ms 25 ms 0.2 0.7
Simulation, STEP 77 ms 44 ms 0.1 0.1 ms 0.3 0.3 25 ms 0.2 1.0
Simulation, STL 72 ms 41 ms 0.1 0.1 ms 0.3 12 ms 23 ms 0.2 0.7
Simulation, OBJ 90 ms 37 ms 0.1 0.1 ms 0.3 0.1 22 ms 0.2 0.9
Visual, GLB 73 ms 43 ms 0.1 0.2 ms 0.5 5 ms 41 ms 0.2 1.0
Visual, OBJ 76 ms 37 ms 0.1 0.1 ms 0.5 0.1 50 ms 0.2 1.1
Board featureTest/
07_pad_shapes.kicad_pcb
Outline 44 × 30 mm
Thickness 1.6 mm
Copper layers 2
Vias none
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 842 kB 68 MB
STEP 3.7 MB 72 MB
STL 1.1 MB 69 MB
OBJ 2.2 MB 74 MB
Visual
GLB 729 kB 102 MB
OBJ 1.9 MB 102 MB

18.4 Copper Drawings, Text And Tracks

18.4.1 08 Copper Graphics

08 Copper graphics straight from above in visual mode 08 Copper graphics straight from below in visual mode, mirrored as KiCad flips the board

08 Copper graphics: stacked bars of seconds per stage, one format a run; reading, start-up and exit take 33% to 49% of a run. Simulation with GLB takes 0.6 s: read 85 ms, resolve 27 ms, geometry 43 ms, materials 0.1 ms, assemble 0.2, write 4 ms, verify 14 ms, start-up and exit 0.2. Simulation with STEP takes 0.8 s: read 71 ms, resolve 23 ms, geometry 38 ms, materials 0.1 ms, assemble 0.2, write 0.2, verify 13 ms, start-up and exit 0.2. Simulation with STL takes 0.6 s: read 73 ms, resolve 24 ms, geometry 38 ms, materials 0.1 ms, assemble 0.2, write 6 ms, verify 13 ms, start-up and exit 0.2. Simulation with OBJ takes 0.8 s: read 89 ms, resolve 25 ms, geometry 39 ms, materials 0.1 ms, assemble 0.3, write 0.1, verify 19 ms, start-up and exit 0.2. Visual with GLB takes 0.7 s: read 70 ms, resolve 23 ms, geometry 39 ms, materials 0.1 ms, assemble 0.3, write 4 ms, verify 40 ms, start-up and exit 0.2. Visual with OBJ takes 0.7 s: read 69 ms, resolve 25 ms, geometry 41 ms, materials 0.1 ms, assemble 0.3, write 96 ms, verify 51 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 85 ms 27 ms 43 ms 0.1 ms 0.2 4 ms 14 ms 0.2 0.6
Simulation, STEP 71 ms 23 ms 38 ms 0.1 ms 0.2 0.2 13 ms 0.2 0.8
Simulation, STL 73 ms 24 ms 38 ms 0.1 ms 0.2 6 ms 13 ms 0.2 0.6
Simulation, OBJ 89 ms 25 ms 39 ms 0.1 ms 0.3 0.1 19 ms 0.2 0.8
Visual, GLB 70 ms 23 ms 39 ms 0.1 ms 0.3 4 ms 40 ms 0.2 0.7
Visual, OBJ 69 ms 25 ms 41 ms 0.1 ms 0.3 96 ms 51 ms 0.2 0.7
Board featureTest/
08_copper_graphics.kicad_pcb
Outline 30 × 24 mm
Thickness 1.6 mm
Copper layers 2
Vias none
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 776 kB 72 MB
STEP 4.4 MB 74 MB
STL 1.2 MB 71 MB
OBJ 2.1 MB 75 MB
Visual
GLB 579 kB 100 MB
OBJ 1.5 MB 102 MB

18.4.2 08b Copper Graphics On Nets

08b Copper graphics on nets straight from above in visual mode 08b Copper graphics on nets straight from below in visual mode, mirrored as KiCad flips the board

08b Copper graphics on nets: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 41% to 60% of a run. Simulation with GLB takes 0.5 s: read 8 ms, resolve 23 ms, geometry 53 ms, materials 0.1 ms, assemble 0.2, write 6 ms, verify 18 ms, start-up and exit 0.2. Simulation with STEP takes 0.7 s: read 7 ms, resolve 31 ms, geometry 54 ms, materials 0.1 ms, assemble 0.2, write 0.2, verify 17 ms, start-up and exit 0.2. Simulation with STL takes 0.6 s: read 7 ms, resolve 28 ms, geometry 55 ms, materials 0.2 ms, assemble 0.3, write 11 ms, verify 21 ms, start-up and exit 0.2. Simulation with OBJ takes 0.6 s: read 7 ms, resolve 29 ms, geometry 60 ms, materials 0.1 ms, assemble 0.2, write 94 ms, verify 19 ms, start-up and exit 0.2. Visual with GLB takes 0.7 s: read 11 ms, resolve 32 ms, geometry 59 ms, materials 0.1 ms, assemble 0.4, write 4 ms, verify 42 ms, start-up and exit 0.2. Visual with OBJ takes 0.7 s: read 8 ms, resolve 24 ms, geometry 56 ms, materials 0.1 ms, assemble 0.3, write 69 ms, verify 38 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 8 ms 23 ms 53 ms 0.1 ms 0.2 6 ms 18 ms 0.2 0.5
Simulation, STEP 7 ms 31 ms 54 ms 0.1 ms 0.2 0.2 17 ms 0.2 0.7
Simulation, STL 7 ms 28 ms 55 ms 0.2 ms 0.3 11 ms 21 ms 0.2 0.6
Simulation, OBJ 7 ms 29 ms 60 ms 0.1 ms 0.2 94 ms 19 ms 0.2 0.6
Visual, GLB 11 ms 32 ms 59 ms 0.1 ms 0.4 4 ms 42 ms 0.2 0.7
Visual, OBJ 8 ms 24 ms 56 ms 0.1 ms 0.3 69 ms 38 ms 0.2 0.7
Board featureTest/
08b_copper_graphics_nets.kicad_pcb
Outline 36 × 24 mm, rounded corners
Thickness 1.6 mm
Copper layers 2
Vias none
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 615 kB 46 MB
STEP 3.3 MB 49 MB
STL 868 kB 47 MB
OBJ 1.6 MB 50 MB
Visual
GLB 474 kB 75 MB
OBJ 1.2 MB 77 MB

18.4.3 09 Copper Text

09 Copper text straight from above in visual mode 09 Copper text straight from below in visual mode, mirrored as KiCad flips the board

09 Copper text: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 44% to 76% of a run. Simulation with GLB takes 1.5 s: read 87 ms, resolve 41 ms, geometry 0.1, materials 0.1 ms, assemble 1.0, write 17 ms, verify 50 ms, start-up and exit 0.2. Simulation with STEP takes 2.5 s: read 85 ms, resolve 38 ms, geometry 0.1, materials 0.1 ms, assemble 1.0, write 1.0, verify 42 ms, start-up and exit 0.2. Simulation with STL takes 1.6 s: read 87 ms, resolve 38 ms, geometry 0.1, materials 0.1 ms, assemble 1.1, write 34 ms, verify 47 ms, start-up and exit 0.2. Simulation with OBJ takes 2.0 s: read 0.1, resolve 38 ms, geometry 0.1, materials 0.1 ms, assemble 1.0, write 0.5, verify 61 ms, start-up and exit 0.2. Visual with GLB takes 1.4 s: read 88 ms, resolve 38 ms, geometry 0.1, materials 0.1 ms, assemble 0.9, write 12 ms, verify 86 ms, start-up and exit 0.2. Visual with OBJ takes 1.9 s: read 87 ms, resolve 40 ms, geometry 0.1, materials 0.1 ms, assemble 0.9, write 0.4, verify 98 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 87 ms 41 ms 0.1 0.1 ms 1.0 17 ms 50 ms 0.2 1.5
Simulation, STEP 85 ms 38 ms 0.1 0.1 ms 1.0 1.0 42 ms 0.2 2.5
Simulation, STL 87 ms 38 ms 0.1 0.1 ms 1.1 34 ms 47 ms 0.2 1.6
Simulation, OBJ 0.1 38 ms 0.1 0.1 ms 1.0 0.5 61 ms 0.2 2.0
Visual, GLB 88 ms 38 ms 0.1 0.1 ms 0.9 12 ms 86 ms 0.2 1.4
Visual, OBJ 87 ms 40 ms 0.1 0.1 ms 0.9 0.4 98 ms 0.2 1.9
Board featureTest/
09_copper_text.kicad_pcb
Outline 44 × 40 mm
Thickness 1.6 mm
Copper layers 2
Vias none
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 3.2 MB 203 MB
STEP 18.9 MB 208 MB
STL 4.7 MB 203 MB
OBJ 8.7 MB 198 MB
Visual
GLB 2.2 MB 159 MB
OBJ 6.1 MB 158 MB

18.4.4 10 Tracks And Arcs

10 Tracks and arcs straight from above in visual mode 10 Tracks and arcs straight from below in visual mode, mirrored as KiCad flips the board

10 Tracks and arcs: stacked bars of seconds per stage, one format a run; reading, start-up and exit take 35% to 46% of a run. Simulation with GLB takes 0.6 s: read 71 ms, resolve 24 ms, geometry 37 ms, materials 0.1 ms, assemble 0.2, write 7 ms, verify 19 ms, start-up and exit 0.2. Simulation with STEP takes 0.8 s: read 74 ms, resolve 27 ms, geometry 36 ms, materials 0.1 ms, assemble 0.2, write 0.2, verify 16 ms, start-up and exit 0.2. Simulation with STL takes 0.6 s: read 69 ms, resolve 23 ms, geometry 38 ms, materials 0.1 ms, assemble 0.2, write 8 ms, verify 17 ms, start-up and exit 0.2. Simulation with OBJ takes 0.6 s: read 68 ms, resolve 24 ms, geometry 46 ms, materials 0.1 ms, assemble 0.2, write 83 ms, verify 16 ms, start-up and exit 0.2. Visual with GLB takes 0.7 s: read 86 ms, resolve 27 ms, geometry 37 ms, materials 0.1 ms, assemble 0.4, write 4 ms, verify 40 ms, start-up and exit 0.2. Visual with OBJ takes 0.8 s: read 71 ms, resolve 25 ms, geometry 38 ms, materials 0.1 ms, assemble 0.3, write 78 ms, verify 40 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 71 ms 24 ms 37 ms 0.1 ms 0.2 7 ms 19 ms 0.2 0.6
Simulation, STEP 74 ms 27 ms 36 ms 0.1 ms 0.2 0.2 16 ms 0.2 0.8
Simulation, STL 69 ms 23 ms 38 ms 0.1 ms 0.2 8 ms 17 ms 0.2 0.6
Simulation, OBJ 68 ms 24 ms 46 ms 0.1 ms 0.2 83 ms 16 ms 0.2 0.6
Visual, GLB 86 ms 27 ms 37 ms 0.1 ms 0.4 4 ms 40 ms 0.2 0.7
Visual, OBJ 71 ms 25 ms 38 ms 0.1 ms 0.3 78 ms 40 ms 0.2 0.8
Board featureTest/
10_tracks_arcs.kicad_pcb
Outline 44 × 24 mm
Thickness 1.6 mm
Copper layers 2
Vias none
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 560 kB 68 MB
STEP 2.5 MB 71 MB
STL 817 kB 68 MB
OBJ 1.4 MB 72 MB
Visual
GLB 521 kB 98 MB
OBJ 1.4 MB 99 MB

18.4.5 27 Hatched Fills

27 Hatched fills straight from above in visual mode 27 Hatched fills straight from below in visual mode, mirrored as KiCad flips the board

27 Hatched fills: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 49% to 71% of a run. Simulation with GLB takes 1.7 s: read 0.1, resolve 86 ms, geometry 0.2, materials 0.1 ms, assemble 1.0, write 11 ms, verify 54 ms, start-up and exit 0.2. Simulation with STEP takes 2.4 s: read 0.1, resolve 78 ms, geometry 0.2, materials 0.1 ms, assemble 1.0, write 0.8, verify 56 ms, start-up and exit 0.2. Simulation with STL takes 1.7 s: read 0.1, resolve 92 ms, geometry 0.2, materials 0.1 ms, assemble 1.0, write 19 ms, verify 51 ms, start-up and exit 0.2. Simulation with OBJ takes 1.9 s: read 0.1, resolve 85 ms, geometry 0.2, materials 0.1 ms, assemble 1.0, write 0.3, verify 61 ms, start-up and exit 0.2. Visual with GLB takes 1.5 s: read 0.1, resolve 84 ms, geometry 0.2, materials 0.1 ms, assemble 0.9, write 10 ms, verify 67 ms, start-up and exit 0.2. Visual with OBJ takes 1.8 s: read 0.1, resolve 92 ms, geometry 0.2, materials 0.1 ms, assemble 0.9, write 0.3, verify 66 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 86 ms 0.2 0.1 ms 1.0 11 ms 54 ms 0.2 1.7
Simulation, STEP 0.1 78 ms 0.2 0.1 ms 1.0 0.8 56 ms 0.2 2.4
Simulation, STL 0.1 92 ms 0.2 0.1 ms 1.0 19 ms 51 ms 0.2 1.7
Simulation, OBJ 0.1 85 ms 0.2 0.1 ms 1.0 0.3 61 ms 0.2 1.9
Visual, GLB 0.1 84 ms 0.2 0.1 ms 0.9 10 ms 67 ms 0.2 1.5
Visual, OBJ 0.1 92 ms 0.2 0.1 ms 0.9 0.3 66 ms 0.2 1.8
Board featureTest/
27_hatched_fills.kicad_pcb
Outline 64 × 44 mm
Thickness 1.6 mm
Copper layers 2
Vias none
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 2.0 MB 83 MB
STEP 13.6 MB 195 MB
STL 2.6 MB 82 MB
OBJ 5.4 MB 102 MB
Visual
GLB 1.7 MB 126 MB
OBJ 4.8 MB 126 MB

18.5 Zones

18.5.1 11 Zones

11 Zones straight from above in visual mode 11 Zones straight from below in visual mode, mirrored as KiCad flips the board

11 Zones: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 42% to 75% of a run. Simulation with GLB takes 1.5 s: read 0.1, resolve 0.1, geometry 0.4, materials 0.1 ms, assemble 0.6, write 19 ms, verify 80 ms, start-up and exit 0.2. Simulation with STEP takes 2.3 s: read 89 ms, resolve 0.1, geometry 0.4, materials 0.1 ms, assemble 0.6, write 0.8, verify 77 ms, start-up and exit 0.2. Simulation with STL takes 1.5 s: read 0.1, resolve 0.1, geometry 0.4, materials 0.1 ms, assemble 0.6, write 26 ms, verify 88 ms, start-up and exit 0.2. Simulation with OBJ takes 2.0 s: read 87 ms, resolve 0.1, geometry 0.4, materials 0.1 ms, assemble 0.6, write 0.6, verify 80 ms, start-up and exit 0.2. Visual with GLB takes 1.9 s: read 99 ms, resolve 0.1, geometry 0.3, materials 0.1 ms, assemble 1.1, write 13 ms, verify 72 ms, start-up and exit 0.2. Visual with OBJ takes 2.2 s: read 92 ms, resolve 0.1, geometry 0.3, materials 0.1 ms, assemble 1.1, write 0.3, verify 71 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.1 0.4 0.1 ms 0.6 19 ms 80 ms 0.2 1.5
Simulation, STEP 89 ms 0.1 0.4 0.1 ms 0.6 0.8 77 ms 0.2 2.3
Simulation, STL 0.1 0.1 0.4 0.1 ms 0.6 26 ms 88 ms 0.2 1.5
Simulation, OBJ 87 ms 0.1 0.4 0.1 ms 0.6 0.6 80 ms 0.2 2.0
Visual, GLB 99 ms 0.1 0.3 0.1 ms 1.1 13 ms 72 ms 0.2 1.9
Visual, OBJ 92 ms 0.1 0.3 0.1 ms 1.1 0.3 71 ms 0.2 2.2
Board featureTest/
11_zones.kicad_pcb
Outline 40 × 31 mm
Thickness 1.6 mm
Copper layers 4
Vias 1 through
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 3.4 MB 182 MB
STEP 13.6 MB 187 MB
STL 4.9 MB 181 MB
OBJ 9.5 MB 185 MB
Visual
GLB 1.8 MB 156 MB
OBJ 5.0 MB 155 MB

18.6 Board Outline

18.6.1 12 Board Outline Shapes

12 Board outline shapes straight from above in visual mode 12 Board outline shapes straight from below in visual mode, mirrored as KiCad flips the board

12 Board outline shapes: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 39% to 59% of a run. Simulation with GLB takes 0.8 s: read 80 ms, resolve 36 ms, geometry 70 ms, materials 0.1 ms, assemble 0.4, write 9 ms, verify 33 ms, start-up and exit 0.2. Simulation with STEP takes 1.2 s: read 79 ms, resolve 39 ms, geometry 77 ms, materials 0.1 ms, assemble 0.4, write 0.4, verify 32 ms, start-up and exit 0.2. Simulation with STL takes 0.8 s: read 83 ms, resolve 38 ms, geometry 77 ms, materials 0.1 ms, assemble 0.4, write 13 ms, verify 26 ms, start-up and exit 0.2. Simulation with OBJ takes 1.1 s: read 80 ms, resolve 40 ms, geometry 79 ms, materials 0.1 ms, assemble 0.4, write 0.2, verify 26 ms, start-up and exit 0.2. Visual with GLB takes 0.9 s: read 81 ms, resolve 37 ms, geometry 76 ms, materials 0.1 ms, assemble 0.5, write 9 ms, verify 58 ms, start-up and exit 0.2. Visual with OBJ takes 1.2 s: read 80 ms, resolve 37 ms, geometry 71 ms, materials 0.1 ms, assemble 0.5, write 0.3, verify 54 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 80 ms 36 ms 70 ms 0.1 ms 0.4 9 ms 33 ms 0.2 0.8
Simulation, STEP 79 ms 39 ms 77 ms 0.1 ms 0.4 0.4 32 ms 0.2 1.2
Simulation, STL 83 ms 38 ms 77 ms 0.1 ms 0.4 13 ms 26 ms 0.2 0.8
Simulation, OBJ 80 ms 40 ms 79 ms 0.1 ms 0.4 0.2 26 ms 0.2 1.1
Visual, GLB 81 ms 37 ms 76 ms 0.1 ms 0.5 9 ms 58 ms 0.2 0.9
Visual, OBJ 80 ms 37 ms 71 ms 0.1 ms 0.5 0.3 54 ms 0.2 1.2
Board featureTest/
12_outline_shapes.kicad_pcb
Outline 40 × 30.9 mm, arcs, a Bezier edge,
a notch and cut-outs
Thickness 1.6 mm
Copper layers 2
Vias none
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 1.6 MB 77 MB
STEP 10.8 MB 83 MB
STL 2.4 MB 78 MB
OBJ 4.5 MB 95 MB
Visual
GLB 1.5 MB 112 MB
OBJ 4.1 MB 114 MB

18.6.2 13a No Board Outline

13a No board outline straight from above in visual mode 13a No board outline straight from below in visual mode, mirrored as KiCad flips the board

13a No board outline: stacked bars of seconds per stage, one format a run; reading, start-up and exit take 42% to 53% of a run. Simulation with GLB takes 0.5 s: read 67 ms, resolve 27 ms, geometry 53 ms, materials 0.1 ms, assemble 0.1, write 4 ms, verify 15 ms, start-up and exit 0.2. Simulation with STEP takes 0.6 s: read 70 ms, resolve 26 ms, geometry 55 ms, materials 0.1 ms, assemble 0.1, write 0.1, verify 18 ms, start-up and exit 0.2. Simulation with STL takes 0.5 s: read 67 ms, resolve 25 ms, geometry 55 ms, materials 0.1 ms, assemble 0.1, write 6 ms, verify 17 ms, start-up and exit 0.2. Simulation with OBJ takes 0.6 s: read 65 ms, resolve 23 ms, geometry 53 ms, materials 0.1 ms, assemble 0.1, write 62 ms, verify 16 ms, start-up and exit 0.2. Visual with GLB takes 0.6 s: read 71 ms, resolve 24 ms, geometry 54 ms, materials 0.1 ms, assemble 0.2, write 4 ms, verify 64 ms, start-up and exit 0.2. Visual with OBJ takes 0.6 s: read 65 ms, resolve 24 ms, geometry 51 ms, materials 0.1 ms, assemble 0.2, write 38 ms, verify 45 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 67 ms 27 ms 53 ms 0.1 ms 0.1 4 ms 15 ms 0.2 0.5
Simulation, STEP 70 ms 26 ms 55 ms 0.1 ms 0.1 0.1 18 ms 0.2 0.6
Simulation, STL 67 ms 25 ms 55 ms 0.1 ms 0.1 6 ms 17 ms 0.2 0.5
Simulation, OBJ 65 ms 23 ms 53 ms 0.1 ms 0.1 62 ms 16 ms 0.2 0.6
Visual, GLB 71 ms 24 ms 54 ms 0.1 ms 0.2 4 ms 64 ms 0.2 0.6
Visual, OBJ 65 ms 24 ms 51 ms 0.1 ms 0.2 38 ms 45 ms 0.2 0.6
Board featureTest/
13a_outline_none.kicad_pcb
Outline 13.7 × 7.2 mm,
from the copper (no Edge.Cuts)
Thickness 1.6 mm
Copper layers 2
Vias 1 through
Board edge Plain
Mask, silkscreen, finish Mask colour not set (drawn green),
no silkscreen, ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 411 kB 68 MB
STEP 1.6 MB 66 MB
STL 621 kB 67 MB
OBJ 1.1 MB 68 MB
Visual
GLB 249 kB 105 MB
OBJ 630 kB 107 MB

18.6.3 13b Two Board Outlines

13b Two board outlines straight from above in visual mode 13b Two board outlines straight from below in visual mode, mirrored as KiCad flips the board

13b Two board outlines: stacked bars of seconds per stage, one format a run; reading, start-up and exit take 44% to 60% of a run. Simulation with GLB takes 0.5 s: read 68 ms, resolve 21 ms, geometry 39 ms, materials 0.1 ms, assemble 0.1, write 5 ms, verify 15 ms, start-up and exit 0.2. Simulation with STEP takes 0.6 s: read 73 ms, resolve 23 ms, geometry 47 ms, materials 0.1 ms, assemble 0.1, write 0.1, verify 15 ms, start-up and exit 0.2. Simulation with STL takes 0.5 s: read 68 ms, resolve 23 ms, geometry 41 ms, materials 0.1 ms, assemble 0.1, write 5 ms, verify 16 ms, start-up and exit 0.2. Simulation with OBJ takes 0.5 s: read 82 ms, resolve 29 ms, geometry 47 ms, materials 0.1 ms, assemble 0.1, write 39 ms, verify 18 ms, start-up and exit 0.2. Visual with GLB takes 0.6 s: read 72 ms, resolve 22 ms, geometry 51 ms, materials 0.1 ms, assemble 0.2, write 3 ms, verify 22 ms, start-up and exit 0.2. Visual with OBJ takes 0.6 s: read 68 ms, resolve 21 ms, geometry 48 ms, materials 0.1 ms, assemble 0.2, write 30 ms, verify 22 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 68 ms 21 ms 39 ms 0.1 ms 0.1 5 ms 15 ms 0.2 0.5
Simulation, STEP 73 ms 23 ms 47 ms 0.1 ms 0.1 0.1 15 ms 0.2 0.6
Simulation, STL 68 ms 23 ms 41 ms 0.1 ms 0.1 5 ms 16 ms 0.2 0.5
Simulation, OBJ 82 ms 29 ms 47 ms 0.1 ms 0.1 39 ms 18 ms 0.2 0.5
Visual, GLB 72 ms 22 ms 51 ms 0.1 ms 0.2 3 ms 22 ms 0.2 0.6
Visual, OBJ 68 ms 21 ms 48 ms 0.1 ms 0.2 30 ms 22 ms 0.2 0.6
Board featureTest/
13b_outline_two.kicad_pcb
Outline 40 × 20 mm,
two boards and a third in a hole
Thickness 1.6 mm
Copper layers 2
Vias none
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 247 kB 70 MB
STEP 1.0 MB 66 MB
STL 354 kB 68 MB
OBJ 627 kB 69 MB
Visual
GLB 165 kB 79 MB
OBJ 402 kB 80 MB

18.7 Stack-Up

18.7.1 14 Full Stack-Up

14 Full stack-up straight from above in visual mode 14 Full stack-up straight from below in visual mode, mirrored as KiCad flips the board

14 Full stack-up: stacked bars of seconds per stage, one format a run; reading, start-up and exit take 36% to 47% of a run. Simulation with GLB takes 0.5 s: read 68 ms, resolve 35 ms, geometry 72 ms, materials 0.1 ms, assemble 0.2, write 5 ms, verify 18 ms, start-up and exit 0.2. Simulation with STEP takes 0.7 s: read 72 ms, resolve 36 ms, geometry 68 ms, materials 0.1 ms, assemble 0.2, write 0.1, verify 18 ms, start-up and exit 0.2. Simulation with STL takes 0.5 s: read 67 ms, resolve 35 ms, geometry 66 ms, materials 0.1 ms, assemble 0.2, write 6 ms, verify 20 ms, start-up and exit 0.2. Simulation with OBJ takes 0.6 s: read 74 ms, resolve 38 ms, geometry 60 ms, materials 0.1 ms, assemble 0.2, write 68 ms, verify 21 ms, start-up and exit 0.2. Visual with GLB takes 0.8 s: read 69 ms, resolve 36 ms, geometry 72 ms, materials 0.1 ms, assemble 0.4, write 4 ms, verify 35 ms, start-up and exit 0.2. Visual with OBJ takes 0.7 s: read 86 ms, resolve 37 ms, geometry 62 ms, materials 0.1 ms, assemble 0.3, write 46 ms, verify 31 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 68 ms 35 ms 72 ms 0.1 ms 0.2 5 ms 18 ms 0.2 0.5
Simulation, STEP 72 ms 36 ms 68 ms 0.1 ms 0.2 0.1 18 ms 0.2 0.7
Simulation, STL 67 ms 35 ms 66 ms 0.1 ms 0.2 6 ms 20 ms 0.2 0.5
Simulation, OBJ 74 ms 38 ms 60 ms 0.1 ms 0.2 68 ms 21 ms 0.2 0.6
Visual, GLB 69 ms 36 ms 72 ms 0.1 ms 0.4 4 ms 35 ms 0.2 0.8
Visual, OBJ 86 ms 37 ms 62 ms 0.1 ms 0.3 46 ms 31 ms 0.2 0.7
Board featureTest/
14_stackup_full.kicad_pcb
Outline 30 × 20 mm
Thickness 1.58 mm
Copper layers 4
Vias 1 through
Board edge Plain
Mask, silkscreen, finish Green, white, ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 433 kB 66 MB
STEP 1.4 MB 67 MB
STL 639 kB 69 MB
OBJ 1.2 MB 69 MB
Visual
GLB 281 kB 89 MB
OBJ 711 kB 90 MB

18.7.2 15 No Stack-Up

15 No stack-up straight from above in visual mode 15 No stack-up straight from below in visual mode, mirrored as KiCad flips the board

15 No stack-up: stacked bars of seconds per stage, one format a run; reading, start-up and exit take 38% to 53% of a run. Simulation with GLB takes 0.5 s: read 75 ms, resolve 34 ms, geometry 61 ms, materials 0.1 ms, assemble 0.1, write 4 ms, verify 18 ms, start-up and exit 0.2. Simulation with STEP takes 0.7 s: read 65 ms, resolve 31 ms, geometry 56 ms, materials 0.1 ms, assemble 0.2, write 0.1, verify 18 ms, start-up and exit 0.2. Simulation with STL takes 0.5 s: read 73 ms, resolve 31 ms, geometry 62 ms, materials 0.1 ms, assemble 0.1, write 5 ms, verify 17 ms, start-up and exit 0.2. Simulation with OBJ takes 0.6 s: read 69 ms, resolve 29 ms, geometry 55 ms, materials 0.1 ms, assemble 0.1, write 59 ms, verify 20 ms, start-up and exit 0.2. Visual with GLB takes 0.7 s: read 64 ms, resolve 30 ms, geometry 52 ms, materials 0.1 ms, assemble 0.3, write 4 ms, verify 32 ms, start-up and exit 0.2. Visual with OBJ takes 0.7 s: read 64 ms, resolve 27 ms, geometry 53 ms, materials 0.1 ms, assemble 0.3, write 32 ms, verify 27 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 75 ms 34 ms 61 ms 0.1 ms 0.1 4 ms 18 ms 0.2 0.5
Simulation, STEP 65 ms 31 ms 56 ms 0.1 ms 0.2 0.1 18 ms 0.2 0.7
Simulation, STL 73 ms 31 ms 62 ms 0.1 ms 0.1 5 ms 17 ms 0.2 0.5
Simulation, OBJ 69 ms 29 ms 55 ms 0.1 ms 0.1 59 ms 20 ms 0.2 0.6
Visual, GLB 64 ms 30 ms 52 ms 0.1 ms 0.3 4 ms 32 ms 0.2 0.7
Visual, OBJ 64 ms 27 ms 53 ms 0.1 ms 0.3 32 ms 27 ms 0.2 0.7
Board featureTest/
15_stackup_none.kicad_pcb
Outline 30 × 20 mm
Thickness 1.2 mm
Copper layers 4
Vias 1 through
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 353 kB 67 MB
STEP 1.0 MB 68 MB
STL 537 kB 70 MB
OBJ 949 kB 68 MB
Visual
GLB 203 kB 84 MB
OBJ 501 kB 85 MB

18.8 Edge Plating

18.8.1 16 Castellated Pads And A Plated Edge

16 Castellated pads and a plated edge straight from above in visual mode 16 Castellated pads and a plated edge straight from below in visual mode, mirrored as KiCad flips the board

16 Castellated pads and a plated edge: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 36% to 50% of a run. Simulation with GLB takes 0.6 s: read 71 ms, resolve 70 ms, geometry 95 ms, materials 0.1 ms, assemble 0.2, write 4 ms, verify 20 ms, start-up and exit 0.2. Simulation with STEP takes 0.8 s: read 72 ms, resolve 70 ms, geometry 0.1, materials 0.1 ms, assemble 0.2, write 0.1, verify 19 ms, start-up and exit 0.2. Simulation with STL takes 0.7 s: read 70 ms, resolve 73 ms, geometry 0.1, materials 0.1 ms, assemble 0.2, write 6 ms, verify 19 ms, start-up and exit 0.2. Simulation with OBJ takes 0.7 s: read 73 ms, resolve 72 ms, geometry 92 ms, materials 0.1 ms, assemble 0.2, write 81 ms, verify 20 ms, start-up and exit 0.2. Visual with GLB takes 0.7 s: read 68 ms, resolve 71 ms, geometry 89 ms, materials 0.1 ms, assemble 0.3, write 4 ms, verify 34 ms, start-up and exit 0.2. Visual with OBJ takes 0.8 s: read 69 ms, resolve 70 ms, geometry 96 ms, materials 0.1 ms, assemble 0.3, write 51 ms, verify 31 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 71 ms 70 ms 95 ms 0.1 ms 0.2 4 ms 20 ms 0.2 0.6
Simulation, STEP 72 ms 70 ms 0.1 0.1 ms 0.2 0.1 19 ms 0.2 0.8
Simulation, STL 70 ms 73 ms 0.1 0.1 ms 0.2 6 ms 19 ms 0.2 0.7
Simulation, OBJ 73 ms 72 ms 92 ms 0.1 ms 0.2 81 ms 20 ms 0.2 0.7
Visual, GLB 68 ms 71 ms 89 ms 0.1 ms 0.3 4 ms 34 ms 0.2 0.7
Visual, OBJ 69 ms 70 ms 96 ms 0.1 ms 0.3 51 ms 31 ms 0.2 0.8
Board featureTest/
16_edge_plating_castellation.kicad_pcb
Outline 30 × 20 mm
Thickness 1.6 mm
Copper layers 2
Vias none
Board edge Castellated pads on the right edge,
plated edge
Mask, silkscreen, finish Not set (drawn green and white),
immersion silver
File
type		 File
size		 Peak memory
used
Simulation
GLB 500 kB 65 MB
STEP 2.6 MB 70 MB
STL 718 kB 68 MB
OBJ 1.3 MB 69 MB
Visual
GLB 337 kB 91 MB
OBJ 848 kB 92 MB

18.8.2 16b Plated Board Edge With A GND Border

16b Plated board edge with a GND border straight from above in visual mode 16b Plated board edge with a GND border straight from below in visual mode, mirrored as KiCad flips the board

16b Plated board edge with a GND border: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 55% to 88% of a run. Simulation with GLB takes 5.6 s: read 0.1, resolve 0.5, geometry 2.2, materials 0.2 ms, assemble 2.2, write 67 ms, verify 0.3, start-up and exit 0.2. Simulation with STEP takes 6.6 s: read 0.1, resolve 0.4, geometry 2.2, materials 0.1 ms, assemble 2.2, write 1.3, verify 0.2, start-up and exit 0.2. Simulation with STL takes 5.5 s: read 0.1, resolve 0.5, geometry 2.2, materials 0.2 ms, assemble 2.2, write 0.1, verify 0.3, start-up and exit 0.2. Simulation with OBJ takes 8.1 s: read 0.1, resolve 0.5, geometry 2.1, materials 0.2 ms, assemble 2.3, write 2.6, verify 0.3, start-up and exit 0.2. Visual with GLB takes 7.6 s: read 99 ms, resolve 0.5, geometry 2.2, materials 0.2 ms, assemble 4.5, write 23 ms, verify 0.2, start-up and exit 0.2. Visual with OBJ takes 8.6 s: read 0.1, resolve 0.5, geometry 2.3, materials 0.2 ms, assemble 4.5, write 0.9, verify 0.1, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.1 0.5 2.2 0.2 ms 2.2 67 ms 0.3 0.2 5.6
Simulation, STEP 0.1 0.4 2.2 0.1 ms 2.2 1.3 0.2 0.2 6.6
Simulation, STL 0.1 0.5 2.2 0.2 ms 2.2 0.1 0.3 0.2 5.5
Simulation, OBJ 0.1 0.5 2.1 0.2 ms 2.3 2.6 0.3 0.2 8.1
Visual, GLB 99 ms 0.5 2.2 0.2 ms 4.5 23 ms 0.2 0.2 7.6
Visual, OBJ 0.1 0.5 2.3 0.2 ms 4.5 0.9 0.1 0.2 8.6
Board featureTest/
16b_edge_plating_border.kicad_pcb
Outline 40 × 28 mm, a cut-out
Thickness 1.6 mm
Copper layers 4
Vias 91 through
Board edge Plated all round
and in the cut-out
Mask, silkscreen, finish Green, white, ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 14.8 MB 287 MB
STEP 54.3 MB 328 MB
STL 22.1 MB 286 MB
OBJ 43.6 MB 347 MB
Visual
GLB 4.5 MB 247 MB
OBJ 13.1 MB 247 MB

18.8.3 28 Machining At A Plated Edge

28 Machining at a plated edge straight from above in visual mode 28 Machining at a plated edge straight from below in visual mode, mirrored as KiCad flips the board

28 Machining at a plated edge: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 61% to 76% of a run. Simulation with GLB takes 1.3 s: read 70 ms, resolve 69 ms, geometry 0.3, materials 0.1 ms, assemble 0.6, write 6 ms, verify 42 ms, start-up and exit 0.2. Simulation with STEP takes 1.5 s: read 66 ms, resolve 70 ms, geometry 0.3, materials 0.1 ms, assemble 0.6, write 0.2, verify 40 ms, start-up and exit 0.2. Simulation with STL takes 1.3 s: read 72 ms, resolve 75 ms, geometry 0.3, materials 0.1 ms, assemble 0.6, write 9 ms, verify 39 ms, start-up and exit 0.2. Simulation with OBJ takes 1.4 s: read 68 ms, resolve 74 ms, geometry 0.3, materials 0.1 ms, assemble 0.6, write 0.1, verify 47 ms, start-up and exit 0.2. Visual with GLB takes 1.5 s: read 67 ms, resolve 69 ms, geometry 0.3, materials 0.1 ms, assemble 0.9, write 7 ms, verify 38 ms, start-up and exit 0.2. Visual with OBJ takes 1.6 s: read 78 ms, resolve 75 ms, geometry 0.3, materials 0.2 ms, assemble 0.9, write 76 ms, verify 35 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 70 ms 69 ms 0.3 0.1 ms 0.6 6 ms 42 ms 0.2 1.3
Simulation, STEP 66 ms 70 ms 0.3 0.1 ms 0.6 0.2 40 ms 0.2 1.5
Simulation, STL 72 ms 75 ms 0.3 0.1 ms 0.6 9 ms 39 ms 0.2 1.3
Simulation, OBJ 68 ms 74 ms 0.3 0.1 ms 0.6 0.1 47 ms 0.2 1.4
Visual, GLB 67 ms 69 ms 0.3 0.1 ms 0.9 7 ms 38 ms 0.2 1.5
Visual, OBJ 78 ms 75 ms 0.3 0.2 ms 0.9 76 ms 35 ms 0.2 1.6
Board featureTest/
28_plated_edge_machining.kicad_pcb
Outline 40 × 24 mm
Thickness 1.6 mm
Copper layers 4
Vias 3: 2 blind and buried, 1 through
Board edge Plated all round,
cut by machining between two heights
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 926 kB 69 MB
STEP 5.1 MB 71 MB
STL 1.4 MB 69 MB
OBJ 2.5 MB 74 MB
Visual
GLB 504 kB 96 MB
OBJ 1.3 MB 97 MB

18.9 Solder Mask And Silkscreen

18.9.1 17 Solder Mask And Silkscreen

17 Solder mask and silkscreen straight from above in visual mode 17 Solder mask and silkscreen straight from below in visual mode, mirrored as KiCad flips the board

17 Solder mask and silkscreen: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 37% to 52% of a run. Simulation with GLB takes 0.6 s: read 74 ms, resolve 72 ms, geometry 0.1, materials 0.1 ms, assemble 0.2, write 5 ms, verify 16 ms, start-up and exit 0.2. Simulation with STEP takes 0.8 s: read 73 ms, resolve 62 ms, geometry 98 ms, materials 0.1 ms, assemble 0.2, write 0.2, verify 20 ms, start-up and exit 0.2. Simulation with STL takes 0.7 s: read 77 ms, resolve 71 ms, geometry 0.1, materials 0.1 ms, assemble 0.2, write 7 ms, verify 17 ms, start-up and exit 0.2. Simulation with OBJ takes 0.8 s: read 82 ms, resolve 67 ms, geometry 0.1, materials 0.1 ms, assemble 0.2, write 0.1, verify 17 ms, start-up and exit 0.2. Visual with GLB takes 0.8 s: read 98 ms, resolve 78 ms, geometry 0.1, materials 0.1 ms, assemble 0.3, write 5 ms, verify 38 ms, start-up and exit 0.2. Visual with OBJ takes 1.0 s: read 80 ms, resolve 65 ms, geometry 0.1, materials 0.1 ms, assemble 0.3, write 0.1, verify 47 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 74 ms 72 ms 0.1 0.1 ms 0.2 5 ms 16 ms 0.2 0.6
Simulation, STEP 73 ms 62 ms 98 ms 0.1 ms 0.2 0.2 20 ms 0.2 0.8
Simulation, STL 77 ms 71 ms 0.1 0.1 ms 0.2 7 ms 17 ms 0.2 0.7
Simulation, OBJ 82 ms 67 ms 0.1 0.1 ms 0.2 0.1 17 ms 0.2 0.8
Visual, GLB 98 ms 78 ms 0.1 0.1 ms 0.3 5 ms 38 ms 0.2 0.8
Visual, OBJ 80 ms 65 ms 0.1 0.1 ms 0.3 0.1 47 ms 0.2 1.0
Board featureTest/
17_mask_silk.kicad_pcb
Outline 40 × 30 mm
Thickness 1.6 mm
Copper layers 2
Vias 1 through
Board edge Plain
Mask, silkscreen, finish Red, black, lead-free HASL
File
type		 File
size		 Peak memory
used
Simulation
GLB 645 kB 67 MB
STEP 2.0 MB 68 MB
STL 880 kB 69 MB
OBJ 1.7 MB 71 MB
Visual
GLB 561 kB 95 MB
OBJ 1.5 MB 95 MB

18.9.2 17b Silkscreen Over Copper

17b Silkscreen over copper straight from above in visual mode 17b Silkscreen over copper straight from below in visual mode, mirrored as KiCad flips the board

17b Silkscreen over copper: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 43% to 65% of a run. Simulation with GLB takes 0.7 s: read 82 ms, resolve 36 ms, geometry 0.1, materials 0.1 ms, assemble 0.2, write 5 ms, verify 24 ms, start-up and exit 0.2. Simulation with STEP takes 0.9 s: read 69 ms, resolve 33 ms, geometry 0.2, materials 0.1 ms, assemble 0.2, write 0.2, verify 26 ms, start-up and exit 0.2. Simulation with STL takes 0.8 s: read 76 ms, resolve 35 ms, geometry 0.1, materials 0.1 ms, assemble 0.3, write 8 ms, verify 26 ms, start-up and exit 0.2. Simulation with OBJ takes 0.8 s: read 70 ms, resolve 32 ms, geometry 0.2, materials 0.1 ms, assemble 0.3, write 0.1, verify 23 ms, start-up and exit 0.2. Visual with GLB takes 0.9 s: read 70 ms, resolve 31 ms, geometry 0.2, materials 0.1 ms, assemble 0.4, write 4 ms, verify 39 ms, start-up and exit 0.2. Visual with OBJ takes 1.0 s: read 71 ms, resolve 32 ms, geometry 0.2, materials 0.1 ms, assemble 0.4, write 80 ms, verify 32 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 82 ms 36 ms 0.1 0.1 ms 0.2 5 ms 24 ms 0.2 0.7
Simulation, STEP 69 ms 33 ms 0.2 0.1 ms 0.2 0.2 26 ms 0.2 0.9
Simulation, STL 76 ms 35 ms 0.1 0.1 ms 0.3 8 ms 26 ms 0.2 0.8
Simulation, OBJ 70 ms 32 ms 0.2 0.1 ms 0.3 0.1 23 ms 0.2 0.8
Visual, GLB 70 ms 31 ms 0.2 0.1 ms 0.4 4 ms 39 ms 0.2 0.9
Visual, OBJ 71 ms 32 ms 0.2 0.1 ms 0.4 80 ms 32 ms 0.2 1.0
Board featureTest/
17b_silk_over_copper.kicad_pcb
Outline 30 × 20 mm
Thickness 1.6 mm
Copper layers 2
Vias none
Board edge Plain
Mask, silkscreen, finish White, black, ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 589 kB 68 MB
STEP 3.0 MB 69 MB
STL 804 kB 69 MB
OBJ 1.6 MB 70 MB
Visual
GLB 513 kB 90 MB
OBJ 1.3 MB 91 MB

18.10 Surface Finish

18.10.1 18 Gold Edge Fingers

18 Gold edge fingers straight from above in visual mode 18 Gold edge fingers straight from below in visual mode, mirrored as KiCad flips the board

18 Gold edge fingers: stacked bars of seconds per stage, one format a run; reading, start-up and exit take 35% to 46% of a run. Simulation with GLB takes 0.6 s: read 79 ms, resolve 35 ms, geometry 55 ms, materials 0.1 ms, assemble 0.2, write 5 ms, verify 19 ms, start-up and exit 0.2. Simulation with STEP takes 0.7 s: read 67 ms, resolve 38 ms, geometry 49 ms, materials 0.1 ms, assemble 0.2, write 0.1, verify 17 ms, start-up and exit 0.2. Simulation with STL takes 0.6 s: read 69 ms, resolve 36 ms, geometry 49 ms, materials 0.1 ms, assemble 0.2, write 6 ms, verify 18 ms, start-up and exit 0.2. Simulation with OBJ takes 0.6 s: read 68 ms, resolve 34 ms, geometry 55 ms, materials 0.1 ms, assemble 0.2, write 88 ms, verify 17 ms, start-up and exit 0.2. Visual with GLB takes 0.7 s: read 70 ms, resolve 35 ms, geometry 48 ms, materials 0.1 ms, assemble 0.3, write 5 ms, verify 51 ms, start-up and exit 0.2. Visual with OBJ takes 0.8 s: read 86 ms, resolve 35 ms, geometry 46 ms, materials 0.1 ms, assemble 0.3, write 77 ms, verify 49 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 79 ms 35 ms 55 ms 0.1 ms 0.2 5 ms 19 ms 0.2 0.6
Simulation, STEP 67 ms 38 ms 49 ms 0.1 ms 0.2 0.1 17 ms 0.2 0.7
Simulation, STL 69 ms 36 ms 49 ms 0.1 ms 0.2 6 ms 18 ms 0.2 0.6
Simulation, OBJ 68 ms 34 ms 55 ms 0.1 ms 0.2 88 ms 17 ms 0.2 0.6
Visual, GLB 70 ms 35 ms 48 ms 0.1 ms 0.3 5 ms 51 ms 0.2 0.7
Visual, OBJ 86 ms 35 ms 46 ms 0.1 ms 0.3 77 ms 49 ms 0.2 0.8
Board featureTest/
18_finishes.kicad_pcb
Outline 30 × 16 mm
Thickness 1.6 mm
Copper layers 2
Vias 6 through
Board edge Gold edge fingers
on a bevelled edge
Mask, silkscreen, finish Not set (drawn green and white),
hard gold
File
type		 File
size		 Peak memory
used
Simulation
GLB 500 kB 69 MB
STEP 2.0 MB 67 MB
STL 776 kB 65 MB
OBJ 1.4 MB 70 MB
Visual
GLB 482 kB 104 MB
OBJ 1.3 MB 105 MB

18.10.2 18b Finish On Every Kind Of Bare Copper

18b Finish on every kind of bare copper straight from above in visual mode 18b Finish on every kind of bare copper straight from below in visual mode, mirrored as KiCad flips the board

18b Finish on every kind of bare copper: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 42% to 61% of a run. Simulation with GLB takes 0.7 s: read 68 ms, resolve 36 ms, geometry 0.1, materials 0.1 ms, assemble 0.3, write 8 ms, verify 24 ms, start-up and exit 0.2. Simulation with STEP takes 0.9 s: read 73 ms, resolve 43 ms, geometry 0.1, materials 0.2 ms, assemble 0.3, write 0.2, verify 22 ms, start-up and exit 0.2. Simulation with STL takes 0.7 s: read 75 ms, resolve 43 ms, geometry 0.1, materials 0.1 ms, assemble 0.2, write 8 ms, verify 26 ms, start-up and exit 0.2. Simulation with OBJ takes 0.8 s: read 70 ms, resolve 35 ms, geometry 0.1, materials 0.1 ms, assemble 0.2, write 0.1, verify 23 ms, start-up and exit 0.2. Visual with GLB takes 0.8 s: read 69 ms, resolve 36 ms, geometry 0.1, materials 0.2 ms, assemble 0.4, write 4 ms, verify 40 ms, start-up and exit 0.2. Visual with OBJ takes 0.8 s: read 69 ms, resolve 33 ms, geometry 94 ms, materials 0.2 ms, assemble 0.4, write 65 ms, verify 33 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 68 ms 36 ms 0.1 0.1 ms 0.3 8 ms 24 ms 0.2 0.7
Simulation, STEP 73 ms 43 ms 0.1 0.2 ms 0.3 0.2 22 ms 0.2 0.9
Simulation, STL 75 ms 43 ms 0.1 0.1 ms 0.2 8 ms 26 ms 0.2 0.7
Simulation, OBJ 70 ms 35 ms 0.1 0.1 ms 0.2 0.1 23 ms 0.2 0.8
Visual, GLB 69 ms 36 ms 0.1 0.2 ms 0.4 4 ms 40 ms 0.2 0.8
Visual, OBJ 69 ms 33 ms 94 ms 0.2 ms 0.4 65 ms 33 ms 0.2 0.8
Board featureTest/
18b_finish_pads.kicad_pcb
Outline 30 × 20 mm
Thickness 1.6 mm
Copper layers 2
Vias 1 through
Board edge Plain
Mask, silkscreen, finish Green, white, ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 635 kB 67 MB
STEP 2.4 MB 69 MB
STL 872 kB 67 MB
OBJ 1.7 MB 70 MB
Visual
GLB 415 kB 93 MB
OBJ 1.1 MB 95 MB

18.10.3 18c Finish Before The Solder Mask

18c Finish before the solder mask straight from above in visual mode 18c Finish before the solder mask straight from below in visual mode, mirrored as KiCad flips the board

18c Finish before the solder mask: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 46% to 69% of a run. Simulation with GLB takes 0.9 s: read 70 ms, resolve 32 ms, geometry 0.2, materials 0.2 ms, assemble 0.5, write 9 ms, verify 36 ms, start-up and exit 0.2. Simulation with STEP takes 1.3 s: read 74 ms, resolve 33 ms, geometry 0.2, materials 0.1 ms, assemble 0.5, write 0.4, verify 43 ms, start-up and exit 0.2. Simulation with STL takes 1.0 s: read 71 ms, resolve 37 ms, geometry 0.2, materials 0.1 ms, assemble 0.5, write 12 ms, verify 34 ms, start-up and exit 0.2. Simulation with OBJ takes 1.2 s: read 74 ms, resolve 35 ms, geometry 0.2, materials 0.1 ms, assemble 0.5, write 0.2, verify 38 ms, start-up and exit 0.2. Visual with GLB takes 1.1 s: read 70 ms, resolve 34 ms, geometry 0.2, materials 0.1 ms, assemble 0.6, write 6 ms, verify 36 ms, start-up and exit 0.2. Visual with OBJ takes 1.2 s: read 68 ms, resolve 35 ms, geometry 0.2, materials 0.2 ms, assemble 0.6, write 80 ms, verify 37 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 70 ms 32 ms 0.2 0.2 ms 0.5 9 ms 36 ms 0.2 0.9
Simulation, STEP 74 ms 33 ms 0.2 0.1 ms 0.5 0.4 43 ms 0.2 1.3
Simulation, STL 71 ms 37 ms 0.2 0.1 ms 0.5 12 ms 34 ms 0.2 1.0
Simulation, OBJ 74 ms 35 ms 0.2 0.1 ms 0.5 0.2 38 ms 0.2 1.2
Visual, GLB 70 ms 34 ms 0.2 0.1 ms 0.6 6 ms 36 ms 0.2 1.1
Visual, OBJ 68 ms 35 ms 0.2 0.2 ms 0.6 80 ms 37 ms 0.2 1.2
Board featureTest/
18c_finish_before_mask.kicad_pcb
Outline 30 × 20 mm
Thickness 1.6 mm
Copper layers 2
Vias 1 through
Board edge Plain
Mask, silkscreen, finish Blue, white, ENEPIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 1.2 MB 69 MB
STEP 6.5 MB 71 MB
STL 1.7 MB 70 MB
OBJ 3.3 MB 80 MB
Visual
GLB 546 kB 93 MB
OBJ 1.4 MB 95 MB

18.11 Items KESE Skips

18.11.1 19 Items KESE Skips

19 Items KESE skips straight from above in visual mode 19 Items KESE skips straight from below in visual mode, mirrored as KiCad flips the board

19 Items KESE skips: stacked bars of seconds per stage, one format a run; reading, start-up and exit take 55% to 74% of a run. Simulation with GLB takes 0.4 s: read 72 ms, resolve 17 ms, geometry 20 ms, materials 0.1 ms, assemble 67 ms, write 4 ms, verify 8 ms, start-up and exit 0.2. Simulation with STEP takes 0.4 s: read 67 ms, resolve 17 ms, geometry 22 ms, materials 0.1 ms, assemble 43 ms, write 42 ms, verify 7 ms, start-up and exit 0.2. Simulation with STL takes 0.3 s: read 65 ms, resolve 17 ms, geometry 19 ms, materials 0.1 ms, assemble 43 ms, write 3 ms, verify 6 ms, start-up and exit 0.2. Simulation with OBJ takes 0.4 s: read 74 ms, resolve 18 ms, geometry 21 ms, materials 0.1 ms, assemble 46 ms, write 16 ms, verify 7 ms, start-up and exit 0.2. Visual with GLB takes 0.4 s: read 66 ms, resolve 16 ms, geometry 21 ms, materials 0.1 ms, assemble 0.1, write 2 ms, verify 18 ms, start-up and exit 0.2. Visual with OBJ takes 0.4 s: read 65 ms, resolve 17 ms, geometry 21 ms, materials 0.1 ms, assemble 0.1, write 26 ms, verify 19 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 72 ms 17 ms 20 ms 0.1 ms 67 ms 4 ms 8 ms 0.2 0.4
Simulation, STEP 67 ms 17 ms 22 ms 0.1 ms 43 ms 42 ms 7 ms 0.2 0.4
Simulation, STL 65 ms 17 ms 19 ms 0.1 ms 43 ms 3 ms 6 ms 0.2 0.3
Simulation, OBJ 74 ms 18 ms 21 ms 0.1 ms 46 ms 16 ms 7 ms 0.2 0.4
Visual, GLB 66 ms 16 ms 21 ms 0.1 ms 0.1 2 ms 18 ms 0.2 0.4
Visual, OBJ 65 ms 17 ms 21 ms 0.1 ms 0.1 26 ms 19 ms 0.2 0.4
Board featureTest/
19_skipped_items.kicad_pcb
Outline 40 × 30 mm
Thickness 1.6 mm
Copper layers 2
Vias none
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 104 kB 67 MB
STEP 510 kB 64 MB
STL 132 kB 67 MB
OBJ 244 kB 67 MB
Visual
GLB 105 kB 76 MB
OBJ 249 kB 77 MB

18.11.2 19b Items KESE Skips, KiCad 10

19b Items KESE skips, KiCad 10 straight from above in visual mode 19b Items KESE skips, KiCad 10 straight from below in visual mode, mirrored as KiCad flips the board

19b Items KESE skips, KiCad 10: stacked bars of seconds per stage, one format a run; reading, start-up and exit take 76% to 84% of a run. Simulation with GLB takes 0.2 s: read 0.7 ms, resolve 6 ms, geometry 10 ms, materials 0.0 ms, assemble 15 ms, write 1 ms, verify 1 ms, start-up and exit 0.2. Simulation with STEP takes 0.2 s: read 0.8 ms, resolve 4 ms, geometry 11 ms, materials 0.1 ms, assemble 19 ms, write 6 ms, verify 2 ms, start-up and exit 0.2. Simulation with STL takes 0.2 s: read 0.8 ms, resolve 6 ms, geometry 7 ms, materials 0.0 ms, assemble 15 ms, write 1 ms, verify 5 ms, start-up and exit 0.2. Simulation with OBJ takes 0.2 s: read 0.8 ms, resolve 7 ms, geometry 8 ms, materials 0.0 ms, assemble 15 ms, write 1 ms, verify 1 ms, start-up and exit 0.2. Visual with GLB takes 0.2 s: read 0.9 ms, resolve 4 ms, geometry 15 ms, materials 0.0 ms, assemble 26 ms, write 1 ms, verify 11 ms, start-up and exit 0.2. Visual with OBJ takes 0.2 s: read 0.9 ms, resolve 4 ms, geometry 8 ms, materials 0.0 ms, assemble 34 ms, write 1 ms, verify 11 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.7 ms 6 ms 10 ms 0.0 ms 15 ms 1 ms 1 ms 0.2 0.2
Simulation, STEP 0.8 ms 4 ms 11 ms 0.1 ms 19 ms 6 ms 2 ms 0.2 0.2
Simulation, STL 0.8 ms 6 ms 7 ms 0.0 ms 15 ms 1 ms 5 ms 0.2 0.2
Simulation, OBJ 0.8 ms 7 ms 8 ms 0.0 ms 15 ms 1 ms 1 ms 0.2 0.2
Visual, GLB 0.9 ms 4 ms 15 ms 0.0 ms 26 ms 1 ms 11 ms 0.2 0.2
Visual, OBJ 0.9 ms 4 ms 8 ms 0.0 ms 34 ms 1 ms 11 ms 0.2 0.2
Board featureTest/
19b_skipped_items_k10.kicad_pcb
Outline 40 × 24 mm
Thickness 1.6 mm
Copper layers 2
Vias none
Board edge Plain
Mask, silkscreen, finish Mask colour not set (drawn green),
no silkscreen, ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 4 kB 40 MB
STEP 19 kB 40 MB
STL 2 kB 40 MB
OBJ 5 kB 40 MB
Visual
GLB 5 kB 46 MB
OBJ 5 kB 45 MB

18.12 KiCad File Formats

18.12.1 20a KiCad 6 Format

20a KiCad 6 format straight from above in visual mode 20a KiCad 6 format straight from below in visual mode, mirrored as KiCad flips the board

20a KiCad 6 format: stacked bars of seconds per stage, one format a run; reading, start-up and exit take 36% to 48% of a run. Simulation with GLB takes 0.5 s: read 65 ms, resolve 29 ms, geometry 61 ms, materials 0.1 ms, assemble 0.1, write 4 ms, verify 17 ms, start-up and exit 0.2. Simulation with STEP takes 0.6 s: read 66 ms, resolve 25 ms, geometry 60 ms, materials 0.1 ms, assemble 0.2, write 0.2, verify 18 ms, start-up and exit 0.2. Simulation with STL takes 0.5 s: read 66 ms, resolve 27 ms, geometry 62 ms, materials 0.1 ms, assemble 0.2, write 7 ms, verify 19 ms, start-up and exit 0.2. Simulation with OBJ takes 0.6 s: read 67 ms, resolve 26 ms, geometry 66 ms, materials 0.1 ms, assemble 0.2, write 79 ms, verify 18 ms, start-up and exit 0.2. Visual with GLB takes 0.7 s: read 71 ms, resolve 27 ms, geometry 65 ms, materials 0.1 ms, assemble 0.3, write 4 ms, verify 35 ms, start-up and exit 0.2. Visual with OBJ takes 0.7 s: read 80 ms, resolve 29 ms, geometry 62 ms, materials 0.1 ms, assemble 0.3, write 62 ms, verify 29 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 65 ms 29 ms 61 ms 0.1 ms 0.1 4 ms 17 ms 0.2 0.5
Simulation, STEP 66 ms 25 ms 60 ms 0.1 ms 0.2 0.2 18 ms 0.2 0.6
Simulation, STL 66 ms 27 ms 62 ms 0.1 ms 0.2 7 ms 19 ms 0.2 0.5
Simulation, OBJ 67 ms 26 ms 66 ms 0.1 ms 0.2 79 ms 18 ms 0.2 0.6
Visual, GLB 71 ms 27 ms 65 ms 0.1 ms 0.3 4 ms 35 ms 0.2 0.7
Visual, OBJ 80 ms 29 ms 62 ms 0.1 ms 0.3 62 ms 29 ms 0.2 0.7
Board featureTest/
20a_format_kicad6.kicad_pcb
Outline 24 × 16 mm
Thickness 1.6 mm
Copper layers 2
Vias 1 through
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 512 kB 67 MB
STEP 2.3 MB 68 MB
STL 746 kB 65 MB
OBJ 1.3 MB 70 MB
Visual
GLB 413 kB 88 MB
OBJ 1.1 MB 89 MB

18.12.2 20b KiCad 7 Format

20b KiCad 7 format straight from above in visual mode 20b KiCad 7 format straight from below in visual mode, mirrored as KiCad flips the board

20b KiCad 7 format: stacked bars of seconds per stage, one format a run; reading, start-up and exit take 35% to 49% of a run. Simulation with GLB takes 0.6 s: read 74 ms, resolve 28 ms, geometry 71 ms, materials 0.1 ms, assemble 0.2, write 5 ms, verify 18 ms, start-up and exit 0.2. Simulation with STEP takes 0.7 s: read 78 ms, resolve 31 ms, geometry 65 ms, materials 0.1 ms, assemble 0.2, write 0.2, verify 19 ms, start-up and exit 0.2. Simulation with STL takes 0.5 s: read 69 ms, resolve 28 ms, geometry 61 ms, materials 0.1 ms, assemble 0.2, write 6 ms, verify 16 ms, start-up and exit 0.2. Simulation with OBJ takes 0.6 s: read 69 ms, resolve 31 ms, geometry 72 ms, materials 0.1 ms, assemble 0.2, write 77 ms, verify 17 ms, start-up and exit 0.2. Visual with GLB takes 0.7 s: read 77 ms, resolve 31 ms, geometry 70 ms, materials 0.1 ms, assemble 0.3, write 5 ms, verify 33 ms, start-up and exit 0.2. Visual with OBJ takes 0.7 s: read 70 ms, resolve 28 ms, geometry 73 ms, materials 0.1 ms, assemble 0.3, write 60 ms, verify 29 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 74 ms 28 ms 71 ms 0.1 ms 0.2 5 ms 18 ms 0.2 0.6
Simulation, STEP 78 ms 31 ms 65 ms 0.1 ms 0.2 0.2 19 ms 0.2 0.7
Simulation, STL 69 ms 28 ms 61 ms 0.1 ms 0.2 6 ms 16 ms 0.2 0.5
Simulation, OBJ 69 ms 31 ms 72 ms 0.1 ms 0.2 77 ms 17 ms 0.2 0.6
Visual, GLB 77 ms 31 ms 70 ms 0.1 ms 0.3 5 ms 33 ms 0.2 0.7
Visual, OBJ 70 ms 28 ms 73 ms 0.1 ms 0.3 60 ms 29 ms 0.2 0.7
Board featureTest/
20b_format_kicad7.kicad_pcb
Outline 24 × 16 mm
Thickness 1.6 mm
Copper layers 2
Vias 1 through
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 506 kB 68 MB
STEP 2.2 MB 68 MB
STL 738 kB 70 MB
OBJ 1.3 MB 70 MB
Visual
GLB 406 kB 87 MB
OBJ 1.0 MB 89 MB

18.12.3 20c KiCad 8 Format

20c KiCad 8 format straight from above in visual mode 20c KiCad 8 format straight from below in visual mode, mirrored as KiCad flips the board

20c KiCad 8 format: stacked bars of seconds per stage, one format a run; reading, start-up and exit take 35% to 50% of a run. Simulation with GLB takes 0.5 s: read 72 ms, resolve 30 ms, geometry 66 ms, materials 0.1 ms, assemble 0.2, write 5 ms, verify 19 ms, start-up and exit 0.2. Simulation with STEP takes 0.7 s: read 73 ms, resolve 27 ms, geometry 59 ms, materials 0.1 ms, assemble 0.2, write 0.2, verify 20 ms, start-up and exit 0.2. Simulation with STL takes 0.6 s: read 82 ms, resolve 28 ms, geometry 68 ms, materials 0.1 ms, assemble 0.2, write 6 ms, verify 17 ms, start-up and exit 0.2. Simulation with OBJ takes 0.6 s: read 70 ms, resolve 28 ms, geometry 72 ms, materials 0.1 ms, assemble 0.2, write 77 ms, verify 17 ms, start-up and exit 0.2. Visual with GLB takes 0.7 s: read 69 ms, resolve 28 ms, geometry 72 ms, materials 0.1 ms, assemble 0.3, write 4 ms, verify 35 ms, start-up and exit 0.2. Visual with OBJ takes 0.7 s: read 71 ms, resolve 30 ms, geometry 65 ms, materials 0.1 ms, assemble 0.3, write 63 ms, verify 32 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 72 ms 30 ms 66 ms 0.1 ms 0.2 5 ms 19 ms 0.2 0.5
Simulation, STEP 73 ms 27 ms 59 ms 0.1 ms 0.2 0.2 20 ms 0.2 0.7
Simulation, STL 82 ms 28 ms 68 ms 0.1 ms 0.2 6 ms 17 ms 0.2 0.6
Simulation, OBJ 70 ms 28 ms 72 ms 0.1 ms 0.2 77 ms 17 ms 0.2 0.6
Visual, GLB 69 ms 28 ms 72 ms 0.1 ms 0.3 4 ms 35 ms 0.2 0.7
Visual, OBJ 71 ms 30 ms 65 ms 0.1 ms 0.3 63 ms 32 ms 0.2 0.7
Board featureTest/
20c_format_kicad8.kicad_pcb
Outline 24 × 16 mm
Thickness 1.6 mm
Copper layers 2
Vias 1 through
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 515 kB 67 MB
STEP 2.3 MB 67 MB
STL 749 kB 67 MB
OBJ 1.4 MB 69 MB
Visual
GLB 415 kB 87 MB
OBJ 1.1 MB 89 MB

18.12.4 20d KiCad 9 Format

20d KiCad 9 format straight from above in visual mode 20d KiCad 9 format straight from below in visual mode, mirrored as KiCad flips the board

20d KiCad 9 format: stacked bars of seconds per stage, one format a run; reading, start-up and exit take 35% to 51% of a run. Simulation with GLB takes 0.6 s: read 75 ms, resolve 29 ms, geometry 68 ms, materials 0.1 ms, assemble 0.2, write 5 ms, verify 17 ms, start-up and exit 0.2. Simulation with STEP takes 0.7 s: read 67 ms, resolve 33 ms, geometry 66 ms, materials 0.1 ms, assemble 0.2, write 0.2, verify 17 ms, start-up and exit 0.2. Simulation with STL takes 0.5 s: read 69 ms, resolve 34 ms, geometry 64 ms, materials 0.1 ms, assemble 0.2, write 7 ms, verify 16 ms, start-up and exit 0.2. Simulation with OBJ takes 0.6 s: read 70 ms, resolve 29 ms, geometry 67 ms, materials 0.1 ms, assemble 0.2, write 74 ms, verify 19 ms, start-up and exit 0.2. Visual with GLB takes 0.7 s: read 68 ms, resolve 28 ms, geometry 71 ms, materials 0.1 ms, assemble 0.3, write 4 ms, verify 30 ms, start-up and exit 0.2. Visual with OBJ takes 0.7 s: read 67 ms, resolve 27 ms, geometry 69 ms, materials 0.1 ms, assemble 0.3, write 59 ms, verify 31 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 75 ms 29 ms 68 ms 0.1 ms 0.2 5 ms 17 ms 0.2 0.6
Simulation, STEP 67 ms 33 ms 66 ms 0.1 ms 0.2 0.2 17 ms 0.2 0.7
Simulation, STL 69 ms 34 ms 64 ms 0.1 ms 0.2 7 ms 16 ms 0.2 0.5
Simulation, OBJ 70 ms 29 ms 67 ms 0.1 ms 0.2 74 ms 19 ms 0.2 0.6
Visual, GLB 68 ms 28 ms 71 ms 0.1 ms 0.3 4 ms 30 ms 0.2 0.7
Visual, OBJ 67 ms 27 ms 69 ms 0.1 ms 0.3 59 ms 31 ms 0.2 0.7
Board featureTest/
20d_format_kicad9.kicad_pcb
Outline 24 × 16 mm
Thickness 1.6 mm
Copper layers 2
Vias 1 through
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 512 kB 65 MB
STEP 2.3 MB 67 MB
STL 746 kB 69 MB
OBJ 1.3 MB 70 MB
Visual
GLB 413 kB 88 MB
OBJ 1.1 MB 89 MB

18.12.5 20e KiCad 10 Format

20e KiCad 10 format straight from above in visual mode 20e KiCad 10 format straight from below in visual mode, mirrored as KiCad flips the board

20e KiCad 10 format: stacked bars of seconds per stage, one format a run; reading, start-up and exit take 36% to 49% of a run. Simulation with GLB takes 0.5 s: read 76 ms, resolve 28 ms, geometry 62 ms, materials 0.1 ms, assemble 0.2, write 5 ms, verify 17 ms, start-up and exit 0.2. Simulation with STEP takes 0.7 s: read 70 ms, resolve 36 ms, geometry 73 ms, materials 0.1 ms, assemble 0.2, write 0.1, verify 17 ms, start-up and exit 0.2. Simulation with STL takes 0.5 s: read 73 ms, resolve 32 ms, geometry 63 ms, materials 0.1 ms, assemble 0.2, write 7 ms, verify 17 ms, start-up and exit 0.2. Simulation with OBJ takes 0.6 s: read 68 ms, resolve 27 ms, geometry 64 ms, materials 0.1 ms, assemble 0.2, write 93 ms, verify 21 ms, start-up and exit 0.2. Visual with GLB takes 0.7 s: read 70 ms, resolve 27 ms, geometry 64 ms, materials 0.1 ms, assemble 0.3, write 4 ms, verify 32 ms, start-up and exit 0.2. Visual with OBJ takes 0.8 s: read 69 ms, resolve 29 ms, geometry 68 ms, materials 0.1 ms, assemble 0.3, write 60 ms, verify 31 ms, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 76 ms 28 ms 62 ms 0.1 ms 0.2 5 ms 17 ms 0.2 0.5
Simulation, STEP 70 ms 36 ms 73 ms 0.1 ms 0.2 0.1 17 ms 0.2 0.7
Simulation, STL 73 ms 32 ms 63 ms 0.1 ms 0.2 7 ms 17 ms 0.2 0.5
Simulation, OBJ 68 ms 27 ms 64 ms 0.1 ms 0.2 93 ms 21 ms 0.2 0.6
Visual, GLB 70 ms 27 ms 64 ms 0.1 ms 0.3 4 ms 32 ms 0.2 0.7
Visual, OBJ 69 ms 29 ms 68 ms 0.1 ms 0.3 60 ms 31 ms 0.2 0.8
Board featureTest/
20e_format_kicad10.kicad_pcb
Outline 24 × 16 mm
Thickness 1.6 mm
Copper layers 2
Vias 1 through
Board edge Plain
Mask, silkscreen, finish Not set (drawn green and white),
ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 517 kB 69 MB
STEP 2.3 MB 68 MB
STL 753 kB 65 MB
OBJ 1.4 MB 70 MB
Visual
GLB 418 kB 87 MB
OBJ 1.1 MB 89 MB

18.13 Example Boards

18.13.1 21 RF Sensor Module

21 RF sensor module straight from above in visual mode 21 RF sensor module straight from below in visual mode, mirrored as KiCad flips the board

21 RF sensor module: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 53% to 85% of a run. Simulation with GLB takes 15.7 s: read 0.2, resolve 1.6, geometry 7.2, materials 0.4 ms, assemble 5.5, write 0.3, verify 0.6, start-up and exit 0.2. Simulation with STEP takes 18.9 s: read 0.3, resolve 1.9, geometry 7.2, materials 0.4 ms, assemble 5.6, write 3.1, verify 0.6, start-up and exit 0.3. Simulation with STL takes 15.2 s: read 0.3, resolve 1.7, geometry 6.8, materials 0.4 ms, assemble 5.3, write 0.4, verify 0.5, start-up and exit 0.2. Simulation with OBJ takes 23.4 s: read 0.3, resolve 1.8, geometry 6.8, materials 0.5 ms, assemble 5.5, write 8.3, verify 0.6, start-up and exit 0.2. Visual with GLB takes 19.1 s: read 0.3, resolve 1.7, geometry 6.8, materials 0.4 ms, assemble 9.5, write 94 ms, verify 0.6, start-up and exit 0.2. Visual with OBJ takes 23.1 s: read 0.2, resolve 1.6, geometry 6.7, materials 0.5 ms, assemble 9.8, write 3.8, verify 0.8, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 1.6 7.2 0.4 ms 5.5 0.3 0.6 0.2 15.7
Simulation, STEP 0.3 1.9 7.2 0.4 ms 5.6 3.1 0.6 0.3 18.9
Simulation, STL 0.3 1.7 6.8 0.4 ms 5.3 0.4 0.5 0.2 15.2
Simulation, OBJ 0.3 1.8 6.8 0.5 ms 5.5 8.3 0.6 0.2 23.4
Visual, GLB 0.3 1.7 6.8 0.4 ms 9.5 94 ms 0.6 0.2 19.1
Visual, OBJ 0.2 1.6 6.7 0.5 ms 9.8 3.8 0.8 0.2 23.1
Board featureTest/
21_rf_module.kicad_pcb
(5.1)
Outline 64 × 44 mm, a cut-out
Thickness 1.6 mm
Copper layers 4
Vias 307 through
Board edge Plated all round
and in the cut-out
Mask, silkscreen, finish Blue, white, ENIG
File
type		 File
size		 Peak memory
used
Simulation
GLB 47.2 MB 548 MB
STEP 171.2 MB 643 MB
STL 69.4 MB 539 MB
OBJ 142.2 MB 971 MB
Visual
GLB 21.6 MB 592 MB
OBJ 65.1 MB 579 MB

18.13.2 22 HDI Radio Module

22 HDI radio module straight from above in visual mode 22 HDI radio module straight from below in visual mode, mirrored as KiCad flips the board

22 HDI radio module: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 45% to 77% of a run. Simulation with GLB takes 6.7 s: read 0.2, resolve 1.1, geometry 2.5, materials 0.4 ms, assemble 2.0, write 0.1, verify 0.5, start-up and exit 0.3. Simulation with STEP takes 8.1 s: read 0.2, resolve 1.1, geometry 2.4, materials 0.4 ms, assemble 2.0, write 1.7, verify 0.5, start-up and exit 0.2. Simulation with STL takes 6.6 s: read 0.2, resolve 1.0, geometry 2.6, materials 0.4 ms, assemble 2.0, write 0.2, verify 0.4, start-up and exit 0.2. Simulation with OBJ takes 9.9 s: read 0.2, resolve 1.0, geometry 2.5, materials 0.3 ms, assemble 2.0, write 3.5, verify 0.5, start-up and exit 0.2. Visual with GLB takes 8.5 s: read 0.2, resolve 1.0, geometry 2.6, materials 0.4 ms, assemble 4.0, write 66 ms, verify 0.4, start-up and exit 0.2. Visual with OBJ takes 10.3 s: read 0.2, resolve 1.0, geometry 2.7, materials 0.4 ms, assemble 4.1, write 1.7, verify 0.4, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.2 1.1 2.5 0.4 ms 2.0 0.1 0.5 0.3 6.7
Simulation, STEP 0.2 1.1 2.4 0.4 ms 2.0 1.7 0.5 0.2 8.1
Simulation, STL 0.2 1.0 2.6 0.4 ms 2.0 0.2 0.4 0.2 6.6
Simulation, OBJ 0.2 1.0 2.5 0.3 ms 2.0 3.5 0.5 0.2 9.9
Visual, GLB 0.2 1.0 2.6 0.4 ms 4.0 66 ms 0.4 0.2 8.5
Visual, OBJ 0.2 1.0 2.7 0.4 ms 4.1 1.7 0.4 0.2 10.3
Board featureTest/
22_hdi_module.kicad_pcb
(5.2)
Outline 22 × 30 mm
Thickness 0.925 mm
Copper layers 6
Vias 150: 71 micro,
34 blind and buried, 45 through
Board edge 43 castellated pads
Mask, silkscreen, finish Black, white, immersion silver
File
type		 File
size		 Peak memory
used
Simulation
GLB 21.0 MB 350 MB
STEP 70.9 MB 357 MB
STL 30.5 MB 340 MB
OBJ 62.8 MB 459 MB
Visual
GLB 10.6 MB 303 MB
OBJ 32.1 MB 319 MB

18.13.3 23 PCIe x1 Card

23 PCIe x1 card straight from above in visual mode 23 PCIe x1 card straight from below in visual mode, mirrored as KiCad flips the board

23 PCIe x1 card: stacked bars of seconds per stage, one format a run; stages 4 and 6 take 44% to 82% of a run. Simulation with GLB takes 10.0 s: read 0.3, resolve 1.2, geometry 3.8, materials 0.5 ms, assemble 3.7, write 0.2, verify 0.6, start-up and exit 0.2. Simulation with STEP takes 12.9 s: read 0.3, resolve 1.2, geometry 3.9, materials 0.4 ms, assemble 3.8, write 3.0, verify 0.6, start-up and exit 0.2. Simulation with STL takes 9.7 s: read 0.3, resolve 1.1, geometry 3.9, materials 0.4 ms, assemble 3.4, write 0.3, verify 0.5, start-up and exit 0.2. Simulation with OBJ takes 16.5 s: read 0.3, resolve 1.2, geometry 3.7, materials 0.4 ms, assemble 3.5, write 7.1, verify 0.5, start-up and exit 0.2. Visual with GLB takes 13.9 s: read 0.3, resolve 1.1, geometry 3.8, materials 0.5 ms, assemble 7.6, write 0.1, verify 0.8, start-up and exit 0.2. Visual with OBJ takes 17.7 s: read 0.3, resolve 1.3, geometry 3.8, materials 0.6 ms, assemble 7.4, write 3.9, verify 0.8, start-up and exit 0.2

Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
Simulation, GLB 0.3 1.2 3.8 0.5 ms 3.7 0.2 0.6 0.2 10.0
Simulation, STEP 0.3 1.2 3.9 0.4 ms 3.8 3.0 0.6 0.2 12.9
Simulation, STL 0.3 1.1 3.9 0.4 ms 3.4 0.3 0.5 0.2 9.7
Simulation, OBJ 0.3 1.2 3.7 0.4 ms 3.5 7.1 0.5 0.2 16.5
Visual, GLB 0.3 1.1 3.8 0.5 ms 7.6 0.1 0.8 0.2 13.9
Visual, OBJ 0.3 1.3 3.8 0.6 ms 7.4 3.9 0.8 0.2 17.7
Board featureTest/
23_pcie_card.kicad_pcb
(5.3)
Outline 80 × 64.4 mm with the fingers' tongue,
a slot
Thickness 1.57 mm
Copper layers 4
Vias 239 through
Board edge 36 gold fingers on
a bevelled tongue
Mask, silkscreen, finish Green, white, hard gold
File
type		 File
size		 Peak memory
used
Simulation
GLB 41.1 MB 530 MB
STEP 130.5 MB 559 MB
STL 60.2 MB 507 MB
OBJ 122.2 MB 833 MB
Visual
GLB 22.5 MB 540 MB
OBJ 67.7 MB 578 MB

18.14 The Numbers

Seconds, the median of three runs for each stage, unless marked ms; the total is the sum of the bars.

Board Mode and format 1–2 read 3 resolve 4 geometry 5 materials 6 assemble 7 write 8 verify start-up and exit Total
01 Slotted holes simulation, GLB 70 ms 56 ms 0.2 0.2 ms 0.3 8 ms 41 ms 0.2 0.9
01 Slotted holes simulation, STEP 74 ms 55 ms 0.2 0.1 ms 0.4 0.4 36 ms 0.2 1.3
01 Slotted holes simulation, STL 69 ms 51 ms 0.2 0.1 ms 0.4 11 ms 40 ms 0.2 0.9
01 Slotted holes simulation, OBJ 74 ms 53 ms 0.2 0.1 ms 0.4 0.2 41 ms 0.2 1.2
01 Slotted holes visual, GLB 83 ms 56 ms 0.2 0.1 ms 0.5 7 ms 40 ms 0.2 1.1
01 Slotted holes visual, OBJ 68 ms 53 ms 0.2 0.2 ms 0.5 0.1 40 ms 0.2 1.2
02 Round holes simulation, GLB 76 ms 45 ms 0.2 0.1 ms 0.4 8 ms 34 ms 0.2 0.9
02 Round holes simulation, STEP 73 ms 46 ms 0.2 0.1 ms 0.4 0.3 31 ms 0.2 1.2
02 Round holes simulation, STL 67 ms 42 ms 0.2 0.1 ms 0.4 12 ms 31 ms 0.2 0.9
02 Round holes simulation, OBJ 72 ms 49 ms 0.2 0.1 ms 0.4 0.2 31 ms 0.2 1.1
02 Round holes visual, GLB 71 ms 46 ms 0.2 0.1 ms 0.4 6 ms 42 ms 0.2 1.0
02 Round holes visual, OBJ 66 ms 39 ms 0.2 0.1 ms 0.4 0.1 43 ms 0.2 1.1
03 Through vias simulation, GLB 67 ms 51 ms 0.2 0.1 ms 0.5 11 ms 44 ms 0.2 1.2
03 Through vias simulation, STEP 71 ms 58 ms 0.2 0.1 ms 0.6 0.3 49 ms 0.2 1.6
03 Through vias simulation, STL 67 ms 51 ms 0.2 0.1 ms 0.6 20 ms 48 ms 0.2 1.2
03 Through vias simulation, OBJ 66 ms 55 ms 0.2 0.1 ms 0.6 0.3 55 ms 0.2 1.5
03 Through vias visual, GLB 67 ms 55 ms 0.2 0.1 ms 0.6 6 ms 67 ms 0.2 1.2
03 Through vias visual, OBJ 82 ms 60 ms 0.2 0.1 ms 0.6 0.1 60 ms 0.2 1.3
03b KiCad 10 via options simulation, GLB 69 ms 0.1 0.3 0.1 ms 0.7 16 ms 0.1 0.2 1.5
03b KiCad 10 via options simulation, STEP 80 ms 0.2 0.3 0.1 ms 0.6 0.7 0.1 0.2 2.2
03b KiCad 10 via options simulation, STL 76 ms 0.1 0.3 0.2 ms 0.6 25 ms 97 ms 0.2 1.4
03b KiCad 10 via options simulation, OBJ 75 ms 0.1 0.3 0.2 ms 0.6 0.4 94 ms 0.2 1.8
03b KiCad 10 via options visual, GLB 92 ms 0.2 0.3 0.1 ms 2.4 14 ms 90 ms 0.2 3.2
03b KiCad 10 via options visual, OBJ 74 ms 0.2 0.3 0.1 ms 2.4 0.3 78 ms 0.2 3.5
04 Blind and buried vias simulation, GLB 73 ms 51 ms 62 ms 0.1 ms 0.2 5 ms 26 ms 0.2 0.7
04 Blind and buried vias simulation, STEP 68 ms 50 ms 59 ms 0.1 ms 0.2 0.2 22 ms 0.2 0.8
04 Blind and buried vias simulation, STL 68 ms 51 ms 59 ms 0.1 ms 0.2 8 ms 21 ms 0.2 0.6
04 Blind and buried vias simulation, OBJ 66 ms 55 ms 62 ms 0.1 ms 0.2 0.1 22 ms 0.2 0.7
04 Blind and buried vias visual, GLB 70 ms 54 ms 59 ms 0.1 ms 0.4 5 ms 37 ms 0.2 0.8
04 Blind and buried vias visual, OBJ 69 ms 53 ms 63 ms 0.1 ms 0.4 47 ms 32 ms 0.2 0.8
05 Microvias simulation, GLB 3 ms 54 ms 61 ms 0.1 ms 0.2 5 ms 21 ms 0.2 0.6
05 Microvias simulation, STEP 3 ms 55 ms 49 ms 0.1 ms 0.2 0.1 20 ms 0.2 0.6
05 Microvias simulation, STL 3 ms 50 ms 57 ms 0.1 ms 0.2 6 ms 25 ms 0.2 0.6
05 Microvias simulation, OBJ 3 ms 58 ms 49 ms 0.1 ms 0.2 97 ms 22 ms 0.2 0.6
05 Microvias visual, GLB 4 ms 60 ms 52 ms 0.1 ms 0.3 3 ms 49 ms 0.2 0.7
05 Microvias visual, OBJ 3 ms 59 ms 55 ms 0.1 ms 0.3 30 ms 49 ms 0.2 0.7
06 Padstacks simulation, GLB 68 ms 48 ms 92 ms 0.1 ms 0.3 7 ms 29 ms 0.2 0.7
06 Padstacks simulation, STEP 69 ms 47 ms 99 ms 0.1 ms 0.3 0.2 30 ms 0.2 1.0
06 Padstacks simulation, STL 71 ms 51 ms 93 ms 0.1 ms 0.3 9 ms 32 ms 0.2 0.8
06 Padstacks simulation, OBJ 80 ms 46 ms 89 ms 0.1 ms 0.3 0.2 35 ms 0.2 0.9
06 Padstacks visual, GLB 65 ms 47 ms 0.1 0.1 ms 0.5 4 ms 33 ms 0.2 0.9
06 Padstacks visual, OBJ 68 ms 48 ms 93 ms 0.1 ms 0.4 73 ms 32 ms 0.2 0.9
07 Pad shapes simulation, GLB 74 ms 40 ms 0.1 0.1 ms 0.3 9 ms 25 ms 0.2 0.7
07 Pad shapes simulation, STEP 77 ms 44 ms 0.1 0.1 ms 0.3 0.3 25 ms 0.2 1.0
07 Pad shapes simulation, STL 72 ms 41 ms 0.1 0.1 ms 0.3 12 ms 23 ms 0.2 0.7
07 Pad shapes simulation, OBJ 90 ms 37 ms 0.1 0.1 ms 0.3 0.1 22 ms 0.2 0.9
07 Pad shapes visual, GLB 73 ms 43 ms 0.1 0.2 ms 0.5 5 ms 41 ms 0.2 1.0
07 Pad shapes visual, OBJ 76 ms 37 ms 0.1 0.1 ms 0.5 0.1 50 ms 0.2 1.1
08 Copper graphics simulation, GLB 85 ms 27 ms 43 ms 0.1 ms 0.2 4 ms 14 ms 0.2 0.6
08 Copper graphics simulation, STEP 71 ms 23 ms 38 ms 0.1 ms 0.2 0.2 13 ms 0.2 0.8
08 Copper graphics simulation, STL 73 ms 24 ms 38 ms 0.1 ms 0.2 6 ms 13 ms 0.2 0.6
08 Copper graphics simulation, OBJ 89 ms 25 ms 39 ms 0.1 ms 0.3 0.1 19 ms 0.2 0.8
08 Copper graphics visual, GLB 70 ms 23 ms 39 ms 0.1 ms 0.3 4 ms 40 ms 0.2 0.7
08 Copper graphics visual, OBJ 69 ms 25 ms 41 ms 0.1 ms 0.3 96 ms 51 ms 0.2 0.7
08b Copper graphics on nets simulation, GLB 8 ms 23 ms 53 ms 0.1 ms 0.2 6 ms 18 ms 0.2 0.5
08b Copper graphics on nets simulation, STEP 7 ms 31 ms 54 ms 0.1 ms 0.2 0.2 17 ms 0.2 0.7
08b Copper graphics on nets simulation, STL 7 ms 28 ms 55 ms 0.2 ms 0.3 11 ms 21 ms 0.2 0.6
08b Copper graphics on nets simulation, OBJ 7 ms 29 ms 60 ms 0.1 ms 0.2 94 ms 19 ms 0.2 0.6
08b Copper graphics on nets visual, GLB 11 ms 32 ms 59 ms 0.1 ms 0.4 4 ms 42 ms 0.2 0.7
08b Copper graphics on nets visual, OBJ 8 ms 24 ms 56 ms 0.1 ms 0.3 69 ms 38 ms 0.2 0.7
09 Copper text simulation, GLB 87 ms 41 ms 0.1 0.1 ms 1.0 17 ms 50 ms 0.2 1.5
09 Copper text simulation, STEP 85 ms 38 ms 0.1 0.1 ms 1.0 1.0 42 ms 0.2 2.5
09 Copper text simulation, STL 87 ms 38 ms 0.1 0.1 ms 1.1 34 ms 47 ms 0.2 1.6
09 Copper text simulation, OBJ 0.1 38 ms 0.1 0.1 ms 1.0 0.5 61 ms 0.2 2.0
09 Copper text visual, GLB 88 ms 38 ms 0.1 0.1 ms 0.9 12 ms 86 ms 0.2 1.4
09 Copper text visual, OBJ 87 ms 40 ms 0.1 0.1 ms 0.9 0.4 98 ms 0.2 1.9
10 Tracks and arcs simulation, GLB 71 ms 24 ms 37 ms 0.1 ms 0.2 7 ms 19 ms 0.2 0.6
10 Tracks and arcs simulation, STEP 74 ms 27 ms 36 ms 0.1 ms 0.2 0.2 16 ms 0.2 0.8
10 Tracks and arcs simulation, STL 69 ms 23 ms 38 ms 0.1 ms 0.2 8 ms 17 ms 0.2 0.6
10 Tracks and arcs simulation, OBJ 68 ms 24 ms 46 ms 0.1 ms 0.2 83 ms 16 ms 0.2 0.6
10 Tracks and arcs visual, GLB 86 ms 27 ms 37 ms 0.1 ms 0.4 4 ms 40 ms 0.2 0.7
10 Tracks and arcs visual, OBJ 71 ms 25 ms 38 ms 0.1 ms 0.3 78 ms 40 ms 0.2 0.8
11 Zones simulation, GLB 0.1 0.1 0.4 0.1 ms 0.6 19 ms 80 ms 0.2 1.5
11 Zones simulation, STEP 89 ms 0.1 0.4 0.1 ms 0.6 0.8 77 ms 0.2 2.3
11 Zones simulation, STL 0.1 0.1 0.4 0.1 ms 0.6 26 ms 88 ms 0.2 1.5
11 Zones simulation, OBJ 87 ms 0.1 0.4 0.1 ms 0.6 0.6 80 ms 0.2 2.0
11 Zones visual, GLB 99 ms 0.1 0.3 0.1 ms 1.1 13 ms 72 ms 0.2 1.9
11 Zones visual, OBJ 92 ms 0.1 0.3 0.1 ms 1.1 0.3 71 ms 0.2 2.2
12 Board outline shapes simulation, GLB 80 ms 36 ms 70 ms 0.1 ms 0.4 9 ms 33 ms 0.2 0.8
12 Board outline shapes simulation, STEP 79 ms 39 ms 77 ms 0.1 ms 0.4 0.4 32 ms 0.2 1.2
12 Board outline shapes simulation, STL 83 ms 38 ms 77 ms 0.1 ms 0.4 13 ms 26 ms 0.2 0.8
12 Board outline shapes simulation, OBJ 80 ms 40 ms 79 ms 0.1 ms 0.4 0.2 26 ms 0.2 1.1
12 Board outline shapes visual, GLB 81 ms 37 ms 76 ms 0.1 ms 0.5 9 ms 58 ms 0.2 0.9
12 Board outline shapes visual, OBJ 80 ms 37 ms 71 ms 0.1 ms 0.5 0.3 54 ms 0.2 1.2
13a No board outline simulation, GLB 67 ms 27 ms 53 ms 0.1 ms 0.1 4 ms 15 ms 0.2 0.5
13a No board outline simulation, STEP 70 ms 26 ms 55 ms 0.1 ms 0.1 0.1 18 ms 0.2 0.6
13a No board outline simulation, STL 67 ms 25 ms 55 ms 0.1 ms 0.1 6 ms 17 ms 0.2 0.5
13a No board outline simulation, OBJ 65 ms 23 ms 53 ms 0.1 ms 0.1 62 ms 16 ms 0.2 0.6
13a No board outline visual, GLB 71 ms 24 ms 54 ms 0.1 ms 0.2 4 ms 64 ms 0.2 0.6
13a No board outline visual, OBJ 65 ms 24 ms 51 ms 0.1 ms 0.2 38 ms 45 ms 0.2 0.6
13b Two board outlines simulation, GLB 68 ms 21 ms 39 ms 0.1 ms 0.1 5 ms 15 ms 0.2 0.5
13b Two board outlines simulation, STEP 73 ms 23 ms 47 ms 0.1 ms 0.1 0.1 15 ms 0.2 0.6
13b Two board outlines simulation, STL 68 ms 23 ms 41 ms 0.1 ms 0.1 5 ms 16 ms 0.2 0.5
13b Two board outlines simulation, OBJ 82 ms 29 ms 47 ms 0.1 ms 0.1 39 ms 18 ms 0.2 0.5
13b Two board outlines visual, GLB 72 ms 22 ms 51 ms 0.1 ms 0.2 3 ms 22 ms 0.2 0.6
13b Two board outlines visual, OBJ 68 ms 21 ms 48 ms 0.1 ms 0.2 30 ms 22 ms 0.2 0.6
14 Full stack-up simulation, GLB 68 ms 35 ms 72 ms 0.1 ms 0.2 5 ms 18 ms 0.2 0.5
14 Full stack-up simulation, STEP 72 ms 36 ms 68 ms 0.1 ms 0.2 0.1 18 ms 0.2 0.7
14 Full stack-up simulation, STL 67 ms 35 ms 66 ms 0.1 ms 0.2 6 ms 20 ms 0.2 0.5
14 Full stack-up simulation, OBJ 74 ms 38 ms 60 ms 0.1 ms 0.2 68 ms 21 ms 0.2 0.6
14 Full stack-up visual, GLB 69 ms 36 ms 72 ms 0.1 ms 0.4 4 ms 35 ms 0.2 0.8
14 Full stack-up visual, OBJ 86 ms 37 ms 62 ms 0.1 ms 0.3 46 ms 31 ms 0.2 0.7
15 No stack-up simulation, GLB 75 ms 34 ms 61 ms 0.1 ms 0.1 4 ms 18 ms 0.2 0.5
15 No stack-up simulation, STEP 65 ms 31 ms 56 ms 0.1 ms 0.2 0.1 18 ms 0.2 0.7
15 No stack-up simulation, STL 73 ms 31 ms 62 ms 0.1 ms 0.1 5 ms 17 ms 0.2 0.5
15 No stack-up simulation, OBJ 69 ms 29 ms 55 ms 0.1 ms 0.1 59 ms 20 ms 0.2 0.6
15 No stack-up visual, GLB 64 ms 30 ms 52 ms 0.1 ms 0.3 4 ms 32 ms 0.2 0.7
15 No stack-up visual, OBJ 64 ms 27 ms 53 ms 0.1 ms 0.3 32 ms 27 ms 0.2 0.7
16 Castellated pads and a plated edge simulation, GLB 71 ms 70 ms 95 ms 0.1 ms 0.2 4 ms 20 ms 0.2 0.6
16 Castellated pads and a plated edge simulation, STEP 72 ms 70 ms 0.1 0.1 ms 0.2 0.1 19 ms 0.2 0.8
16 Castellated pads and a plated edge simulation, STL 70 ms 73 ms 0.1 0.1 ms 0.2 6 ms 19 ms 0.2 0.7
16 Castellated pads and a plated edge simulation, OBJ 73 ms 72 ms 92 ms 0.1 ms 0.2 81 ms 20 ms 0.2 0.7
16 Castellated pads and a plated edge visual, GLB 68 ms 71 ms 89 ms 0.1 ms 0.3 4 ms 34 ms 0.2 0.7
16 Castellated pads and a plated edge visual, OBJ 69 ms 70 ms 96 ms 0.1 ms 0.3 51 ms 31 ms 0.2 0.8
16b Plated board edge with a GND border simulation, GLB 0.1 0.5 2.2 0.2 ms 2.2 67 ms 0.3 0.2 5.6
16b Plated board edge with a GND border simulation, STEP 0.1 0.4 2.2 0.1 ms 2.2 1.3 0.2 0.2 6.6
16b Plated board edge with a GND border simulation, STL 0.1 0.5 2.2 0.2 ms 2.2 0.1 0.3 0.2 5.5
16b Plated board edge with a GND border simulation, OBJ 0.1 0.5 2.1 0.2 ms 2.3 2.6 0.3 0.2 8.1
16b Plated board edge with a GND border visual, GLB 99 ms 0.5 2.2 0.2 ms 4.5 23 ms 0.2 0.2 7.6
16b Plated board edge with a GND border visual, OBJ 0.1 0.5 2.3 0.2 ms 4.5 0.9 0.1 0.2 8.6
17 Solder mask and silkscreen simulation, GLB 74 ms 72 ms 0.1 0.1 ms 0.2 5 ms 16 ms 0.2 0.6
17 Solder mask and silkscreen simulation, STEP 73 ms 62 ms 98 ms 0.1 ms 0.2 0.2 20 ms 0.2 0.8
17 Solder mask and silkscreen simulation, STL 77 ms 71 ms 0.1 0.1 ms 0.2 7 ms 17 ms 0.2 0.7
17 Solder mask and silkscreen simulation, OBJ 82 ms 67 ms 0.1 0.1 ms 0.2 0.1 17 ms 0.2 0.8
17 Solder mask and silkscreen visual, GLB 98 ms 78 ms 0.1 0.1 ms 0.3 5 ms 38 ms 0.2 0.8
17 Solder mask and silkscreen visual, OBJ 80 ms 65 ms 0.1 0.1 ms 0.3 0.1 47 ms 0.2 1.0
17b Silkscreen over copper simulation, GLB 82 ms 36 ms 0.1 0.1 ms 0.2 5 ms 24 ms 0.2 0.7
17b Silkscreen over copper simulation, STEP 69 ms 33 ms 0.2 0.1 ms 0.2 0.2 26 ms 0.2 0.9
17b Silkscreen over copper simulation, STL 76 ms 35 ms 0.1 0.1 ms 0.3 8 ms 26 ms 0.2 0.8
17b Silkscreen over copper simulation, OBJ 70 ms 32 ms 0.2 0.1 ms 0.3 0.1 23 ms 0.2 0.8
17b Silkscreen over copper visual, GLB 70 ms 31 ms 0.2 0.1 ms 0.4 4 ms 39 ms 0.2 0.9
17b Silkscreen over copper visual, OBJ 71 ms 32 ms 0.2 0.1 ms 0.4 80 ms 32 ms 0.2 1.0
18 Gold edge fingers simulation, GLB 79 ms 35 ms 55 ms 0.1 ms 0.2 5 ms 19 ms 0.2 0.6
18 Gold edge fingers simulation, STEP 67 ms 38 ms 49 ms 0.1 ms 0.2 0.1 17 ms 0.2 0.7
18 Gold edge fingers simulation, STL 69 ms 36 ms 49 ms 0.1 ms 0.2 6 ms 18 ms 0.2 0.6
18 Gold edge fingers simulation, OBJ 68 ms 34 ms 55 ms 0.1 ms 0.2 88 ms 17 ms 0.2 0.6
18 Gold edge fingers visual, GLB 70 ms 35 ms 48 ms 0.1 ms 0.3 5 ms 51 ms 0.2 0.7
18 Gold edge fingers visual, OBJ 86 ms 35 ms 46 ms 0.1 ms 0.3 77 ms 49 ms 0.2 0.8
18b Finish on every kind of bare copper simulation, GLB 68 ms 36 ms 0.1 0.1 ms 0.3 8 ms 24 ms 0.2 0.7
18b Finish on every kind of bare copper simulation, STEP 73 ms 43 ms 0.1 0.2 ms 0.3 0.2 22 ms 0.2 0.9
18b Finish on every kind of bare copper simulation, STL 75 ms 43 ms 0.1 0.1 ms 0.2 8 ms 26 ms 0.2 0.7
18b Finish on every kind of bare copper simulation, OBJ 70 ms 35 ms 0.1 0.1 ms 0.2 0.1 23 ms 0.2 0.8
18b Finish on every kind of bare copper visual, GLB 69 ms 36 ms 0.1 0.2 ms 0.4 4 ms 40 ms 0.2 0.8
18b Finish on every kind of bare copper visual, OBJ 69 ms 33 ms 94 ms 0.2 ms 0.4 65 ms 33 ms 0.2 0.8
18c Finish before the solder mask simulation, GLB 70 ms 32 ms 0.2 0.2 ms 0.5 9 ms 36 ms 0.2 0.9
18c Finish before the solder mask simulation, STEP 74 ms 33 ms 0.2 0.1 ms 0.5 0.4 43 ms 0.2 1.3
18c Finish before the solder mask simulation, STL 71 ms 37 ms 0.2 0.1 ms 0.5 12 ms 34 ms 0.2 1.0
18c Finish before the solder mask simulation, OBJ 74 ms 35 ms 0.2 0.1 ms 0.5 0.2 38 ms 0.2 1.2
18c Finish before the solder mask visual, GLB 70 ms 34 ms 0.2 0.1 ms 0.6 6 ms 36 ms 0.2 1.1
18c Finish before the solder mask visual, OBJ 68 ms 35 ms 0.2 0.2 ms 0.6 80 ms 37 ms 0.2 1.2
19 Items KESE skips simulation, GLB 72 ms 17 ms 20 ms 0.1 ms 67 ms 4 ms 8 ms 0.2 0.4
19 Items KESE skips simulation, STEP 67 ms 17 ms 22 ms 0.1 ms 43 ms 42 ms 7 ms 0.2 0.4
19 Items KESE skips simulation, STL 65 ms 17 ms 19 ms 0.1 ms 43 ms 3 ms 6 ms 0.2 0.3
19 Items KESE skips simulation, OBJ 74 ms 18 ms 21 ms 0.1 ms 46 ms 16 ms 7 ms 0.2 0.4
19 Items KESE skips visual, GLB 66 ms 16 ms 21 ms 0.1 ms 0.1 2 ms 18 ms 0.2 0.4
19 Items KESE skips visual, OBJ 65 ms 17 ms 21 ms 0.1 ms 0.1 26 ms 19 ms 0.2 0.4
19b Items KESE skips, KiCad 10 simulation, GLB 0.7 ms 6 ms 10 ms 0.0 ms 15 ms 1 ms 1 ms 0.2 0.2
19b Items KESE skips, KiCad 10 simulation, STEP 0.8 ms 4 ms 11 ms 0.1 ms 19 ms 6 ms 2 ms 0.2 0.2
19b Items KESE skips, KiCad 10 simulation, STL 0.8 ms 6 ms 7 ms 0.0 ms 15 ms 1 ms 5 ms 0.2 0.2
19b Items KESE skips, KiCad 10 simulation, OBJ 0.8 ms 7 ms 8 ms 0.0 ms 15 ms 1 ms 1 ms 0.2 0.2
19b Items KESE skips, KiCad 10 visual, GLB 0.9 ms 4 ms 15 ms 0.0 ms 26 ms 1 ms 11 ms 0.2 0.2
19b Items KESE skips, KiCad 10 visual, OBJ 0.9 ms 4 ms 8 ms 0.0 ms 34 ms 1 ms 11 ms 0.2 0.2
20a KiCad 6 format simulation, GLB 65 ms 29 ms 61 ms 0.1 ms 0.1 4 ms 17 ms 0.2 0.5
20a KiCad 6 format simulation, STEP 66 ms 25 ms 60 ms 0.1 ms 0.2 0.2 18 ms 0.2 0.6
20a KiCad 6 format simulation, STL 66 ms 27 ms 62 ms 0.1 ms 0.2 7 ms 19 ms 0.2 0.5
20a KiCad 6 format simulation, OBJ 67 ms 26 ms 66 ms 0.1 ms 0.2 79 ms 18 ms 0.2 0.6
20a KiCad 6 format visual, GLB 71 ms 27 ms 65 ms 0.1 ms 0.3 4 ms 35 ms 0.2 0.7
20a KiCad 6 format visual, OBJ 80 ms 29 ms 62 ms 0.1 ms 0.3 62 ms 29 ms 0.2 0.7
20b KiCad 7 format simulation, GLB 74 ms 28 ms 71 ms 0.1 ms 0.2 5 ms 18 ms 0.2 0.6
20b KiCad 7 format simulation, STEP 78 ms 31 ms 65 ms 0.1 ms 0.2 0.2 19 ms 0.2 0.7
20b KiCad 7 format simulation, STL 69 ms 28 ms 61 ms 0.1 ms 0.2 6 ms 16 ms 0.2 0.5
20b KiCad 7 format simulation, OBJ 69 ms 31 ms 72 ms 0.1 ms 0.2 77 ms 17 ms 0.2 0.6
20b KiCad 7 format visual, GLB 77 ms 31 ms 70 ms 0.1 ms 0.3 5 ms 33 ms 0.2 0.7
20b KiCad 7 format visual, OBJ 70 ms 28 ms 73 ms 0.1 ms 0.3 60 ms 29 ms 0.2 0.7
20c KiCad 8 format simulation, GLB 72 ms 30 ms 66 ms 0.1 ms 0.2 5 ms 19 ms 0.2 0.5
20c KiCad 8 format simulation, STEP 73 ms 27 ms 59 ms 0.1 ms 0.2 0.2 20 ms 0.2 0.7
20c KiCad 8 format simulation, STL 82 ms 28 ms 68 ms 0.1 ms 0.2 6 ms 17 ms 0.2 0.6
20c KiCad 8 format simulation, OBJ 70 ms 28 ms 72 ms 0.1 ms 0.2 77 ms 17 ms 0.2 0.6
20c KiCad 8 format visual, GLB 69 ms 28 ms 72 ms 0.1 ms 0.3 4 ms 35 ms 0.2 0.7
20c KiCad 8 format visual, OBJ 71 ms 30 ms 65 ms 0.1 ms 0.3 63 ms 32 ms 0.2 0.7
20d KiCad 9 format simulation, GLB 75 ms 29 ms 68 ms 0.1 ms 0.2 5 ms 17 ms 0.2 0.6
20d KiCad 9 format simulation, STEP 67 ms 33 ms 66 ms 0.1 ms 0.2 0.2 17 ms 0.2 0.7
20d KiCad 9 format simulation, STL 69 ms 34 ms 64 ms 0.1 ms 0.2 7 ms 16 ms 0.2 0.5
20d KiCad 9 format simulation, OBJ 70 ms 29 ms 67 ms 0.1 ms 0.2 74 ms 19 ms 0.2 0.6
20d KiCad 9 format visual, GLB 68 ms 28 ms 71 ms 0.1 ms 0.3 4 ms 30 ms 0.2 0.7
20d KiCad 9 format visual, OBJ 67 ms 27 ms 69 ms 0.1 ms 0.3 59 ms 31 ms 0.2 0.7
20e KiCad 10 format simulation, GLB 76 ms 28 ms 62 ms 0.1 ms 0.2 5 ms 17 ms 0.2 0.5
20e KiCad 10 format simulation, STEP 70 ms 36 ms 73 ms 0.1 ms 0.2 0.1 17 ms 0.2 0.7
20e KiCad 10 format simulation, STL 73 ms 32 ms 63 ms 0.1 ms 0.2 7 ms 17 ms 0.2 0.5
20e KiCad 10 format simulation, OBJ 68 ms 27 ms 64 ms 0.1 ms 0.2 93 ms 21 ms 0.2 0.6
20e KiCad 10 format visual, GLB 70 ms 27 ms 64 ms 0.1 ms 0.3 4 ms 32 ms 0.2 0.7
20e KiCad 10 format visual, OBJ 69 ms 29 ms 68 ms 0.1 ms 0.3 60 ms 31 ms 0.2 0.8
21 RF sensor module simulation, GLB 0.2 1.6 7.2 0.4 ms 5.5 0.3 0.6 0.2 15.7
21 RF sensor module simulation, STEP 0.3 1.9 7.2 0.4 ms 5.6 3.1 0.6 0.3 18.9
21 RF sensor module simulation, STL 0.3 1.7 6.8 0.4 ms 5.3 0.4 0.5 0.2 15.2
21 RF sensor module simulation, OBJ 0.3 1.8 6.8 0.5 ms 5.5 8.3 0.6 0.2 23.4
21 RF sensor module visual, GLB 0.3 1.7 6.8 0.4 ms 9.5 94 ms 0.6 0.2 19.1
21 RF sensor module visual, OBJ 0.2 1.6 6.7 0.5 ms 9.8 3.8 0.8 0.2 23.1
22 HDI radio module simulation, GLB 0.2 1.1 2.5 0.4 ms 2.0 0.1 0.5 0.3 6.7
22 HDI radio module simulation, STEP 0.2 1.1 2.4 0.4 ms 2.0 1.7 0.5 0.2 8.1
22 HDI radio module simulation, STL 0.2 1.0 2.6 0.4 ms 2.0 0.2 0.4 0.2 6.6
22 HDI radio module simulation, OBJ 0.2 1.0 2.5 0.3 ms 2.0 3.5 0.5 0.2 9.9
22 HDI radio module visual, GLB 0.2 1.0 2.6 0.4 ms 4.0 66 ms 0.4 0.2 8.5
22 HDI radio module visual, OBJ 0.2 1.0 2.7 0.4 ms 4.1 1.7 0.4 0.2 10.3
23 PCIe x1 card simulation, GLB 0.3 1.2 3.8 0.5 ms 3.7 0.2 0.6 0.2 10.0
23 PCIe x1 card simulation, STEP 0.3 1.2 3.9 0.4 ms 3.8 3.0 0.6 0.2 12.9
23 PCIe x1 card simulation, STL 0.3 1.1 3.9 0.4 ms 3.4 0.3 0.5 0.2 9.7
23 PCIe x1 card simulation, OBJ 0.3 1.2 3.7 0.4 ms 3.5 7.1 0.5 0.2 16.5
23 PCIe x1 card visual, GLB 0.3 1.1 3.8 0.5 ms 7.6 0.1 0.8 0.2 13.9
23 PCIe x1 card visual, OBJ 0.3 1.3 3.8 0.6 ms 7.4 3.9 0.8 0.2 17.7
24 Backdrills simulation, GLB 82 ms 0.2 0.3 0.1 ms 0.6 22 ms 90 ms 0.2 1.5
24 Backdrills simulation, STEP 73 ms 0.2 0.3 0.2 ms 0.6 0.8 90 ms 0.2 2.2
24 Backdrills simulation, STL 72 ms 0.2 0.2 0.2 ms 0.6 28 ms 86 ms 0.2 1.3
24 Backdrills simulation, OBJ 70 ms 0.2 0.2 0.2 ms 0.6 0.5 90 ms 0.2 1.9
24 Backdrills visual, GLB 70 ms 0.2 0.3 0.2 ms 1.3 12 ms 75 ms 0.2 2.0
24 Backdrills visual, OBJ 72 ms 0.2 0.3 0.1 ms 1.3 0.3 68 ms 0.2 2.3
25 Counterbores and countersinks simulation, GLB 76 ms 0.1 0.8 0.1 ms 1.5 15 ms 0.1 0.2 2.9
25 Counterbores and countersinks simulation, STEP 75 ms 0.1 0.8 0.1 ms 1.6 0.9 0.1 0.2 3.8
25 Counterbores and countersinks simulation, STL 74 ms 0.2 0.9 0.1 ms 1.5 21 ms 0.1 0.2 3.0
25 Counterbores and countersinks simulation, OBJ 74 ms 0.1 0.9 0.1 ms 1.6 0.4 0.2 0.2 3.5
25 Counterbores and countersinks visual, GLB 75 ms 0.1 0.9 0.1 ms 3.5 14 ms 88 ms 0.2 4.9
25 Counterbores and countersinks visual, OBJ 81 ms 0.1 0.9 0.1 ms 3.6 0.4 77 ms 0.2 5.4
26 Via protection simulation, GLB 6 ms 0.1 0.2 0.1 ms 0.5 16 ms 59 ms 0.2 1.1
26 Via protection simulation, STEP 5 ms 0.1 0.1 0.1 ms 0.5 0.7 62 ms 0.2 1.7
26 Via protection simulation, STL 5 ms 0.1 0.2 0.1 ms 0.5 20 ms 59 ms 0.2 1.1
26 Via protection simulation, OBJ 5 ms 0.1 0.2 0.2 ms 0.5 0.4 62 ms 0.2 1.5
26 Via protection visual, GLB 5 ms 0.1 0.2 0.2 ms 1.0 8 ms 0.1 0.2 1.6
26 Via protection visual, OBJ 5 ms 0.1 0.2 0.2 ms 1.1 0.2 73 ms 0.2 1.9
27 Hatched fills simulation, GLB 0.1 86 ms 0.2 0.1 ms 1.0 11 ms 54 ms 0.2 1.7
27 Hatched fills simulation, STEP 0.1 78 ms 0.2 0.1 ms 1.0 0.8 56 ms 0.2 2.4
27 Hatched fills simulation, STL 0.1 92 ms 0.2 0.1 ms 1.0 19 ms 51 ms 0.2 1.7
27 Hatched fills simulation, OBJ 0.1 85 ms 0.2 0.1 ms 1.0 0.3 61 ms 0.2 1.9
27 Hatched fills visual, GLB 0.1 84 ms 0.2 0.1 ms 0.9 10 ms 67 ms 0.2 1.5
27 Hatched fills visual, OBJ 0.1 92 ms 0.2 0.1 ms 0.9 0.3 66 ms 0.2 1.8
28 Machining at a plated edge simulation, GLB 70 ms 69 ms 0.3 0.1 ms 0.6 6 ms 42 ms 0.2 1.3
28 Machining at a plated edge simulation, STEP 66 ms 70 ms 0.3 0.1 ms 0.6 0.2 40 ms 0.2 1.5
28 Machining at a plated edge simulation, STL 72 ms 75 ms 0.3 0.1 ms 0.6 9 ms 39 ms 0.2 1.3
28 Machining at a plated edge simulation, OBJ 68 ms 74 ms 0.3 0.1 ms 0.6 0.1 47 ms 0.2 1.4
28 Machining at a plated edge visual, GLB 67 ms 69 ms 0.3 0.1 ms 0.9 7 ms 38 ms 0.2 1.5
28 Machining at a plated edge visual, OBJ 78 ms 75 ms 0.3 0.2 ms 0.9 76 ms 35 ms 0.2 1.6
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