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BRAM Output Queues with registers and back pressure

Marco Forconesi edited this page Mar 23, 2015 · 1 revision

Name

nf10_bram_output_queues

Version

v1.11a

Author

Type

pcore (HW)

Location

netfpga-10g/lib/hw/std/pcores/nf10_bram_output_queues_v1_10_a/

Interface Types

AXI4-Stream

Busses

S_AXIS: Slave AXI4-Stream bus, Variable width

M_AXIS_0: Master AXI4-Stream bus, Variable width

M_AXIS_1: Master AXI4-Stream bus, Variable width

M_AXIS_2: Master AXI4-Stream bus, Variable width

M_AXIS_3: Master AXI4-Stream bus, Variable width

M_AXIS_4: Master AXI4-Stream bus, Variable width

S_AXI: Slave AXI4-Lite

Parameters

C_AXIS_DATA_WIDTH: Data width of the AXI4-Stream bus.

C_BASEADDR: Base address value of the core.

C_HIGHADDR: High address value of the core.

Register map

0x0 : RESET_CNTRS_OFFSET

0x4 : PKT_STORED_PORT_0_OFFSET

0x8 : BYTES_STORED_PORT_0_OFFSET

0xc : PKT_REMOVED_PORT_0_OFFSET

0x10 : BYTES_REMOVED_PORT_0_OFFSET

0x14 : PKT_DROPPED_PORT_0_OFFSET

0x18 : BYTES_DROPPED_PORT_0_OFFSET

0x1c : PKT_IN_QUEUE_PORT_0_OFFSET

0x20 : BYTES_IN_QUEUE_PORT_0_OFFSET

0x24 : PKT_STORED_PORT_1_OFFSET

0x28 : BYTES_STORED_PORT_1_OFFSET

0x2c : PKT_REMOVED_PORT_1_OFFSET

0x30 : BYTES_REMOVED_PORT_1_OFFSET

0x34 : PKT_DROPPED_PORT_1_OFFSET

0x38 : BYTES_DROPPED_PORT_1_OFFSET

0x3c : PKT_IN_QUEUE_PORT_1_OFFSET

0x40 : BYTES_IN_QUEUE_PORT_1_OFFSET

0x44 : PKT_STORED_PORT_2_OFFSET

0x48 : BYTES_STORED_PORT_2_OFFSET

0x4c : PKT_REMOVED_PORT_2_OFFSET

0x50 : BYTES_REMOVED_PORT_2_OFFSET

0x54 : PKT_DROPPED_PORT_2_OFFSET

0x58 : BYTES_DROPPED_PORT_2_OFFSET

0x5c : PKT_IN_QUEUE_PORT_2_OFFSET

0x60 : BYTES_IN_QUEUE_PORT_2_OFFSET

0x64 : PKT_STORED_PORT_3_OFFSET

0x68 : BYTES_STORED_PORT_3_OFFSET

0x6c : PKT_REMOVED_PORT_3_OFFSET

0x70 : BYTES_REMOVED_PORT_3_OFFSET

0x74 : PKT_DROPPED_PORT_3_OFFSET

0x78 : BYTES_DROPPED_PORT_3_OFFSET

0x7c : PKT_IN_QUEUE_PORT_3_OFFSET

0x80 : BYTES_IN_QUEUE_PORT_3_OFFSET

0x84 : PKT_STORED_PORT_4_OFFSET

0x88 : BYTES_STORED_PORT_4_OFFSET

0x8c : PKT_REMOVED_PORT_4_OFFSET

0x90 : BYTES_REMOVED_PORT_4_OFFSET

0x94 : PKT_DROPPED_PORT_4_OFFSET

0x98 : BYTES_DROPPED_PORT_4_OFFSET

0x9c : PKT_IN_QUEUE_PORT_4_OFFSET

0x100: BYTES_IN_QUEUE_PORT_4_OFFSET

Description

The function of this block is to dispatch packets from one input stream to a number of output streams whereby the DPT sub-band channel determines to which output the packets are routed. All input interfaces need to have the same bandwidth (and therefore width) as the output stream to ensure that maximum throughput can be achieved. The arbiter can operate in 1G or 10G mode; this is setup through selecting the data width accordingly.

The difference between this version and the previous one is that packets cannot be dropped within the module. If an output interface has insufficient bandwidth, the Output Queues (e.g. this module) will receive back pressure to throttle the rate. In this case, the internal state machines will stall until the interface signals that it is ready for continue receiving packets - in the meanwhile the Output Queues will signal it is not ready for receiving incoming packets from the Output Port Lookup and hence propagating the back pressure. This version has been created for the "reference_nic" like projects where a dma engine capable of more than 10Gbps is in use. When the software is sending outbound packets to a single interface at top speed, it generally exceeds the rate of 10Gbps. In this case, the back pressure originated in the MAC core needs to be propagated through the reference pipeline (e.g. Output Queues, Output Port Lookup, Input Arbiter) to the dma engine. The dma engine will then reduce the speed until it matches the maximum allowed by the interface.

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