IP Library

NetFPGA-10G leverages Xilinx's large AXI-based IP core library and builds all NetFPGA-10G native IP as AXI-compliant pcores. See here for more information on the AXI standard.

IP cores with a "nf10_" prefix were developed by the NetFPGA team, while those without this prefix were taken or derived from Xilinx IP. Many of these "non-nf10" pcores were modified from Xilinx IP so as to be synthesizable for Virtex-5 devices, since they were originally designed to be Virtex-6 specific. We do not have documentation here for those types of pcores, but rather defer to Xilinx for such information. For more details on how we were able to port these pcores to Virtex-5, please see the document "Port an AXI IP to Virtex-5 device".

• 10G MAC Interface
• 1G MAC Interface
• AXI4-Stream Packet Generator/Checker
• MDIO Engine
• Input Arbiter
• BRAM Ouput Queues
• NIC Output Port Lookup
• OPED
• AXI4-Stream Width Converter
• SRAM FIFO
• Switch Output Port Lookup new!

Here is some information that may be useful for IP development

• How to Create a Custom AXI IP
• Port an AXI IP to Virtex-5 device

Contributions

• AXI4-Stream and Packet Bus Bridge
• AXI4-Lite and Register Bus Bridge
• NetFPGA-1G NIC Port
• NetFPGA-1G Switch Port
• NetFPGA-1G Port Template
• DMA Engine
• Simple Switch new!
• [ARP Reply] (ARP-Reply) new!
• [Encap] (Encap) new!
• [Decap] (Decap) new!
• Register IO new!
• Memcached Client new!