NiC NaaS

Name

nic_naas

Author

Marco Forconesi (marco.forconesi_at_cl.cam.ac.uk)

Location

contrib-projects/nic_naas/

IP Cores

• NetFPGA-10G Specific cores
  • nf10_10g_interface
  • nf10_mdio
  • DMA v2.1x
  • nf10_nic_output_port_lookup
  • nf10_bram_output_queues
  • nf10_input_arbiter
• Xilinx AXI Peripheral
  • axi_interconnect
  • axi_uartlite
  • axi_timebase_wdt
• Microblaze Subsystem
  • MicroBlaze
  • lmb_v10
  • lmb_bram_if_cntlr
  • bram_block
  • proc_sys_reset
  • clock_generator
• Other
  • diff_input_buf

Software

• Linux Device Driver

Description

This project is based on the reference nic project and its aim is to test a new version of a DMA/driver subsystem. It is assumed that the user has experience with the reference nic and understands the concept of the each component in the system as well as the software on the host machine.

Every aspect including the hardware block diagram and the basic testing is compatible with the reference nic. It is recommended that the user gets first familiarized with the reference nic first before digging into this version.

The main contribution of this projects are:

• A more efficient DMA/driver which is able to achieve 9.41Gbps running iperf. Note that core affinitizing could be needed as well as a kernel version 3.14 or newer.
• Sustainable line-rate for all packet sizes, e.g. 60 to 1514 bytes packets.
• Kernel bypassing features. Under sw/host/apps/nf10-usr-level you will find example applications that bypass the kernel and take advantage of a DMA capable of line-rate across all the packet range.

Disclaimer

Be aware that this project and its components are under development and testing. Stability is not guaranteed and the reference nic is suggested for that matter. You are welcome to test it and give any feedback to marco.forconesi_at_cl.cam.ac.uk - Any contribution will be much appreciated.

Block Diagram

Same as reference nic.