NetFPGA 10G RLDRAM Stream
This RLDRAM Axi stream contrib project uses Xilinx RLDRAM controller as a packet buffer. Figure on below shows configuration of the project. The RLDRAM controller with Axi stream compliant interface is between Output Port Lookup and BRAM Output Queues. The controller stores all packets coming from Output Port Lookup and forwards them to BRAM Output Queues.
After cloning NetFPGA10G-live, follow below steps to set up environments for RLDRAM projects.
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Download Xilinx RLDRAM memory controller to ./contrib-projects/rldram_stream/hw/pcores/nf10_rldram_stream_v1_00_a/hdl/verilog/.
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Extract the downloaded file at the same directory.
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Create a directory xilinx, copy all verilog files in ./XAPP852/verilog/ to xilinx directory.
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Do a Make outside the xilinx directory, to patch the files for our design requirements.
Before run simulation, users need to download Micron RLDRAM model from the website. Once the model is downloaded, copy rldram2.v and rldram2_parameter.v to ./NetFPGA-10G/contrib-projects/rldram_stream/hw/nf10/. Then, move to ./NetFPGA-10G-live/tools/bin/ and run the command on below. Users can find more information about the simulation in NetFPGA-10G simulation page.
$./nf_test.py sim --major rx --minor dma --isim --rx –gui
The RLDRAM controller has been integrated with Axi-lite bus. And, there are registers mapped on the bus address. Address range : 0x87006000 (This base address can be modified into other address that users preferred.)
1. Offset : 0x00, Clear register that clears read only registers from 0x04 – 0x14. Once this register is written any value, the read only register values are cleared.
2. Offset : 0x04, RLDRAM address of packet written.
3. Offset : 0x08, RLDRAM address of packet read.
4. Offset : 0x0C, [31:16] – number of read packets, [15:0] – number of write packets.
5. Offset : 0x10, This value indicates status of the RLDRAM on the board. After programming FPGA with a bit image, if it is 0x3, the RLDRAM is successfully initialize.
Note : Read and write data interfaces of the RLDRAM are bidirectional ports. Thus, data can be read from RLDRAM after completing data writing processes, which increases latency of packet data. If users are interested in low latency packet data, the SRAM controller, which read and write ports are separated in uni-direction, is more suitable for that purpose.