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Memcached client
nf10_axis_memcached
v1.00a
Jeremia Baer (baerj_at_ethz.ch)
pcore (HW)
lib/hw/contrib/pcores/nf10_axis_memcached_client_v1_00_a/
AXI4-Lite, AXI4-Stream
S_AXIS: Slave AXI4-Stream bus, Variable width
M_AXIS: Master AXI4-Stream bus, Variable width
S_AXI: Slave AXI4-Lite
C_AXIS_DATA_WIDTH: Data width of the AXI4-Stream bus.
C_USER_WIDTH: Data width of the TUSER field.
localparam [31:0] REG_RUN = BASEADDR + 32'h00000000;
- start/stop packet generator localparam [31:0] REG_COUNTER_RESET = BASEADDR + 32'h00000001;
- set and unset to reset statistics localparam [31:0] REG_IFG = BASEADDR + 32'h00000002;
- inter frame gap used between repeated requests localparam [31:0] REG_ONESHOT = BASEADDR + 32'h00000003;
- write to this address to trigger a latency measurement
- read from this address to get the result of the latest measurement
- the MSB is used as a valid bit:
- triggering a measurement sets this bit to 0.
- when a response is recieved (or after 5sec), the bit is set to 1 localparam [31:0] REG_TX_COUNT = BASEADDR + 32'h00000010;
- counts the number of packets sent localparam [31:0] REG_RX_COUNT = BASEADDR + 32'h00000011;
- counts the number of packets received that match the check/RX buffer localparam [31:0] REG_ERR_COUNT = BASEADDR + 32'h00000012;
- counts the number of packets received that do not match the check/RX buffer localparam [31:0] REG_STREAMBLOCK = BASEADDR + 32'h00000020;
- update the send/TX and check/RX buffers. an update is performed by 764 subsequent writes to this register as follows:
- write 1: Number of 8-byte data words the send/TX buffers consists of
- write 2: Strobe field for the last 8-byte data word of the send/TX buffer
- write 3-382: 380 writes of 4 bytes of the send/TX buffer in each (for a total of 1520B)
- write 383-764: the same for the check/RX buffer
This module implements the packet generator/checker/latency measurement/validiation functionality of the memcached_client project. It has two AXI4-Streams (Master/Slave) to send/receive network packets. For configuration and control it has an AXI4-Lite interface. A detailed description of the functionality and usage can be found in the memcached_client project {reference please}.