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Platform IP Documentation
--under construction----
This page describes interfaces, parameters, register map and general properties for key building blocks in the Howth and Skellig reference designs.
Interfaces:
This block has the following interfaces:
* 5 slave AXI streaming interfaces which can be parameterized to be 32bit or 256bit wide depending on whether we operate in 1G or 10G mode. One of these interfaces would connect to the PCIe endpoint (oped) and the other 4 to the AXI preprocessors.
* 1 master AXI streaming interface which can be parameterized to be 32bit or 256bit wide. This would typically feed the data path through the FPGA.
These interfaces all have the AXIS-NetFPGA-10G base class defined sub-band channels. When these are unused, then they need to be driven as '0'. In general the information propagates through as provided on the input. For example, if error channel is not driven, then the corresponding output packets will never have error asserted either. Similarly on the length channel, when un-driven an invalid packet length of 0bytes is propagated. Also, the corresponding VALID signals never assert.
All interfaces must have the same data width parameter setting.
In addition the input arbiter will have one AXI lite interface for control and status.
Parameters:
All streaming interfaces will provide the standardized AXI streaming interface parameters relating to data width etc. - see interface description:
Standard Interfaces for NetFPGA-10G Platform IP
The AXI lite interface provides the standardized AXI lite parameters - again see interface description.
Register map:
The input arbiter provides only 6 register to be read at C_BASEADDR with offsets 0,1,2,3,4 and 5.
offset 0: number of received packet on interface 0
offset 1: number of received packet on interface 1
offset 2: number of received packet on interface 2
offset 3: number of received packet on interface 3
offset 4: number of received packet on interface 4
offset 5: number of transmitted packets
General properties:
The function of this block is to merge a number of input streams into one output stream. All input interfaces need to have the same bandwidth (and therefore width) as the output stream to ensure that maximum throughput can be achieved.
There will be only one FIFO inside this module which is sitting in front of the output port. The input port buffering will be handled in the AXI pre-processor block.
The arbiter can operate in 1G or 10G mode; this is setup through selecting the data width accordingly.
Interfaces:
This block has the following interfaces:
* 5 master AXI streaming interfaces which can be parameterized to be 32bit or 256bit wide depending on whether we operate in 1G or 10G mode. One of these interfaces would connect to the PCIe endpoint (oped) and the other 4 to the AXI post-processors.
* 1 slave AXI streaming interface which can be parameterized to be 32bit or 256bit wide. This would typically be the endpoint of the data path through the FPGA before packets are dispatched to the various network interfaces.
These interfaces all have the AXIS-NetFPGA-10G base class specified sub-band channels present. When these are unused, then they need to be driven as '0'. In general the information propagates through as provided on the input. For example, if error channel is not driven, then the corresponding output packets will never have error asserted either. Similarly on the length channel, when un-driven an invalid packet length of 0bytes is propagated. Also, the corresponding VALID signals never assert.
All interfaces must have the same data width parameter setting.
In addition the input arbiter will have one AXI lite interface for control and status.
Parameters:
All streaming interfaces will provide the standardized AXI streaming interface parameters relating to data width etc. - see interface description:
Standard Interfaces for NetFPGA-10G Platform IP
The AXI lite interface provides the standardized AXI lite parameters - again see interface description.
Register map:
The input arbiter provides only 6 register to be read at C_BASEADDR with offsets 0,1,2,3,4 and 5.
offset 0: number of transmitted packet on interface 0
offset 1: number of transmitted packet on interface 1
offset 2: number of transmitted packet on interface 2
offset 3: number of transmitted packet on interface 3
offset 4: number of transmitted packet on interface 4
offset 5: number of received packets
General properties:
The function of this block is to dispatch packets from one input stream to a number of output streams whereby the DPT sub-band channel determines to which output the packets are routed. DPT value 0 corresponds to output port 0, and so on.
All input interfaces need to have the same bandwidth (and therefore width) as the output stream to ensure that maximum throughput can be achieved.
The arbiter can operate in 1G or 10G mode; this is setup through selecting the data width accordingly.
This module does not require any internal buffering as this is handled by the AXI post-processor block.
Interfaces:
Parameters:
Register map:
General properties:
The wrapper will fast forward the BAD_FRAME signal to appear during the packet transmission when TVALID is asserted on the data channel.
It will include FIFOs such that the AXI interface on the receiving side can provide flow control (accept a READY signal)
Interfaces:
This block has the following interfaces:
* 2 AXI stream interfaces with different widths (one master and one slave)
* 1 AXI lite interface for polling of statistics.
The slave data streaming interface has an error sub-band channel.
The master data streaming interface has an error and length sub-band channel.
Parameters:
All streaming interfaces will provide the standardized AXI streaming interface parameters:
**Parameter name ** **Description ** Default Type
C_DAT_DATA_WIDTH width of TDATA (see AXI spec) 32 for 4Gbps transport, 256 for 40Gbps transport integer (cardinal)
C_DAT_ID_WIDTH width of TID (see AXI spec) 4 integer (cardinal)
C_DAT_DEST_WIDTH width of TDEST (see AXI spec) 4 integer (cardinal)
C_LEN_DATA_WIDTH width of TDATA (see AXI spec) 16
integer (cardinal)
C_ERR_DATA_WIDTH width of TDATA (see AXI spec) 8 integer (cardinal)
The AXI lite interface provides the standardized AXI lite parameters:
**Parameter name ** **Description ** Default Type
C_BASEADDR AXI Base Address
integer (cardinal)
C_HIGHADDR
AXI High Address
integer (cardinal)
C_AXI_ADDR_WIDTH
AXI address bus width
32
integer (cardinal)
C_AXI_DATA_WIDTH AXI data bus width 32 integer (cardinal)
C_AXI_PROTOCOL AXI flavour AXI4LITE String
Register map:
General properties:
This block has mainly 3 function: It can compute length information through storing up a complete packet in a FIFO and counting bytes. It also handles width conversion. This is important in conjunction with the input arbiter for example as this block takes in 256bit AXI streams whereas the 10GGMAC provides 64bit interfaces. Finally, it can drop erroneous frames.