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10G MAC Interface with registers

Georgina Kalogeridou edited this page Jan 15, 2015 · 5 revisions

Name

nf10_10g_interface

Version

v1.20a

Type

pcore (HW)

Location

netfpga-10g/lib/hw/std/pcores/nf10_10g_interface_v1_20_a/

Interface Types

XAUI, AXI4-Stream

Busses

M_AXIS: Master AXI4-Stream (RX) bus, 64bit

S_AXIS: Slave AXI4-Stream (TX) bus, 64bit

S_AXI: Slave AXI4-Lite

M_AXIS_ERR: Master AXI4-Stream (ERR) bus, 0bit, [handshake only](Standard-IP-Interfaces)

Parameters

C_XAUI_REVERSE: Must be 1 for Port 0, 1, 2; 0 for Port 3. Please consult the schematic for more information

C_XAUI_CONFIGURATION: XAUI configuration vector. See [Xilinx XAUI core documentation](http://www.xilinx.com/products/intellectual-property/xaui.html) for more information.

C_XGMAC_CONFIGURATION: 10G Ethernet MAC configuration vector. See [Xilinx 10G Ethernet MAC core documentation](http://www.xilinx.com/products/ipcenter/DO-DI-10GEMAC.htm) for more information.

C_M_AXIS_DATA_WIDTH: Data width of the master AXI4-Stream (RX) bus. Must be 64

C_S_AXIS_DATA_WIDTH: Data width of the slave AXI4-Stream (TX) bus. Must be 64

C_BASEADDR: Base address value of the core.

C_HIGHADDR: High address value of the core.

Register map

0x0 : reset counters

0x4 : bad frames counter (from MAC side)

0x8 : good frames counter (from MAC side)

0xC : bytes send from MAC

0x10 : number of packets enqueued at the rx queues

0x14 : number of bytes enqueued at the rx queues

0x18 : number of packets dequeued at the rx queues

0x1c : number of bytes dequeued at the rx queues

0x20 : number of packets enqueued at the tx queues

0x24 : number of bytes enqueued at the tx queues

0x28 : number of packets dequeued at the tx queues

0x2c : number of bytes dequeued at the tx queues

0x30 : number of packets in the rx queue

0x34 : number of bytes in the rx queue

0x38 : number of packets in the tx queue

0x3c : number of bytes in the rx queue

0x40 : number of packets dropped at the rx queue

0x44 : number of bytes dropped at the rx queue

Description

This pcore is a combination of Xilinx [XAUI](http://www.xilinx.com/products/ipcenter/XAUI.htm) and [10G MAC](http://www.xilinx.com/products/ipcenter/DO-DI-10GEMAC.htm) IP cores, in addition to an AXI4-Stream adapter. Incoming XAUI signals from AEL2005 are firstly transformed into XGMII signals by Xilinx XAUI core. The XGMII signals are read in by Xilinx 10G MAC and finally transformed into AXI4-Stream. The TX side follows the exact same path but in the opposite direction.

There is one additional AXI4-Stream bus for transmitting bad_frame signal provided by Xilinx 10G MAC. For more information about NetFPGA Standard IP Interfaces, please see [here](Standard-IP-Interfaces).

Note : The current implementation doesn’t have synchronization (for clock domain crossing) for registers which interface with the MAC.

Licenses

To build a bistream with this core included, the end-user must obtain a license for the Xilinx 10G MAC. Universities can usually obtain a free license through the Xilinx University Program. Please follow the procedure as described in [Licensing](Licensing).

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