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davidva-cml edited this page Aug 11, 2016 · 25 revisions

NetFPGA-1G-CML Frequently Asked Questions

Part 1 - Operating Systems and Xilinx Tools

Q: Are there any particular OS and Xilinx packages I should have installed before I get started?

A: Yes. We have adopted Fedora 20 (x86_64) and Xilinx ISE Design Suite 14.6. Also, see the Getting Started Guide for a list of other packages that should be installed.

B. Note: in fact, the main concern that we have is as the kernel version. After several tests with Fedora versions (20, 21 and 22), several things were going on, causing the loss of time was too large. My experience with CentOS 7 - kernel 3.10.0-229.11.1.el7.x86_64 (on the site they indicate the version 4.14 as stable but CentOS, even in version 7, still maintains this kernel, probably for still being the most stable) is excellent, with all projects being created with no errors, and when it occurs (happens only when the iMPACT tool does not find the driver), there is a fix to help to correct this error. So, avoid getting stuck the suggested version because it cost for that reality testing, okay?

Q: What about Xilinx licenses?

A: In short, you'll need to have a Xilinx ISE/EDK license. The XC7K325T FPGA device is not one of the supported parts in the freely available Xilinx webpack. For more details see the Licensing page.

Word from our Xilinx project representative related to the ISE tool chain availability: "It will be available for some time, and there is commitment to continue to support it. You can't buy an ISE license by itself, but if you buy (or get a donation) of Vivado, you are entitled to an ISE license. It is already included with the Vivado license now. After the next version of Vivado is released in April, the plan is that ISE licenses will be available on request. This should only be an issue for completely new users, as all existing licenses for ISE will continue to work."

Q: Are there any other things I should do before I begin?

A: A good first step is to familiarize yourself with the board by going through the NetFPGA-1G-CML Reference Manual. When you're ready to begin checkout the Getting Started Guide.

Q: Why does my on-board JTAG stop working after a reboot?

A: You are most likely using an older version of the Digilent Adept software. Go to the Digilent website and install the Adept 2.16.1 Runtime (or later version) if you're on Linux or the Adept 2.16.1 System (or later version) if you're on Windows.

Part 2 - NetFPGA-1G-CML Codebase

Q: Have all previous NetFPGA-1G projects been ported to the NetFPGA-1G-CML Project?

A: The following NetFPGA-10G projects have been ported to NetFPGA-1G-CML: loopback_test, reference_nic, reference_switch_lite, reference_switch, and reference_router.

Q: Were the NetFPGA-1G-CML projects derived directly from the original NetFPGA-1G projects?

A: No. The NetFPGA-1G-CML projects were derived from the more recent NetFPGA-10G projects. The original NetFPGA-1G projects were organized differently and were developed using Fedora-13 and Xilinx 10.1. The NetFPGA-1G-CML projects have been developed using Fedora-20 and Xilinx ISE/EDK 14.6, as mentioned in Part 1 - Operating Systems and Xilinx Tools.

Q: Does the 7-series FPGA support the CAM generator used on the Virtex-5?

A: Yes, it does now. The CAM generator, as provided by Xilinx, doesn't support the Kintex7 device on the NetFPGA-1G-CML. However, we have provided patches for it that will allow it to work with the Kintex7. Please see the README file in the reference_switch_nf1_cml and reference_router_nf1_cml projects.

Q: How can I port projects from the NetFPGA-10G to the NetFPGA-1G-CML?

A: This isn't an easy question to answer. Most of the NetFPGA IP is generic IP that will work on any FPGA, however, some of the IP contains code that is specific for an FPGA family. For example, the NetFPGA-10G DMA core contains a specific version of the built-in Virtex5 PCIe block. The Kintex7 on the NetFPGA-1G-CML contains a different built-in PCIe block and so the DMA core had to be ported to the new FPGA family. Another example was the CAM generator. Xilinx only officially supports it up to 5 Series of FPGAs. We have successfully patched it to work with 7 series parts. With that being said, a lot of the IP didn't require changes and could be used as is.

After you identify the IP that has FPGA family dependent code and have finished porting them, you can then create projects for the NetFPGA-1G-CML. I find the easiest and least problematic way of porting projects is to start with a new design in XPS. Starting new means you don't have to deal with using old versions of Xilinx IP that my have problems or compatibility issues. Add in each required core using the old project as a reference. It may be slow work to get the initial design in place, but you can use the new design as a reference for any other designs that follow the same general project layout. For example, after we ported the reference nic to the NetFPGA-1G-CML, we used it as a starting point for porting over each of the other reference designs.

The trickiest part is making sure that all of the pcore parameters are correctly set for each of the IP when you add them to the project. A good way of checking is to compare the system.mhs files from the original project and the ported project.

Part 3 - NetFPGA-1G-CML Hardware

Q: Does the NetFPGA-1G-CML have to be installed into a host's PCIe socket for development?

A: No. The NetFPGA-1G-CML can be used in either a stand-alone mode or installed into a host PCIe slot. The stand-alone mode requires power from an ATA power connector and cables for the JTAG connection and UART connection via the PMOD connector. See photos below.

NetFPGA 1G CML PCIe Slot Mode
Figure 1 - NetFPGA 1G CML Standalone Mode

NetFPGA 1G CML Standalone Mode
Figure 2 - NetFPGA 1G CML PCIe Mode

Q: Does the PCIe mode require a specific PCIe driver?

A: Yes. The specific Linux driver to access the card while in PCIe mode is located at NetFPGA-1G-CML/projects/reference_nic_nf1_cml/sw/host/driver. Run the Makefile while in that directory make. The Makefile will create the nf10.ko file. The nf10.ko can be installed by running the following command sudo insmod nf10.ko.

Note: The NetFPGA card must be loaded with correct bit stream to operate in PCIe mode. The computer will need to be restarted after loading the bitstream. After restarting the computer, run the command lspci and the Xilinx card should be visible with VendorID 0x10ee and ProductID 0x4244.

Q: How should the UART be configured for testing the NetFPGA 1G CML board?

A: CML has adopted Minicom for serial communication with the NetFPGA-1G-CML board. The UART is accessed using a PmodUSBUART and is seen in the pictures connected to the PMOD connector.

Q: How is the board tested using the loopback test?

A: The loopback test is located in the projects directory, loopback_test_nf1_cml.

  • The pcores must first be created by running make in the netfpga root directory, NetFPGA-1G-CML-live.
  • Change directories to /NetFPGA-1G-CML-live/projects/loopback_test_nf1_cml and run make.
  • Connect the JTAG programming cable to JTAG header and PmodUARTUSB module with USB cable to the PMOD connector.
  • Connect one Ethernet cable between ETH1 and ETH2 and another between ETH3 and ETH4.
  • After the make has successfully completed, run make download.
    • This will download bitfile located in /projects/loopback_test_nf1_cml/bitfiles into the FPGA.
  • Upon completion the Minicom terminal should display the test configuration menu as shown in Figure 3.
  • Figure 4 shows the board setup for loopback testing.

Minicom Screen
Figure 3 - Minicom Screen loopback-test-nf1-cml

NetFPGA 1G CML Loopback Test
Figure 4 - NetFPGA 1G CML Loopback Test

Q: How do I correct the following error?
ERROR:EDK - BlackBox Netlist file nf1_cml_interface_v1_00_a/netlist/trimac_lite.ngc not found

A: Go to the NetFPGA-1G-CML-live directory and run the following command 'make cml_cores'.

Q: Is there a fix for reference_switch_lite_nf1_cml and reference_switch_nf1_cml Python hardware tests failing on the first run?

A: Yes, The issue is associated with a service called 'avahi' present on Fedora and Ubuntu which sends out MDNS packets. The service is not required and can be disabled by performing the following for the specific OS:

Fedora:  [perform] sudo systemctl disable avahi-daemon.service  then rebooting  
Ubuntu:  [follow instructions]  

Q: Does connecting to a design via XMD using the supplied USB cable require a special plug-in for connecting to a Microblaze debug module?

A: Yes, type the following command at the XMD prompt: XMD% connect mb mdm -cable type xilinx_plugin modulename digilent_plugin

Q: Running "make cores" from the repository root directory generates a series of errors. How can I fix this?

A: The "make cores" rule has been changed to "make cml_cores" for the NetFPGA-1G-CML.

Q: How can I fix an error while running "make" in a project directory indicating the MPD file cannot be found?
ERROR:EDK - IPNAME: nf1_cml_interface, INSTANCE: nf1_cml_interface_0 - cannot find MPD for the pcore

A: Go to the <project_name>/lib folder and perform an 'ls -l'. The contrib and std folders should be symbolic links, as shown below:

lrwxrwxrwx 1 name name   23 Apr 23 10:03 contrib -> ../../../lib/hw/contrib   
lrwxrwxrwx 1 name name   19 Apr 23 10:03 std -> ../../../lib/hw/std  

Extracting the code on a Windows system causes the symbolic links to convert to regular files. This will result in EDK not finding the MPD for the pcores. Convert these folders to symbolic pointing to /lib/hw/ as shown above.

Q: How do I select the MAC used in the nf1_cml_interface and are there license requirements and limitations?

A: The MAC is selected by setting the C_MAC_SEL parameter under the nf1_cml_interface instantiation in system.mhs file. A Xilinx license is required to build either the TRIMAC_LITE or TRIMAC MAC. The UCSD MAC is the default and only works at 1G speeds (not 10 or 100).

C_MAC_SEL = 0 : Xilinx tri-mode Ethernet MAC with external registers (TRIMAC_LITE) C_MAC_SEL = 1 : Xilinx tri-mode Ethernet MAC with internal registers (TRIMAC) C_MAC_SEL = 2 : UCSD Ethernet MAC (default)

Q: Hardware tests occasionally fail with a message saying the received packet was an unexpected length of 62. How do I fix this?

A: Interfaces using IPv6 may periodically send Router Solicitation packets which have a length of 62 bytes. If you are using a dual-port NIC for tests (e.g. reference_nic_nf1_cml project), the system may send these router solicitation packets out of the dual NICs while the test is running, which will cause the test to fail. You can verify that this is the cause on your system by analyzing the dual NIC interfaces with Wireshark and looking for Router Solicitation packets.

One way to solve this problem is by disabling IPv6 globally for all interfaces with the command:

$ sudo sysctl -w net.ipv6.conf.all.disable_ipv6=1

Q: The Reference Router GUI build fails with: make: *** No rule to make target ../reg_defines.h ', needed by src/org/netfpga/backend/'. Stop. How do I fix this?

A: Run make regs from projects/reference_router_nf1_cml/hw/ before building the GUI.

Q: After loading a reference project bitstream and rebooting, the NetFPGA-1G-CML does not enumerate on the PCIe bus (i.e. "lspci | grep Xilinx" does not return anything). How can I fix this?

A: Some users have found that the reference project bitstreams on the "master" branch of the repository don't always work properly with PCIe 3.0 slots. For this reason, we updated the DMA on the "develop" branch of the repository to a version that should properly handle PCIe 3.0. If you are having enumeration issues, please try checking out the "develop" branch and using the reference project bitstreams found there.

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