Register IO by Muhammad Shahbaz

Name

reg_io

Location

contrib-projects/reg_io

IP Cores

• NetFPGA-10G Specific cores
  • dma
  • nf10_reg_io
    • driver
• Xilinx AXI Peripheral
  • axi_interconnect
  • axi_uartlite
• Microblaze Subsystem
  • MicroBlaze
  • lmb_v10
  • lmb_bram_if_cntlr
  • bram_block
  • proc_sys_reset
  • clock_generator

Software

• NF10 Register IO

Description

This is a Register IO sample project using the DMA engine. It includes many of the standard NetFPGA modules (microblaze, AXI interconnect, nf10_interface), but in addition it uses a new pcore that demonstrates the use of generic register and table modules. These modules are flexible in nature and should be used, in a pcore, where register or table access is required via AXI bus. This project also shows how custom IP drivers - software attached to a particular pcore - are used inside a design.

Block Diagram

Steps to implement reg_io

1. Run the project makefile to implement and generate bitstream

2. Program the FPGA

3. Reboot the system

4. Build and load the driver under the contrib-projects/nic/sw/host/drivers

   make insmod nf10.ko

Read(s) and Write(s)

using nf10_reg_io utility

Run the nf10_reg_io utility under the contrib-projects/reg_io/sw/host/nf10_reg_io directory. This will perform simple registers and table read(s)/write(s).

./nf10_reg_io

This utility uses functions provided in the associated driver for the nf10_reg_io core. For more information about the drivers and their usage see Register System.

using wraxi and rdaxi utilities

Read(s)/write(s) can also be performed using the 'wraxi' and 'rdaxi' utilities. Build the 'wraxi' and 'rdaxi' located under the contrib-projects/nic/sw/host/apps directory

make

Registers

Four registers are instantiated in the design (Register [0-4]). Each register is mapped to different addresses (shown below) with varying access permissions.

Memory Map

bar0 base address = 0x78220000

bar0 + 0x00 --[WO]-> Register 0  
bar0 + 0x04 --[WO]-> Register 1  
bar0 + 0x08 -<[RW]-> Register 2  
bar0 + 0x0C -<[RW]-> Register 3  
bar0 + 0x10 -<[RO]-- Register 2  
bar0 + 0x14 -<[RO]-- Register 3  
bar0 + 0x18 -<[RO]-- Register 0  
bar0 + 0x1C -<[RO]-- Register 1

• --[WO]->, means write only registers
• -<[RW]->, means read/write registers
• -<[RO]--, means read only registers

read(s)/write(s)

./wraxi 78220000 12345678
./rdaxi 78220000

Tables

The table consists of 4 Cells (i.e. rows) and each Cell has 4 columns. In order to write a Cell in a table, you first have to fill up the columns inside the Cell and then update the write Row Index register. For reads, follow this in reverse.

Memory Map

bar1 base address = 0x78200000

bar1 + 0x00 -<[RW]-> Cell[Current Row Index][0]  
bar1 + 0x04 -<[RW]-> Cell[Current Row Index][1]
bar1 + 0x08 -<[RW]-> Cell[Current Row Index][2]
bar1 + 0x0C -<[RW]-> Cell[Current Row Index][3]
bar1 + 0x10 -<[RW]-> Current Row Index (Write)
bar1 + 0x14 -<[RW]-> Current Row Index (Read)

• -<[RW]-> , means read/write registers

read(s)/write(s)

./wraxi 78200000 12340001 # Write 1st column in the Cell
./wraxi 78200004 12340002 # Write 2nd column in the Cell
./wraxi 78200008 12340003 # Write 3rd column in the Cell
./wraxi 7820000C 12340004 # Write 4th column in the Cell
./wraxi 78200010 2        # Write Current Row at index 2 in the table

./wraxi 78200014 2        # Read Current Row at index 2 from the table
./rdaxi 78200000          # Read 1st column in the Cell
./rdaxi 78200004          # Read 2nd column in the Cell
./rdaxi 78200008          # Read 3rd column in the Cell
./rdaxi 7820000C          # Read 4th column in the Cell