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NetFPGA 1G CML nf1_cml_interface_v1_00_a
nf1_cml_interface
v1.00a
pcore (HW)
lib/hw/contrib/pcores/nf1_cml_interface_v1_00_a
AXI4-Stream, AXI-Lite, RGMII
M_AXIS: Master AXI4-Stream (RX) bus, 8 bit minimum
S_AXIS: Slave AXI4-Stream (TX) bus, 8 bit minimum
| Parameter | Description |
|---|---|
| C_MAC_SEL | Select which MAC implementation to use. 0: TRIMAC Lite, 1: TRIMAC, 2: UCSD Gig MAC |
| C_INCLUDE_IDELAYCTRL | All for 1G ports share the IDELAYCTRL between them. Only one of the instantiated ports may include the IDELAYCTRL. |
| C_M_AXIS_DATA_WIDTH | Width of AXIS Master (RX) bus. Can be 8, 32, 64, 256 |
| C_S_AXIS_DATA_WIDTH | Width of AXIS Slave (TX) bus. Can be 8, 32, 64, 256 |
| The following parameters are only available with the TRIMAC Lite and UCSD MAC: |
| Parameter | Description | Values |
|---|---|---|
| C_TX_EN | Enable TX by default? | 1=Yes, 0=No |
| C_TX_FCS_EN | Disable automatic padding and checksum generation by default | 1=Yes, 0=No |
| C_TX_JUMBO_EN | Enable TX jumbo packets by default | 1=Yes, 0=No |
| C_RX_EN | Enable RX by default | 1=Yes, 0=No |
| C_RX_FCS_EN | Pass on the RX frame checksum by default | 1=Yes, 0=No |
| C_RX_JUMBO_EN | Enable RX jumbo packets by default | 1=Yes, 0=No |
The following parameters are only available with the TRIMAC Lite:
| Parameter | Description | Values |
|---|---|---|
| C_TX_VLAN_EN | Enable TX VLAN packets by default | 1=Yes, 0=No |
| C_TX_FC_EN | Enable TX flow control by default | 1=Yes, 0=No |
| C_TX_HD_EN | Enable TX half duplex by default | 1=Yes, 0=No |
| C_TX_IFG_ADJUST_EN | Enable interframe gap alternate value by default | 1=Yes, 0=No |
| C_TX_MAX_FRAME_EN | Enable maximum transmittable frame size specified by TX Max Frame Size register by default | 1=Yes, 0=No |
| C_TX_MAX_FRAME_SIZE | Default TX Max Frame Size register value | 1518 - 65535 |
| C_TX_PAUSE_MAC_ADDR | Transmitter pause frame source address | |
| C_TX_RESET | Hold TX in reset by default? | 1=Yes, 0=No |
| C_RX_VLAN_EN | Enable RX VLAN packets by default | 1=Yes, 0=No |
| C_RX_FC_EN | Enable RX flow control by default | 1=Yes, 0=No |
| C_RX_HD_EN | Enable RX half duplex by default | 1=Yes, 0=No |
| C_RX_PROMISCUOUS_EN | Enable RX promiscous mode by default | 1=Yes, 0=No |
| C_RX_LEN_TYPE_CHK_DIS | Disable length/type error check by default | 1=Yes, 0=No |
| C_RX_CONTROL_LEN_CHK_DIS | Disable checks on control frame lengths by default | 1=Yes, 0=No |
| C_RX_MAX_FRAME_EN | Enable maximum receivable frame size specified by the RX Max Frame Size register by default | 1=Yes, 0=No |
| C_RX_MAX_FRAME_SIZE | Default RX Max Frame Size register value | 1518 - 65535 |
| C_RX_PAUSE_MAC_ADDR | Receiver pause frame source address | |
| C_RX_RESET | Hold RX in reset by default? | 1=Yes, 0=No |
The TRIMAC uses registers from the Tri-Mode Ethernet MAC. Please see LogiCORE IP Tri-Mode Ethernet MAC v5.5 Product Guide for more details.
The TRIMAC Lite and UCSD MAC both use a separate set of registers. However, the only valid bits for the UCSD mac are the TX_EN, TX_FCS_EN, TX_JUMBO_EN, RX_EN, RX_FCS_EN, and RX_JUMBO_EN.
| Offset | Name | Description |
|---|---|---|
| 0x00 | RX_CTRL | RX control register |
| 0x08 | RX_PAUSE_HI | RX pause control address high bits |
| 0x0c | RX_PAUSE_LO | RX pause control address low bits |
| 0x10 | TX_CTRL | TX control register |
| 0x18 | TX_PAUSE_HI | TX pause control address high bits |
| 0x1c | TX_PAUSE_LO | TX pause control address low bits |
| Bits | Name | Default Value | Description |
|---|---|---|---|
| 31:16 | RX_MAX_FRAME_SIZE | C_RX_MAX_FRAME_SIZE | Receiver Max Frame Size |
| 15 | Reserved | ||
| 14 | RX_MAX_FRAME_EN | C_RX_MAX_FRAME_EN | Receiver Max Frame Enable |
| 13:12 | Reserved | ||
| 11 | RX_PROMISCUOUS_EN | C_RX_PROMISCUOUS_EN | Promiscuous Mode |
| 10 | Reserved | ||
| 9 | RX_CONTROL_LEN_CHK_DIS | C_RX_CONTROL_LEN_CHK_DIS | Receiver Control Frame Length Check Disable |
| 8 | RX_LEN_TYPE_CHK_DIS | C_RX_LEN_TYPE_CHK_DIS | Receiver Length/Type Error Check Disable |
| 7 | Reserved | ||
| 6 | RX_HD_EN | C_RX_HD_EN | Receiver Half-Duplex |
| 5 | RX_FC_EN | C_RX_FC_EN | Receiver Flow Control Enable |
| 4 | RX_JUMBO_EN | C_RX_JUMBO_EN | Receiver Jumbo Frame Enable |
| 3 | RX_FCS_EN | C_RX_FCS_EN | Receive In-Band FCS Enable |
| 2 | RX_VLAN_EN | C_RX_VLAN_EN | Receive VLAN Enable |
| 1 | RX_EN | C_RX_EN | Receiver Enable |
| 0 | RX_RESET | C_RX_RESET | Receiver Reset |
| Bits | Name | Default Value | Description |
|---|---|---|---|
| 31:16 | Reserved | ||
| 15:0 | RX_PAUSE_MAC_ADDR_HI | C_RX_PAUSE_MAC_ADDR_HI | Receiver Pause Frame Source Address bits 47 - 32 |
| Bits | Name | Default Value | Description |
|---|---|---|---|
| 31:0 | RX_PAUSE_MAC_ADDR_LO | C_RX_PAUSE_MAC_ADDR_LO | Receiver Pause Frame Source Address bits 31 - 0 |
| Bits | Name | Default Value | Description |
|---|---|---|---|
| 31:16 | TX_MAX_FRAME_SIZE | C_TX_MAX_FRAME_SIZE | Transmitter Max Frame Size |
| 15 | Reserved | ||
| 14 | TX_MAX_FRAME_EN | C_TX_MAX_FRAME_EN | Transmitter Max Frame Enable |
| 13:9 | Reserved | ||
| 8 | TX_IFG_ADJUST_EN | C_TX_IFG_ADJUST_EN | Interframe Gap Adjust Enable |
| 7 | Reserved | ||
| 6 | TX_HD_EN | C_TX_HD_EN | Transmitter Half-Duplex |
| 5 | TX_FC_EN | C_TX_FC_EN | Transmitter Flow Control Enable |
| 4 | TX_JUMBO_EN | C_TX_JUMBO_EN | Transmitter Jumbo Frame Enable |
| 3 | TX_FCS_EN | C_TX_FCS_EN | Transmit In-Band FCS Enable |
| 2 | TX_VLAN_EN | C_TX_VLAN_EN | Transmit VLAN Enable |
| 1 | TX_EN | C_TX_EN | Transmitter Enable |
| 0 | TX_RESET | C_TX_RESET | Transmitter Reset |
| Bits | Name | Default Value | Description |
|---|---|---|---|
| 31:16 | Reserved | ||
| 15:0 | TX_PAUSE_MAC_ADDR_HI | C_TX_PAUSE_MAC_ADDR_HI | Transmitter Pause Frame Source Address bits 47 - 32 |
| Bits | Name | Default Value | Description |
|---|---|---|---|
| 31:0 | TX_PAUSE_MAC_ADDR_LO | C_TX_PAUSE_MAC_ADDR_LO | Transmitter Pause Frame Source Address bits 31 - 0 |
This pcore gives you the option of using several different ethernet MACs. The most fully featured MAC is the TRIMAC. It allows operation in 10/100/1000 and lots of configuration of features. TRIMAC Lite allows lots of configuration, but will only opperate at the 1G speed. Both the TRIMAC and TRIMAC Lite require a license from Xilinx. The UCSD MAC is completely open source but it doesn't provide as many of the features as the TRIMAC cores. It only runs at 1G speeds. The only features the UCSD MAC has is the ability to check and generate frame checksums and allow or disallow jumbo frames.
To build a bistream with either of the TRIMAC cores included, the end-user must obtain a license for the Xilinx Tri-mode Ethernet MAC. Universities can usually obtain a free license through the Xilinx University Program. Please follow the procedure as described in Licensing.