pcore (HW) + driver (SW)
S_AXI: Slave AXI4-Lite
See Xilinx AXI Ethernet Lite. Note that only MDIO related registers have effect since all other logics are trimmed.
Reuse is good. To program AEL2005 with MDIO, we reuse the MDIO engine that is already shipped with Xilinx AXI Ethernet Lite IP core. This core is a derived work of the original Xilinx IP, minus ALL the MAC functionality, such as ping-pong buffer, client side AXI stream, and the MAC itself. We reuse the MDIO engine hardware (HDL) and the software (emaclite driver).
As one modification we have add to Xilinx AXI Ethernet Lite is IEEE 802.3 Clause 45 capability (i.e. 10 Gigabit Ethernet MDIO) in addition to Clause 22. You may find the embedded software in projects loopback_test and loopback_test_1g useful in terms of demonstrating reading/writing AEL2005 MDIO registers.