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MDIO Engine

Georgina Kalogeridou edited this page Jan 15, 2015 · 4 revisions

Name

nf10_mdio

Version

v1.00a

Type

pcore (HW) + driver (SW)

Location

netfpga-10g/lib/hw/std/pcores/nf10_mdio_v1_00_a/

netfpga-10g/lib/sw/std/drivers/nf10_mdio_v1_00_a/

Interface

MDIO, AXI4-Lite

Bus

S_AXI: Slave AXI4-Lite

Parameter

None

Register map

See Xilinx AXI Ethernet Lite. Note that only MDIO related registers have effect since all other logics are trimmed.

Description

Reuse is good. To program AEL2005 with MDIO, we reuse the MDIO engine that is already shipped with Xilinx AXI Ethernet Lite IP core. This core is a derived work of the original Xilinx IP, minus ALL the MAC functionality, such as ping-pong buffer, client side AXI stream, and the MAC itself. We reuse the MDIO engine hardware (HDL) and the software (emaclite driver).

As one modification we have add to Xilinx AXI Ethernet Lite is IEEE 802.3 Clause 45 capability (i.e. 10 Gigabit Ethernet MDIO) in addition to Clause 22. You may find the embedded software in projects loopback_test and loopback_test_1g useful in terms of demonstrating reading/writing AEL2005 MDIO registers.

External references

  1. AXI Spec: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.amba/index.html

  2. Xilinx AXI Ethernet Lite: http://www.xilinx.com/support/documentation/ipembedprocess_peripheralnetwork_axi_ethernetlite.htm

  3. IEEE 802.3: http://standards.ieee.org/about/get/802/802.3.html

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