NetFPGA 1G CML Ethernet Interface Loopback Test

Name

loopback_test_nf1_cml

Location

projects/loopback_test_nf1_cml

IP Cores

• NetFPGA Specific cores
  • nf1_cml_interface_v1_00_a
  • mdio_ctrl_v1_00_a
  • nf10_axis_gen_check_v1_00_a
  • dma_v1_20_a
• Xilinx IP
  • MicroBlaze
  • mdm
  • axi_uartlite
  • axi_timebase_wdt
  • proc_sys_reset
  • clock_generator
  • axi_interconnect
  • lmb_v10
  • lmb_bram_if_cntlr
  • bram_block

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Description

This example project shows the usage of the 1G Ethernet interfaces on NetFPGA-1G-CML board. Outside the FPGA, the interfaces are paired up using CAT-5e/CAT-6 Ethernet cables. Inside the FPGA, two packet generator/checkers are connected to two out of the four 1G interfaces while the remaining two interfaces are looped back together. MicroBlaze subsystem will poll the statistics out of the packet generator/checkers and output them through the UART interface.

Usage

1. Build the bitfile. Please read the README under projects/loopback_test_nf1_cml/ for detailed instructions. This process will take up to an hour. However, you may skip this step if you have a pre-built bitfile available.
2. Connect Port 0 to Port 1, and Port 2 and Port 3 on the NetFPGA-10G board using CAT-5e/CAT-6 Ethernet cables.
3. Connect the supplied PmodUSBUART to the top row of PMOD port JB. Connect the PmodUSBUART using the supplied USB cable to the PC. Open a terminal (PuTTY on Windows or minicom/gtkterm on Linux) and listen to your serial port.
4. Download the bitfile to the FPGA and follow the instructions on the terminal (see the screenshot below).

Block Diagram