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DMA v2.10
dma | naas_dma
v2.10a
Marco Forconesi (marco.forconesi_at_cl.cam.ac.uk)
pcore (HW)
lib/hw/std/pcores/dma_v2_10_a/
AXI4-Stream
AXI4-Lite
PCIe
M_AXIS: Master AXI4-Stream (RX) bus, 64bit
S_AXIS: Slave AXI4-Stream (TX) bus, 64bit
M_AXI: Master AXI4-LITE bus, 32bit address, 32 bit data
S_AXI: Slave AXI4-LITE bus, 32 bit address, 32 bit data
C_BASEADDR: Base address for the S_AXI interface
C_HIGHADDR: High address for the S_AXI interface
There are 8 AXI registers (32 bit) implemented for test purposes. One can write any data into them and then read it out later. They do not affect the operation of the DMA in any way. These registers are located at: C_BASEADDR...C_BASEADDR+7
This module is a DMA engine that interconnects the hardware systems running on the FPGA with the software components in the host computer. The DMA engine has two AXI4-Stream interfaces, one of which is a slave interface for sending packets from the card to the host and the other master interface is where packets sent by the host are received and pushed to the FPGA fabric. Packet metadata (e.g. length, source and destination) is encoded in the TUSER signal of the AXI4-Stream bus. The AXI4-Lite master interface exposes the registers of every pcore to the host in order to read and/or write them by using a user level application. A (linux) device driver ref a driver running on the host works orchestrated with the DMA and is in charge of delivering and sending the packets to each interface: nf0, nf1, etc.