AXI transaction grammar

AXI Transaction Grammar

In BNF, the generic AXI grammar is as follows:

**<AXI4_Stream>** ::= ( <AXI4_Stream_data> | <delay_spec> "\n" )+  

**<AXI4_Lite> ** ::= ( <AXI4_Lite_data> | <delay_spec> "\n" )+  

**<delay_spec> ** ::= "@" <integer>                 ; absolute time spec (nanoseconds)
                    | "+" <integer>                 ; relative time spec (nanoseconds)
                    | "*" <integer>                 ; relative time spec (cycle)    

**<AXI4_Stream_data>**   ::= <hex_integer> ","      ; TDATA value
                             <hex_integer> ","      ; TSTRB value
                             <hex_integer>          ; TUSER value  
                             <terminal>             ; TLAST value

**<AXI4_Lite_data>**     ::= <write_trans> ","      ; Write transaction data  
                             <read_trans>           ; Read transaction data  
                             <terminal>             ; Wait flag

<write_trans>            ::= "-, -, -"              ; No-op; XOR...  
                           | ( <hex_integer> ","    ; Write address (AWADDR)  
                               <hex_integer> ","    ; Write data (WDATA)  
                               <hex_integer> )      ; Write enables (WSTRB)

<read_trans>             ::= "-"                    ; No-op; XOR...   
                           | <hex_integer>          ; Read address (ARADDR)  

<terminal>               ::= ","                    ; !eop (AXI4 Stream), !wait (AXI4 Lite)  
                           | "."                    ; eop (AXI4 Stream), wait (AXI4 Lite)  

<integer> ::= <digit>+

<hex_integer> ::= <hex_digit>+  

<digit> ::= "0" | "1" | "2" | "3" | "4" | "5" | "6" | "7" | "8" | "9"

<hex_digit> ::= <digit> | "a" | "b" | "c" | "d" | "e" | "f"

General notes:

• Blank lines are ignored.
• Comments demarcated by '#' may be included, and will be ignored until end-of-line.
• Each line of data represents one clock tick with *VALID = '1'.
• <delay_spec>s specified in nanoseconds include an additional wait of up to one clock cycle, to guarantee that the next event happens at the beginning of a clock period.
• The grammar allows for cycle-accurate specification of AXI4 -Stream and -Lite links, but the timing actually seen depends on any reverse flow control applied by the design.

AXI4-Stream specific notes:

• Each AXI4-Stream file describes the flow of packets over a single AXI4-Stream link. A separate file is required for each interface in the design.
• First line of input data is not read until system reset is deasserted.
• TUSER data exists on each line, but typically should be zero on all cycles except for the first of each packet.
• All fields are mandatory.
• The width of hex values must be exactly correct for the respective vector in the design. Use leading zeros if required. Do not write vectors larger than what is present in the design. The example below shows an AXI-Stream grammar for a 64-bit link. Note that the width of TSTRB is 64 ÷ 8 = 8.
• Data are typically little-endian (as described in the 10GMac datasheet, ds201).
• Example packet:

2211ccbbaa998877, ff, 0000000000000000000000000000003c,
0045000866554433, ff, 00000000000000000000000000000000,  
0640000001002e00, ff, 00000000000000000000000000000000,  
a8c00101a8c075f7, ff, 00000000000000000000000000000000,  
0000500014000201, ff, 00000000000000000000000000000000,  
0250000000000000, ff, 00000000000000000000000000000000,  
00000000250c0020, ff, 00000000000000000000000000000000,  
0000000000000000, 0f, 00000000000000000000000000000000.

AXI4-Lite specific notes:

• Although the AXI4-Lite grammar reflects the possibility of committing both a read and a write transaction in the same cycle, note that whether this is actually possible or not depends on how the AXI Interconnect component is configured. As of this writing, the default behaviour is 'shared interconnect' — for the sake of device utilisation — meaning that only one operation can occur at any given moment.
• When a write transaction is not NO-OP (-, -, -), all three arguments (address, data, and byte-lane strobes) must be specified, valid hex values.
• When the terminal character specifies a wait, the transactor module will wait until it sees the write acknowledgement and/or data read returned by the AXI interconnect for this transaction, as indicated by the address fields of this transaction. This means that if you write to addresses A, B, C, D, A, with a wait only on the **fifth **write operation, the transactor will probably proceed onto the next line of transaction data when the write acknowledgement arrives for the first transaction (because it has the same address as the fifth) — i.e., not wait at all.
• Example transactions:

80000000, deadc0de, f, -       . # write to 0xdeadc0de to 0x80000000
-,        -,        -, 80000000. # read from same address, after write completes.