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Encap
nf10_encap
v1.00a
Yilong Geng (Stanford University)
pcore (HW)
netfpga-10g/lib/hw/contrib/pcores/nf10_encap_v1_00_a/
AXI4-Stream & AXI4-Lite
S_AXIS: Slave AXI4-Stream bus, Variable width
M_AXIS: Master AXI4-Stream bus, Variable width
S_AXI: AXI4-Lite configuration register bus
C_AXIS_DATA_WIDTH: Data width of the AXI4-Stream bus.
C_AXIS_TUSER_WIDTH: Data width of the TUSER field.
TOTAL_LENGTH_POS: The positon of the Total_Packet_Length field in TUSER.
SRC_PORT_POS: The position of the Source_Port field in TUSER.
DST_PORT_POS: The position of the Destination_Port field in TUSER.
Y = 0,1,2,3 represents 4 groups of configuration registers. Each group for one output Ethernet port.
Base Address+
0xY0: 32-bit source IP address
0xY1: 32-bit destination IP address
0xY2: The lower 32 bits of the source MAC address
0xY3: [The lower 16 bits of the destination MAC address, The higher 16 bits of the source MAC address]
0xY4: The higher 32 bits of the destination MAC address
0x40: [8-bit bitwise encap_ports, 8-bit IP "type of service" field, 8-bit IP "ttl" field, 8-bit IP "protocol" field]
This module is a part of the tunneling Openflow switch data path. It enables tunneling by adding an IP header according to the configuration registers.