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SRAM FIFO

sdamico edited this page Aug 2, 2012 · 3 revisions

Name

nf10_sram_fifo

Version

v1.00a

Author

Sam D'Amico (sdamico_at_stanford.edu)

Type

pcore (HW)

Location

netfpga-10g/lib/hw/std/pcores/nf10_sram_fifo_v1_00_a/

Interface Types

AXI4-Stream

Buses

S_AXIS_0: Slave AXI4-Stream bus, 256 Bit width

S_AXIS_1: Slave AXI4-Stream bus, 256 Bit width

S_AXIS_2: Slave AXI4-Stream bus, 256 Bit width

S_AXIS_3: Slave AXI4-Stream bus, 256 Bit width

M_AXIS_0: Master AXI4-Stream bus, 256 Bit width

M_AXIS_1: Master AXI4-Stream bus, 256 Bit width

M_AXIS_2: Master AXI4-Stream bus, 256 Bit width

M_AXIS_3: Master AXI4-Stream bus, 256 Bit width

Parameters

Register map

No registers are implemented for v1.00a.

Description

The function of this block is to dispatch packets from multiple input streams to a number of output streams, passing data through the QDR-II SRAM. Four large queues are implemented within this memory, which is divided into four equal sections, one for each queue. All input interfaces need to have the same bandwidth (and therefore width) as the output stream to ensure that maximum throughput can be achieved. To run at narrower bit-widths, use a stream converter module.

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