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Switch Output Port Lookup
mshahbaz edited this page Jan 22, 2013
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nf10_switch_output_port_lookup
Gianni Anitchi (gianni.antichi_at_iet.unipi.it)
Muhammad Shahbaz (muhammad.shahbaz_at_cl.cam.ac.uk)
pcore (HW)
netfpga-10g/lib/hw/std/pcores/nf10_switch_output_port_lookup_v1_10_a/
AXI4-Stream
AXI4-Lite
S_AXIS: Slave AXI4-Stream bus, Variable width
M_AXIS: Master AXI4-Stream bus, Variable width
S_AXI: Slave AXI4-Lite
C_AXIS_DATA_WIDTH: Data width of the AXI4-Stream bus.
C_USER_WIDTH: Data width of the TUSER field.
C_AXI_DATA_WIDTH: Data width of the AXI4-Lite bus.
C_BASEADDR: Base address value of the core.
C_HIGHADDR: High address value of the core.
0x0: number of hits
0x1: number of misses
For information on Learning CAM Switch visit, http://netfpga.org.