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Frequent Asked Questions

Georgina Kalogeridou edited this page Apr 7, 2015 · 2 revisions

Part 1 Operating Systems and Xilinx Tools

Q1: Are there any particular OS packages I should have installed before I get started?

A: Yes. Before you begin any development work, please read the Reference Operating System page.

Q2: Are there any other things I should do before I begin?

A: Please read the Reference Operating System page, which provides a guide to setting up a development machine and installing the tools in the Xilinx ISE Design Suite.

Word from our Xilinx project representative related to the ISE tool chain availability: "It will be available for some time, and there is commitment to continue to support it. You can't buy an ISE license by itself, but if you buy (or get a donation) of Vivado, you are entitled to an ISE license. It is already included with the Vivado license now. After the next version of Vivado is released in April, the plan is that ISE licenses will be available on request. This should only be an issue for completely new users, as all existing licenses for ISE will continue to work."

Q3: My USB JTAG cable doesn't work! What can I do?

A: It seems that Xilinx JTAG cable driver doesn't always play well with Fedora (and some other Linux distributions). Please refer to for installing a third-party driver.

Q4: Can I build the bitfile/run the simulation under Windows/Ubuntu/Fedora 15?

It is not officially supported and most of our development work is strictly under Fedora 14. Some small effort has been made to support windows, but we can't promise it will work, and we recommend avoiding it - particularly in classroom situations. All the same, if you find something that is broken and you can fix it, we'll accept a patch if we can (and it's appropriate.) We will document some fixes we found here too.

Fedora 15

  • Problem # 1: make cores fails in Fedora 15. Particularly, coregen fails when generating 10G MAC. You should be able to see the coredump in dmesg

  • Cause: coregen fails because a Xilinx tool (netgen) crashes due to the share library conflicts under Fedora 15

  • Solution:

  1. Go to ${XILINX}/bin/lin64/unwrapped/

  2. Rename netgen to netgen_real

  3. Create a new file "netgen" with the following content

export LD_PRELOAD=${XILINX}/lib/lin64/
DIR=`dirname $0`
echo Running: netgen "$@"
$DIR/netgen_real "$@" 
  • Problem # 2: synthesis fails in Fedora 15. Particularly, map fails when -logic_opt flag is turned on.

  • Cause: synthesis fails because a Xilinx tool (map) crashes due to the share library conflicts under Fedora 15

  • Solution:

  1. Go to ${XILINX}/bin/lin64/unwrapped/

  2. Rename map to map_real

  3. Create a new file "map" with the following content

export LD_PRELOAD=${XILINX}/lib/lin64/
DIR=`dirname $0`
echo Running: map "$@"
$DIR/map_real "$@" 
  • Reference:

Q5: How can I run PlanAhead on 64-bit Linux OS?

PlanAhead is provided with 32-bit binaries, and thus it requires that 32-bit OS libraries be available on a 64-bit OS. To resolve this issue on Fedora 14 64-bit OS, install the following 32-bit packages using 'yum':

* glibc.i686 
* ncurses-libs.i686
* libX11.i686
* libXext.i686
* libXtst.i686
  • References:

Part 2 NetFPGA-10G Codebase

Q1: When I try to run the main make file, I get a complaint about an old version of python. Why do I need a newer version than what's already installed?

A: Both simulations and regression tests depend on the library scapy, which itself requires a python 2.x interpreter version 2.5 or newer. Some operating systems, including Redhat EL 4 and 5, provide only python 2.4, which cannot be upgraded without breaking RHEL's own system management scripts.

There are 3rd party RPMs that provide suitable versions of python as documented here, here and here, amongst others. If there are dependency problems, or your local environment prevents you from installing 3rd party RPMs, you can download and install from source. If you don't have root on your own machine, python can be installed into your home directory. After unpacking the source tarball, run configure like so:

machine:~/Python-2.7.2$ ./configure --prefix=$HOME

Don't forget to include $HOME/bin in your path.

Q2: I'm getting an error, eg python-nf: No such file or directory. What's wrong?

A: You need to include netfpga-10g-dev/tools/scripts in your path. If your NetFPGA working directory is in your home directory, you can add this directory to your path:

$ export PATH=$PATH:~/netfpga-10g-dev/tools/scripts

Q3: Where can I locate mb-gcc? The Makefile throws out an error message when initializing the bitfile with embedded software.

A: $(XILINX_EDK)/gnu/microblaze/{Your OS}/bin/. Replace {Your OS} with lin or lin64. You may want to add it into your $(PATH). This is documented in Getting Started Guide - Section 3 Installation.

Q4: When I try to build the embedded software, I get a message about a 'bad ELF interpreter'. I'm running a 64-bit operating system.

A: The µBlaze binutils package is statically built, but still as 32-bit binaries. You need to install the 32-bit version of which, on Fedora, is provided in package glibc.i686.

Q5: At the last stage of building the bitfile of loopback_test project, bitgen throws out "ERROR:Bitgen:169" and won't let me go through.

A: It is likely that you do not have a valid 10G MAC license, or your license file is not installed correctly. A "Hardware Evaluation" or "Full" license will allow you to generate the bitfile, while "Design Linking" license (the default license that comes with ISE installation) only allows you to simulate the design. Please see Licensing page for how to obtain a valid license. Refer to Xilinx answer record database and support forum if you are not sure how to install a IP license.

During installation, the make script will generate the NGC netlist with coregen and put it into the IP library, along with other patching jobs. This process is not repeatable nor reversible. Hence, please make sure you have the correct license before installation. Once you change the license settings, you will need to clean up IP library before running "make install" again. The following commands can do the job:

Warning: These commands will erase any files you have created that are not yet added to your local repository! Back up sources that are important to you, and/or add them to your local index with git add.

cd netfpga-10g/lib/ && git clean -df .
cd netfpga-10g/ && make install

Q6: When I try to generate simulation HDL, I get warnings and/or errors similar to the following:

WARNING:EDK:2478 - The EDK simulation library specified does not currently  
exist. Make sure it exists at simulation time.

Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...  
ERROR:EDK:2951 -   
Unknown Tcl procedure ::hw_lmb_bram_if_cntlr_v2_10_b::check_iplevel_settings  

You probably haven't installed the required Xilinx non-distributable dependencies by executing make install in the source tree's root.

**Q7: **make install just produces an error, similar to the following:

host:~/netfpga-10g$ make install  
make: *** [pcores] Error 1

Make sure the environment variable $XILINX_EDK is set to the correct value.

Windows users: Set this variable in System Properties->Advanced (tab)->Environment Variables->System Variables to the appropriate Windows path (typically something like C:\Xilinx\12.3\ISE_DS\EDK).

Cygwin users: Cygwin make requires Unix paths. Add the following to your .bashrc:

export XILINX_EDK=$(cygpath -u "$XILINX_EDK")

Q8: Why are so many Xilinx pcores copied from the EDK installation directory? Why are there no pcores listed under EDK Install in the IP catalogue?

A: The EDK Install section of the IP catalogue is empty because the Virtex 5TXT family of devices are not officially supported by EDK. The root make install process copies the pcores required for the NetFPGA 10g project into the project repository with modified MPD descriptions so they can be used. If you need something from the standard IP library, compare the differences between the distributed and local MPD files, and replicate them for the core you want to use.

NB: be sure to consider whether a particular pcore makes use of instantiated primitives not present on the Virtex 5TXT family of devices, and take appropriate steps as required.

Q9: The shell seems to become unresponsive when I type make. There is a lone process 'cmd' in Process Explorer that never terminates. (Windows/Cygwin)

Q10: I get a Microsoft Visual C++ runtime error when iSim first starts (during elaboration). iSim then terminates. (Windows/Cygwin)

Q11: make terminates with a Command not found error.(Windows/Cygwin)

*** Make sure you have the NF10_CYGWIN environment variable defined. ***

Building and simulating under Cygwin is not officially supported, but it known to work provided the required support is present in the project Makefile. Look at the Makefile for the reference_nic project for an example. A brief summary of what this support does, when the NF10_CYGWIN environment variable is defined:

  • The NT edition of EDK 13.x sets the $(SHELL) variable to CMD, which is incompatible with the Cygwin port of make, and needs to be reset to /bin/sh.
  • There is some conflict between bash (at least) and the simulation executable - possibly something to do with the process environment (such as Unix paths in $PATH). $(SIM_CMD) needs to be tweaked such that the simulator is launched in a CMD environment.
  • Whereas earlier versions of EDK simgen produced build scripts named *.sh, irrespective of OS — and despite EDK 13.1 documentation to the contrary — simgen produces *.cmd scripts under NT EDK 13.x. Any references to such scripts need to be set appropriately, depending on the build environment.

Q12: How to insert a new pcore or user defined Pcore into the NetFPGA infrastructure?

A: Please refer to "section 7 implementation" on the presentation, that gives some details about inserting modules in EDK environment. Try to download the presentation (ctrl+s), if it has difficulty loading. If you have your module and is axi compliant, it is well and good. Else if you want to start your pcore/module from scratch using this script.

Q13: How is the AEL2005 programmed? I am looking for information about the AEL2005 PHY. Where can I find the datasheet?

A: The AEL2005 is programmed by the Microblaze through the MDIO. The actual AEL2005 datasheet is available from NetLogic (now broadcom) under an NDA. The original AEL2005 code for NetFPGA-10G was taken from an open-source driver for a (not sure) Mellanox card - we use the same programming sequence to setup the AEL2005.

Q14: How to work with the Test infrastructure of NetFPGA projects?

A: NetFPGA-10G reference projects (nic, switch,switch_lite, router) have an integrated test infrastructure based on python. Please find the details below:

wiki for simulation infrastructure:

wiki for HW test infrastructure:

Part 3 NetFPGA-10G Hardware

Q1: I get strange behaviour, e.g. the production test fails on a card that should be good. The system runs very hot.

A: The NetFPGA card has numerous high-speed, high-power parts that naturally run quite hot (hence the many heatsinks.) Be sure that there is adequate airflow around the card, especially if the NetFPGA card is installed next to another hot-running card (eg a 10g Ethernet card.) You may need to consider adding extra case fans.

As a simple diagnostic, you can check the internal temperature of the FPGA using iMPACT. Connect a JTAG cable, initialise the chain, and perform a 'ReadIDCode' operation. iMPACT should give an indication of the current and maximum temperature of the FPGA device. Note:

  • the specified temperature range for this FPGA is 0°C to 85°C (32°F to 185°F). Outside of this range, FPGA timing characteristics are not guaranteed, and therefore unexpected and inconsistent behaviour may result. Significantly outside of this range, the device's longevity can shortened, or could even become damaged.
  • that power consumption (and therefore heat) can be very dynamic, depending on what is loaded into the FPGA, and what that image is doing. Ambient temperature also affects internal temperature. You therefore need to allow for some margin to ensure reliable operation.

Q2: The production test passes everything except the physical layer tests, though I'm sure they should be okay.

A: If the SFP+ cables are (re)plugged after the production bitstream has loaded, the physical layer devices are not properly reset. This is a deliberate compromise owing to space constraints within the FPGA. If the physical layers fail the production test, try reprogramming the FPGA and retesting. See "Can I reprogramme the FPGA without rebooting my OS?"

Q3: Can I reprogramme the FPGA without rebooting Linux?

Yes: before you reprogramme the FPGA, save the PCI configuration space with save then, after the FPGA is programmed, restore the PCI configuration with restore.

Q4: Why wont my motherboard power-down (e.g. from "sudo halt") when the NF10 card is inserted?

A: The NF10 card at revision 4 connects the PCIe signal WAKE#_B11 to the FPGA through 0 ohm resistor R13. When the power to the FPGA is removed, the voltage is low-enough to trigger the WAKE motherboard system function (as in wake-on-LAN). Future revisions of NF10 may remove (or not stuff) R13 which would prevent this "self-waking" behavior.

Q5: How to configure minicom for UART testing in production test?

A: We have seen that the users prefer to use different ports (some use serial others use usb with serial adapters) to connect to serial port on NetFPGA board. So in 4.8.1, we have allowed the user to configure the port.

So you should configure the port you are using for running minicom (minicom -s). The file minirc.prod_test_cfg, found inside projects/production_test/sw/config and the has the configuration information. So update this file with your settings (based on what serial port you are connecting) and that should be sufficient to run the UART test.

Here are the steps to be followed as far as UART testing is concerned

  1. dmesg | grep tty to identity the serial port which is going to be used for the UART test.
  2. Then you will have to update minirc.prod_test_cfg and based on this port.
  3. Follow the instructions as mentioned in the production test and the production test manual

If I were you, I would also try the production test of an earlier release where the ports were hardcoded (the test expects UART to be on /dev/ttyUSB0).This is just to identify if the issue is beyond the script environment.

Q6: What is the part number for the Samtec cable?

A: A loopback cable can be ordered from Part number is: HQDP-020-05.00-STL-SBR-2

For reference, the connector on the board has the following part number: QTH-020-01-F-D-DP-A

Q7: Why is the configuration interfaceSlaveselectMap not working in 16bit mode?

The upper 8bits of the 16bit data bus are incorrectly assigned on the board to FPGA, in other words there is a mistake on the PCB. However the interface operates perfectly in 8bit mode. The upshot of this is that the minimum configuration speed in roughly 80ms at a configuration frequency of 100MHz. Given a TPOR on the FPGA of 50ms this exceeds the theoretical limit of PCIe which requires all boards to be operational within 100ms after power-up. However in reality most servers allow for much more time such that we don't expect an issue. In particular the specified standard server operates perfectly even given the slightly longer power-up time, such that board is always instantly recognized.

Q8: Can I use the SamTec interface for my own purposes?

Yes, but be aware that Virtex 5 GTX transceiver clock compensation logic is broken in certain circumstances. Be sure to read Xilinx Answer Record #32164 for details. It is perhaps best to stick to Xilinx protocols like Aurora which avoid the problem.

Q9. Project implementation results report timing violation. How can I resolve the timing violation errors?

A: Constraints and options of all projects are optimized to meet timing closure. But, adding a new PCORE or logics to the project can cause of occurring setup violation. When users have timing issues, at first users need to look at the added designs whether they are created by using proper clock, signals, etc. If there are no problems, users can implement with different options in a file of xflow.opt that can be found in a directory /hw/nf10/ of each projects. In the options of the file, you can see mapping options like on below.

  # Options for Mapper
  # Type "map -h <arch>" for a detailed list of map command line options
  Program map
  -mt 4;                   # James: Use 4 cores if possible
  -o <design>_map.ncd;     # Output Mapped ncd file
  -w;			 # Overwrite output files.
  -pr b;                   # Pack internal FF/latches into IOBs
  #-fp <design>.mfp;       # Floorplan file
  -xe n;
  -ol high;
  #-cm speed;
  -t 7;
  -register_duplication on;
  -logic_opt on;
  <inputdir><design>.ngd;  # Input NGD file
  <inputdir><design>.pcf;  # Physical constraints file
  END Program map

Most of the options are optimized without giving any timing violations. Therefore, users don’t need to modify the options. However, implementation with different –t (Placer Cost Table) values are sometimes effective to elimination the timing errors. [The values are possible to change from 1 to 100.] ( Thus, if users can not find out any problems from additional cores and logics, implementation with different Placer Cost Table values will help to meet timing required.

Another useful tool for solving timing issues is SmartXplorer. Look at [UG688 - SmartXplorer for command line users] ( for examples on how to use SmartXplorer.

Q10: Why did my DMA Test fail ?

The result of the DMA test may dependent also on the spec of the machine on which the NetFPGA is running. Some users reported to have solved this issue by increasing their RAM resource. Other users have tried instructed the kernel to shut down its IOMMU, by writing an argument intel_iommu=no in grub configure. Please be very careful while configuring the grub, prior learning is suggested for novice users.

Q11: Why are some modules not supported for NetFPGA package ?

Some modules like AXI interconnect and Chipscope is not supported for Virtex5 FPGA's. But NetFPGA uses a teak to overcome the above issue.

Refer to line 61 in the below link

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