How to Create a Custom AXI IP

In many cases, you may have a logic block that needs to be transformed into AXI-compliant IP, either AXI4 Lite or AXI4 Stream. You can "wrap up' your logic block with a process we call "AXI'fication".

Unfortunately, according to Xilinx, "The EDK Create IP Wizard does not have examples until EDK 13.1". However, you have two ways of doing it by yourself.

1. You can visit the Xilinx Answer Record to download AXI IP examples and more information. After that, put your logic blocks into axi_/hdl/verilog or axi_/hdl/vhdl directories and wire them up to the AXI signals. Regarding the logic part of the AXI transaction model (functionalities of signals, timing etc), please visit ARM website.

2. If you prefer to use Xilinx IPIF rather than standard AXI, you can reuse Xilinx AXI-IPIF converter and use Xilinx IPIF interface. It is used by axi_uartlite, axi_timebase_wdt and other Xilinx AXI cores. To use this converter, you need to include axi_lite_ipif_v1_00_a in your PAO. For more information about IPIF, please visit Xilinx EDK documentation and search for "IPIF". If you don't know what IPIF is, don't bother. Please use approach 1) since it may be easier for you :-)

In the future EDK releases (13.1 according to Xilinx website), we should be able to run a "Peripheral Wizard" to generate a custom AXI IP easily, as what we do for the PLB. Go Xilinx!