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XAPP852 patch by Muhammad Shahbaz

mshahbaz edited this page Jan 23, 2013 · 2 revisions

XAPP852 patch for RLDRAM

Location

netfpga-10g/contrib-projects/rldram_xapp852

Description

This project implements a patch for simulating and running the Xilinx Application Note (XAPP852) - RLDRAM II Memory Interface for Virtex-5 FPGAs. The design targets the four CIO DDR RLDRAM II devices available on the NetFPGA-10G board. It operates the devices as a pair of two separate controllers (A & B) running at a clock rate of up to 300 MHz.

Steps to simulate and implement rldram_xapp852:

1.) Download the application note from Xilinx website (XAPP852)

  1. Copy verilog and Chipscope folders from the freshly downloaded XAPP852 to nf10_rldram_xapp852/

  2. Change directory to nf10_rldram_xapp852/ folder and apply the patch (nf10_rldram.patch)

    patch -d verilog/ < nf10_rldram.patch

Running Simulation

  1. Download the rldram2 memory model

  2. Copy rldram2.v and rldram2_parameters.vh into the nf10_rldram_xapp852/sim folder

  3. Run isim_run.bat under the sim/ folder

    sh ./isim_run.bat

Running Implementation

  1. Change directory to the run/ folder (Note: current clock speed - 250MHz)

  2. Run xtclsh run4rld_A run_process for RLDRAM A

    or

    run xtclsh run4rld_B run_process for RLDRAM B

If the "DEBUG" flag is enabled in the nf10_rldram_xapp852/nf10_defs.v file, the status signals can then be monitored using the chipsope. Use the "run.cdc" file under the run/ folder to view these signals.

The status code for PASS_FAIL bus are

RESET_CODE   = 3'b001;
PASS_CODE    = 3'b010; - you should see this code for happiness :-)    
ERROR_CODE   = 3'b100;
INVALID_CODE = 3'b111;
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